NCS2632 Datasheet by onsemi

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© Semiconductor Components Industries, LLC, 2013
October, 2013 Rev. 4
1Publication Order Number:
NCS2632/D
NCS2632
NOCAP], Pop-Free, 3 VRMS
Audio Line Driver with
Adjustable Gain
The NCS2632 is a popfree stereo line driver. It uses
ON Semiconductors patented NOCAP technology which allows the
elimination of the external DCblocking capacitors by providing
groundreferenced outputs through the generation of an internal
negative supply rail. The device can drive 3 VRMS into a 600 W load at
5 V power supply. By eliminating the two external heavy coupling
capacitors, the NOCAP approach offers significant space and cost
savings compared to similar audio solutions.
The NCS2632 has differential inputs and is available with an
external adjustable gain ranging from ±1 V/V to ±10 V/V. The gain is
adjusted with external resistors. The device can also be configured as a
2nd order low pass filter to complement DAC’s and SOC converters.
In addition to the NOCAP architecture, it contains specific circuitry to
prevent “Pop & Click” noise from occurring during Enable /
Shutdown transitions. The Signal-to-Noise Ratio reaches 105 dB,
offering high fidelity audio sound. The NCS2632 exhibits a high
power supply rejection with a typical value of 90 dB. This device also
features an UnderVoltage Protection (UVP) function which can be
adjusted using an external resistor bridge. The device is available in a
TSSOP14 package.
Features
NOCAP
Eliminates Pop/Clicks
Eliminates Output DCBlocking Capacitors –
Provides Flat Frequency Response 20 Hz – 20 kHz
Supply Voltage from 2.2 V to 5.5 V
Low Noise and THD
SNR = 105 dB
Typical Vn at 8 mVrms, AWeighted
THD+N < 0.001% at 1 kHz
Output Voltage into 600 W Load
2 VRMS with 3.3 V Supply Voltage
3 VRMS with 5 V Supply Voltage
Adjustable Gain from ± 1 V/V to ± 10 V/V
Differential Input
High PSRR: 90 dB
External UnderVoltage Detection Function
Enhanced Pop & Click Suppression Function
Offset Voltage ±400 mV
Outputs pass ±8 kV contact discharge according to
IEC6100042 under application conditions
Available in a TSSOP14 package
These Devices are PbFree, Halogen Free/BFR Free
and are RoHS Compliant
Applications
SetTop Boxes
PDP / LCD TV
Bluray Player, DVD Players
Home Theater in a Box
Laptops, Notebook PCs
MARKING
DIAGRAM
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A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= PbFree Package
1
14
TSSOP14
CASE 948G
NCS
2632
ALYWG
G
1
14
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
ORDERING INFORMATION
*For additional marking information, refer to
Application Note AND8473/D.
(*Note: Microdot may be in either location)
II + l —:l i 1 + . .. ."' j Figure 1. NCSZSBZ, Simplified Block D hllp://onsemi.com 2
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Charge
Pump
Circuitry
Click/Pop
Suppression
Circuitry
Bias
Circuitry
VDD INLP INLM
CP
CN
OUTL
OUTR
VSS INRMINRP
PGND
AGND
EN
AGND AGND
UVP
Figure 1. NCS2632, Simplified Block Diagram
1
2
3
4
5
6
7
14
13
12
11
10
9
8
INRP
INRM
OUTR
AGND
EN
VSS
CN CP
VDD
PGND
UVP
OUTL
INLM
INLP
Figure 2. NCS2632, Pinout
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PIN FUNCTION AND DESCRIPTION
Pin Name Type Description
1 INRP Input Right channel positive input
2 INRM Input Right channel negative input
3 OUTR Output Right channel output
4 AGND Ground Analog ground. Connect to PGND
5 EN Input Enable pin. Active High
6 VSS Power Negative rail output. Connected to ground through 1 mF low ESR ceramic reservoir capacitor.
7 CN Flying capacitor Negative terminal. Connected to CP through 1 mF low ESR ceramic capacitor.
8 CP Flying capacitor Positive terminal. Connected to CN through 1 mF low ESR ceramic capacitor.
9 VDD Power Power Supply Input
10 PGND Ground Power ground
11 UVP Input Undervoltage detection pin.
12 OUTL Output Left Channel Output
13 INLM Input Left channel negative input
14 INLP Input Left channel positive input
ABSOLUTE MAXIMUM RATINGS (Note 1)
Parameter Symbol Value Unit
Supply Voltage, VDD to GND VDD 0.3 to 5.5 V
Input Voltage VIVSS – 0.3 to VDD + 0.3 V
Minimum Load Impedance RL>600 W
Logic Pin Voltage (EN) –0.3 to VDD +0.3 V
Maximum Junction Temperature TJ(max) 40 to 150 °C
Storage Temperature Range TSTG 40 to 150 °C
ESD Capability (Note 2) Human Body Model
Machine Model
ESDHBM
ESDMM
2000
200
V
Latchup Current (Note 3) ILU 100 mA
Moisture Sensitivity Level (Note 4) MSL Level 1
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AECQ100002 (JEDEC standard: JESD22A114)
ESD Machine Model tested per AECQ100003 (JEDEC standard: JESD22A115)
3. Latchup Current tested per JEDEC standard: JESD78
4. Moisture Sensitivity Level tested per IPC/JEDEC standard: JSTD020A
THERMAL CHARACTERISTICS
Parameter Symbol Value Unit
JunctiontoAmbient Thermal Resistance, TSSOP14 (Note 5) qJA 115 °C/W
5. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate.
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
Supply Voltage with UVP connected to Ground VDD 2.2 3.3 5.5 V
HighLevel Input Voltage VIH (EN) 1.2 V
LowLevel Input Voltage VIL (EN) 0.4 V
Ambient Temperature TA40 85 °C
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ELECTRICAL CHARACTERISTICS, TA = 25°C (unless otherwise noted)
Parameter Symbol Test Conditions Min Typ Max Unit
Output Offset Voltage |VOS| VDD = 2.5 V to 5 V, Voltage follower gain = 1 100 400 mV
HighLevel Input Current (EN) |IIH| VDD = 5 V, VI = VDD 100 nA
LowLevel Input Current (EN) |IIL| VDD = 5 V, VI = 0 V 100 nA
Supply Current IDD VDD = 2.2 V, No load, EN = VDD 711 mA
VDD = 5.5 V, No load, EN = VDD 811 mA
Shutdown mode, VDD = 2.2 V to 5.5 V 60 500 nA
UnderVoltage Protection (UVP)
Threshold
VUVP 1.25 V
UVP Internal Hysteresis Current Source IHYS 5mA
Charge Pump Frequency fcp 400 kHz
OPERATING CHARACTERISTICS
VDD = 3.3 V, TA = 25°C, RL = 2.5 kW, CVSS = 1 mF, CIN = 10 mF, RIN = 10 kW, Rfb = 20 kW (unless otherwise noted)
Parameter Symbol Test Conditions Min Typ Max Unit
Output Voltage (Outputs In Phase)
VOTHD = 1%, VDD = 3.3 V, f = 1 kHz 2.05 Vrms
THD = 1%, VDD = 5 V, f = 1 kHz 3.05
THD = 1%, VDD = 5 V, f = 1 kHz, RL = 100 kW3.1
Total Harmonic Distortion plus Noise THD+N VO = 2 Vrms, f = 1 kHz 0.001 %
VO = 2 Vrms, f = 10 kHz 0.001 %
Power Supply Rejection PSRR VDD = 2.5 V to 5 V 90 dB
Crosstalk XTALK VO = 2 Vrms, f = 1 kHz 120 dB
Output Current Limit IOVDD = 3.3 V 21 mA
Input Resistor Range (Note 6) RIN 1 10 47 kW
Feedback Resistor Range (Note 6) Rfb 4.7 20 100 kW
Maximum Capacitive Load (Note 6) COUT 220 pF
Noise Output Voltage VNAweighted 8mVrms
Signal to Noise Ratio SNR VO = 2 Vrms, THD + N = 0.1% Aweighted
filter
105 dB
6. Guaranteed by design.
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TYPICAL CHARACTERISTICS
VDD = 3.3 V, TA = 25°C, RL = 2.5 kW, CVSS = 1 mF, CIN = 10 mF, RIN = 10 kW, Rfb = 20 kW (unless otherwise noted)
Figure 3. THD+N vs. Output Voltage over
Temperature, RL = 2.5 kW, VDD = 3.3 V, f = 1 kHz
Figure 4. THD+N vs. Output Voltage over
Temperature, RL = 2.5 kW, VDD = 5 V, f = 1 kHz
VOUT (V) VOUT (V)
1010.10.01
0.0001
0.001
0.01
0.1
1
10
1010.10.01
0.0001
0.001
0.01
0.1
1
10
Figure 5. THD+N vs. Output Voltage over
Supply, RL = 2.5 kW, f = 1 kHz
Figure 6. THD+N vs. Output Voltage over
Supply, RL = 600 W, f = 1 kHz
VOUT (V) VOUT (V)
1010.10.01
0.0001
0.001
0.01
0.1
1
10
1010.10.01
0.0001
0.001
0.01
0.1
1
10
Figure 7. THD+N vs. Frequency, RL = 2.5 kWFigure 8. THD+N vs. Frequency, RL = 600 W
FREQUENCY (Hz) FREQUENCY (Hz)
20,000200020020
0.0001
0.001
0.01
0.1
20,000200020020
0.0001
0.001
0.01
0.1
THD+N (%)
THD+N (%)
THD+N (%)
THD+N (%)
THD+N (%)
THD+N (%)
40°C
25°C
85°C
125°C
40°C
25°C
85°C
125°C
VDD = 2.0 V
VDD = 3.0 V
VDD = 3.3 V
VDD = 4.0 V
VDD = 4.2 V
VDD = 5.0 V
VDD = 5.5 V
VDD = 2.2 V
VDD = 3.0 V
VDD = 3.3 V
VDD = 3.6 V
VDD = 4.2 V
VDD = 5.0 V
VDD = 5.5 V
VDD = 5 V, VOUT = 3 V
VDD = 3.3 V, VOUT = 2 V
VDD = 2.2 V, VOUT = 1.4 V
VDD = 3.3 V, VOUT = 2.2 V
VDD = 5 V, VOUT = 3.3 V
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TYPICAL CHARACTERISTICS
VDD = 3.3 V, TA = 25°C, RL = 2.5 kW, CVSS = 1 mF, CIN = 10 mF, RIN = 10 kW, Rfb = 20 kW (unless otherwise noted)
Figure 9. Gain vs. Frequency,
RL = 2.5 kW
Figure 10. Gain vs. Frequency,
RL = 600 W
FREQUENCY (Hz) FREQUENCY (Hz)
20,000200020020
5.90
5.92
5.94
5.96
5.98
6.00
20,000200020020
5.90
5.92
5.94
5.96
5.98
6.00
Figure 11. Crosstalk vs. Frequency,
RL = 2.5 kW, VDD = 3.3 V, VO = 2 Vrms
Figure 12. Crosstalk vs. Frequency,
RL = 2.5 kW, VDD = 5 V, VO = 2 Vrms
FREQUENCY (Hz) FREQUENCY (Hz)
20,000200020020
140
120
80
60
40
0
20,000200020020
140
120
80
60
40
0
Figure 13. SignaltoNoise Ratio vs.
Frequency, RL = 2.5 kW
Figure 14. Power Supply Rejection Ratio vs.
Frequency, RL = 2.5 kW
FREQUENCY (Hz) FREQUENCY (Hz)
20,000200020020
0
20
80
120
20,000200020020
120
80
40
0
GAIN (dB)
GAIN (dB)
CROSSTALK (dB)
CROSSTALK (dB)
SNR (dB)
PSRR (dB)
VDD = 2.2 V, VOUT = 1.4 V
VDD = 3.3 V, VOUT = 2 V
VDD = 5 V, VOUT = 3 V VDD = 3.3 V, VOUT = 2 V
VDD = 5 V, VOUT = 3 V
100
20
100
20
40
60
100
VDD = 5 V, VOUT = 3 Vrms
VDD = 3.3 V, VOUT = 2 Vrms
100
60
20
VDD = 2.2 V
VDD = 3.3 V
VDD = 5 V
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TYPICAL CHARACTERISTICS
VDD = 3.3 V, TA = 25°C, RL = 2.5 kW, CVSS = 1 mF, CIN = 10 mF, RIN = 10 kW, Rfb = 20 kW (unless otherwise noted)
Figure 15. Quiescent Current vs. Temperature,
No Load, VI = 0 V, EN = High
Figure 16. VSS vs. Temperature
TEMPERATURE (°C) TEMPERATURE (°C)
852540
6.0
6.5
7.0
7.5
8.0
8.5
12550050
0
1
2
4
5
6
Figure 17. Startup TurnOn Time, RL = 2.5 kW,
VDD = 5 V
Figure 18. Shutdown TurnOff Time,
RL = 2.5 kW, VDD = 5 V
Figure 19. Startup TurnOn Time, RL = 2.5 kW,
VDD = 3.3 V
Figure 20. Shutdown TurnOff Time,
RL = 2.5 kW, VDD = 3.3 V
SUPPLY CURRENT (mA)
VSS (V)
VDD = 2.2 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 5.5 V
25 25 75 100
3
VDD = 3.3 V
VDD = 5 V
EN
OUT
VSS
tON 650 ms
EN
OUT
VSS
tON 550 ms
EN
OUT
VSS
tOFF 80 ms
EN
OUT
VSS
tOFF 100 ms
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APPLICATION INFORMATION
DESCRIPTION
The NCS2632 is a stereo line driver with a NOCAP
architecture. This architecture eliminates the need to use two
large, external capacitors required by conventional audio
line driver applications. The NCS2632 is basically
composed of two true ground amplifiers with internal power
supply rail, one UVPcircuit block, and shortcircuit
protection. The gain of the NCS2632 can be adjusted with
two external resistors.
The NOCAP approach is a patented architecture that
requires only two 1 mF low ESR ceramic capacitors (fly
capacitor and reservoir capacitor). It generates a
symmetrical positive and negative voltage and it allows the
output of the amplifiers to be biased around the ground (True
Ground).
The NCS2632 includes a special circuitry for eliminating
any pop and click noise during turn on and turn off time. This
circuitry combined with the true ground output architecture
and a trimmed output offset voltage makes the elimination
of pop and click particularly efficient.
UNDERVOLTAGE PROTECTION (UVP) PIN
MANAGEMENT
The UVP pin can be used to shut down the audio line
driver by monitoring the board’s main power supply. Then
the line driver can be shut down before upstream devices
disable, contributing this way to eliminate potential source
of pop noise.
The device shuts down when the UVP voltage goes below
1.25 V typically. To monitor the lower main power supply
limit, an external voltage divider constituted with three
resistors, RUP, RDW and RHYS is used (Figure 21).
Resistors values have to be chosen based on the requested
power supply shutdown threshold and hysteresis for a given
application. It is recommended to have RHYS >> RDW //
RUP. RHYS is optional in the case where hysteresis is not
necessary.
UVP
Board Main
Power Suppply
RUP
RDW
PVDD
RHYS
Vn
IHYS
On/Off
Figure 21. Voltage Divider Connected to UVP for
Power Supply Monitoring
PVDD Shmduwn Threshold PVDD Hvflcfcsis PVDD Hvsmfc 5 Sim lificd PVDD H slcmsh ussumin ‘ RYS >> RDW RUP RUP and RDW RHYS
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When the resistor divider is connected to the pin UVP as shown in Figure 21, the UVP pin voltage is a function of PVDD
and IHYS according to the below equation:
VUVP +PVDD RDW
RDW )RUP )ǒRHYS RDW RUP
RDW )RUPǓ IHYS (eq. 1)
With VUVPth = 1.25 V and IHYS = 5 mA
This gives a PVDD Shutdown threshold.
PVDD Shutdown Threshold:
PVDDSD +VUVPth RDW )RUP
RDW *IHYS ǒRHYS )RDW RUP
RDW )RUPǓ RDW )RUP
RDW (eq. 2)
Simplified PVDD Shutdown threshold assuming RHYS >> RDW // RUP:
PVDDSD +ǒVUVPth *IHYS RHYSǓ RDW )RUP
RDW (eq. 3)
The PVDD Startup threshold is given by the below equation.
PVDD Hysteresis:
PVDDUP +VUVPth RDW )RUP
RDW (eq. 4)
The hysteresis component is:
PVDD Hysteresis:
DPVDD +VHYS +IHYS ǒRHYS )RDW RUP
RDW )RUPǓ RDW )RUP
RDW
(eq. 5)
+IHYS ǒRHYS )RDW RUP
RDW )RUPǓ
PVDDUP
VUVPth
Simplified PVDD Hysteresis assuming RYS >> RDW // RUP:
DPVDD +VHYS +IHYS RHYS RDW )RUP
RDW +IHYS RYS
PVDDUP
VUVPth
(eq. 6)
For a given PVDD threshold RUP will be a function of RDW.
RUP and RDW:
RUP +ǒPVDDUP
VUVPth
*1Ǔ RDW (eq. 7)
According to Equation 6, assuming RHYS >> RDW // RUP, and for a given hysteresis VHYS and PVDD threshold, RHYS is:
RHYS
RHYS +
VHYS VUVPth
IHYS PVDDUP
+
1.25 VHYS
5mA PVDDUP
(eq. 8)
For example, to get PVDDSD = 2.5 V and 0.625 V hysteresis,
Power Divider Resistors have to be: RUP = 1.5 kW, RDW = 1 kW and RHYS = 51 kW
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GAIN SETTING RESISTOR SELECTION (RIN and RFB)
RIN and RFB set the closedloop gain of the amplifier. The
resistor values have to be chosen so that amplifier stability
is preserved. A low gain configuration (close to 1)
minimizes the THD + noise values and maximizes the signal
to noise ratio.
A closedloop gain in the range of 1 to 10 is recommended
to optimize overall system performance.
Selecting values that are too low requires a relatively large
input ac-coupling capacitor, CIN. Selecting values that are
too high increases the overall noise of the amplifier.
CIN
CIN
RIN
RIN
RFB
RFB
Vout
Vin+
Vin
Av +Vout
Vin+ *Vin+
RFB
Rin
(eq. 9)
Figure 22. Differential Input Gain Configuration
CIN RIN
RFB
Vin
Vout
Av +Vout
Vin+
RFB
RIN
(eq.
10)
Figure 23. Inverting Gain Configuration
CIN
CIN
RIN
Rx
Vout
Vin+
RFB
Av +
Vout
Vin+ +1)
RFB
RIN
(eq. 11)
Figure 24. NonInverting Gain Configuration
4w 4w
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Table 1. RECOMMENDED RESISTOR VALUES
Input Resistor Val-
ue, RIN
Feedback Resistor Val-
ue, RFB Differential Input Gain Inverting Input Gain
Non Inverting Input
Gain
22 kW22 kW1.0 V/V –1.0 V/V 2.0 V/V
22 kW33 kW1.5 V/V –1.5 V/V 2.5 V/V
33 kW68 kW2.06 V/V –2.06 V/V 3.1 V/V
10 kW100 kW10.0 V/V –10.0 V/V 11.0 V/V
INPUT CAPACITOR
The input coupling capacitor blocks the DC voltage at the
amplifier input terminal. This capacitor creates a highpass
filter with RIN. The size of the capacitor must be large
enough to couple at low frequencies without severe
attenuation in the audio bandwidth (20 Hz 20 kHz).
The cut off frequency for the input highpass filter is:
fc+1
2pRinCin
(eq. 12)
A fc < 20 Hz is recommended.
CHARGE PUMP CAPACITOR SELECTION
It is recommended to use ceramic capacitors with low
ESR for better performances. X5R or X7R capacitors are
recommended. The flying capacitor Cfly (1 mF) serves to
transfer charge during the generation of the negative
voltage. The VSS reservoir capacitor CVSS must be equal at
least to the Cfly capacitor to allow maximum charge transfer.
The 1 mF capacitors have to be connected as close as
possible to the corresponding pins.
Lower value capacitors can be used but the device may not
operate to specifications.
POWER SUPPLY DECOUPLING CAPACITORS
The NCS2632 is a True Ground amplifier that requires an
adequate decoupling capacitor on VDD to reduce noise and
THD+N. Use a X5R / X7R ceramic capacitor and place it
close to the VDD pin. A value of 1mF is recommended. For
filtering lower frequency noise signals, a 10 mF or greater
capacitor placed near the audio power amplifier would also
help.
SHUTDOWN FUNCTION
The device enters shutdown mode when Enable signal is
low. During the shutdown mode, the internal charge pump
is shut down, and the DC quiescent current of the circuit does
not exceed 500 nA. The output is pulled to ground through
a low output impedance of about 40 ohms.
USING THE NCS2632 AS A 2nd ORDER FILTER
Audio DACs can require an external low-pass filter to
remove out-of-band noise. This is possible with the
NCS2632, which can be used as a standard Operational
Amplifier with the advantage of better performances
including “pop & click” noise behavior.
Single-ended and differential topologies can be
implemented. In Figures 25 and 26, a Multiple-FeedBack
(MFB) topoplogy, with differential inputs and single-ended
inputs is shown. The two topologies use AC-Coupling
capacitors (CIN) to block the DC-signal component coming
from the source; they contribute to reducing the output offset
voltage.
RIN
RIN
CIN
CIN
Vin
Vin+
CDIFF
CINT
RFB
RFB
CINT
RINT
RINT
Vout
Figure 25. 2nd Order Active Low Pass Filter Differential Input
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RIN
CIN
Vin
CT
CINT
RFB
RINT
Vout
Figure 26. 2nd Order Active Low Pass Filter Inverting Input
INITIALIZATION AND POPFREE POWER UP/DOWN
For an on/off/on power sequence, VDD is required to be
ramped down to 0 V before ramping back up for power on
(shown in Figure 27). This ensures that the NCS2632
internal circuits are properly initialized to guarantee an
optimal output.
Popfree powerup/down is ensured by keeping EN
(Enable pin) low during power supply rampup or
rampdown. The EN pin should be kept low until the input
accoupling capacitors are fully charged before asserting
the EN pin high; this way, proper precharge of the
accoupling is performed, and popfree powerup is
achieved. Figure 27 illustrates the preferred sequence.
Figure 27. Initialization and Power Up/Down Sequence
VDD
Rampup
VSS
(Negative Rail)
0V
0V
+VDD
VDD
Internal VSS
Supply
VDD
Supply
EN
VDD
Rampdown
VSS
Dtcharge Dtdischarge
ACcoupled
Input Capacitor
PreCharge Time
Capacitor
Discharge
CAPACITIVE LOAD
The NCS2632 has the ability to drive a high capacitive
load up to 220 pF directly. Higher capacitive loads can be
accepted by adding a series resistor of 10 W or larger.
ESD PERFORMANCE
From the system level perspective, the outputs of the
NCS2632 are rated to Level 4 of the IEC6100042 ESD
standard. Using the contact discharge method, the outputs
pass a ±8 kV discharge with an RC network of R = 33 ohms
and C = 1 nF at each output to simulate the application
environment.
1 7, g .— Regulaled VDD _ 3.3V/5.0V G 4 OU'IL EN + CF '_ l g J— Charge 8' Click/Pop UVP 1 —— Pump 0' mi Suppresswon _3— Circuitry ”CL" ry Circuim/ CN AGND Ag“, E PGND ' .— + OUTR AGND .L I!) A 1 _J_ '— ‘I T L INRP INRM —— || || hllp://onsemi.com 13
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APPLICATION SCHEMATIC
Charge
Pump
Circuitry
Click/Pop
Suppression
Circuitry
Bias
Circuitry
INLP INLM
CP
CN
OUTL
OUTR
INRMINRP
PGND
AGND
EN
AGND AGND
UVP
Regulated
3.3V/5.0 V
VDD
VSS
Board Main
Power Suppply
ENABLE
RIGHT
INPUT
+
LEFT
INPUT
1mF
+
C1
C1
R1
R1
R2
R2
C2
C3
R3
R3
C3
R1
R1
C1
C1
C3 R3
R2
R2
C2
RUP
RDW
R3
C3
1mF
1mF
LEFT
OUTPUT
RIGHT
OUTPUT
R1 = R2 = R3 = 5.6 kW, C1 = 100 nF, C2 = 470 pF, C3 = 220 pF
Figure 28. Application Schematic
ORDERING INFORMATION
Device Package Shipping
NCS2632DTBR2G TSSOP14
(PbFree)
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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PACKAGE DIMENSIONS
TSSOP14
CASE 948G
ISSUE B
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.50 0.60 0.020 0.024
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE W.
____
S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V S
T
LU
SEATING
PLANE
0.10 (0.004)
T
SECTION NN
DETAIL E
JJ1
K
K1
DETAIL E
F
M
W
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
V
14X REFK
N
N
7.06
14X
0.36 14X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
m J and
NCS2632
http://onsemi.com
15
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