IDT8N4SV76 ~ Datasheet by Renesas Electronics America Inc

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DATASHEET
LVDS Frequency-Programmable VCXO IDT8N4SV76
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IDT8N4SV76CCD
REVISION B NOVEMBER 20, 2013 1 ©2013 Integrated Device Technology, Inc.
General Description
The IDT8N4SV76 is an LVDS Frequency-Programmable VCXO with
very flexible frequency and pull-range programming capabilities. The
device uses IDT’s fourth generation FemtoClock® NG technology for
an optimum of high clock frequency and low phase noise
performance. The device accepts 2.5V or 3.3V supply and is
packaged in a small, lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm
x 1.55mm package.
The device can be factory-programmed to any frequency in the
range of 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz
to the very high degree of frequency precision of 218Hz or better.
The extended temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements.
Features
Fourth generation FemtoClock® NG technology
Programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
Frequency programming resolution is 218Hz and better
Factory-programmable VCXO pull range and control voltage
polarity
Absolute pull-range (APR) programmable from ±4.5 to
±754.5ppm
One 2.5V or 3.3V LVDS clock output
Output enable control input, LVCMOS/LVTTL compatible
RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.53ps (typical)
2.5V or 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm
package
IDT8N4SV76
6-lead ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
Pin Assignment
Block Diagram
Q
nQ
OSC
114.285 MHz
÷MINT, MFRAC
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz
÷N
Configuration Register (ROM)
(Frequency, Pull-range, Polarity)
25 7
VC
nOE
A/D 7
Pulldown
2
÷P6V
DD
5nQ
4Q
VC 1
nOE 2
GND 3
IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO
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Pin Description and Characteristic Tables
NOTE: Pulldown refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.
Function Tables
nOE
0 (default) Outputs are enabled.
1 Outputs Q, nQ are in high-impedance state.
.
NOTE: Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of
218Hz or better.
Table 1. Pin Descriptions
Number Name Type Description
1 VC Input VCXO Control Voltage input.
2 nOE Input Pulldown Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface
levels.
3 GND Power Power supply ground.
4, 5 Q, nQ Output Differential clock output pair. LVDS interface levels.
6VDD Power Power supply pin.
Table 2. Pin Characteristics
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance nOE 5.5 pF
VC 10 pF
RPULLDOWN Input Pulldown Resistor 50 k
Table 3A. nOE Configuration
Input
Output Enable
Table 3B. Output Frequency Range
15.476MHz to 866.67MHz
975MHz to 1,300MHz
FEW {]
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Block Diagram with Factory-Configuration Registers
Q
nQ
OSC
114.285MHz
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz
÷N
VC
nOE
Pulldown
Feedback Divider M (25 Bit)
MINT
(7 bits)
MFRAC
(18 bits)
Factory - Programming Registers
ADC_GAIN ADC_POL
I2C: 6 bits 1 bit
Def: 6 bits 1 bit
P MINT MFRAC
I2C: 2 bits 7 bits 18 bits
Def: 2 bits 7 bits 18 bits 34
7
34
7
18
Output Divider N
A/D
7
7
41
÷P
2
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Principles of Operation
The block diagram consists of the internal 3rd overtone crystal and
oscillator which provide the reference clock fXTAL of 114.285MHz.
The PLL includes the FemtoClock® VCO along with the Pre-divider
(P), the feedback divider (M) and the post divider (N). The P,M, and
Ndividers determine the output frequency based on the fXTAL
reference. The feedback divider is fractional supporting a huge
number of output frequencies. Internal registers are used to hold up
the factory pre-set configuration setting. The P,M, and Nfrequency
configurations support an output frequency range 15.476MHz to
866.67MHz and 975MHz to 1,300MHz.
The devices use the fractional feedback divider with a delta-sigma
modulator for noise shaping and robust frequency synthesis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator. The output frequency
is determined by the 2-bit pre-divider (P), the feedback divider (M)
and the 7-bit post divider (N). The feedback divider (M) consists of
both a 7-bit integer portion (MINT) and an 18-bit fractional portion
(MFRAC) and provides the means for high-resolution frequency
generation. The output frequency fOUT is calculated by:
fOUT fXTAL
1
PN
-------------MINT MFRAC 0.5+
218
-------------------------------------+=
Frequency Configuration
An order code is assigned to each frequency configuration and the
VCXO pull-range programmed by the factory (default frequencies).
For more information on the available default frequencies and order
codes, please see the Ordering Information Section in this document.
For available order codes, see the FemtoClock NG Ceramic-Package
XO and VCXO Ordering Product Information document.
For more information on programming capabilities of the device for
custom frequency and pull-range configurations, see the FemtoClock
NG Ceramic 5x7 Module Programming Guide.
l) 65“ on
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Supply Voltage, VDD 3.63V
Inputs, VI-0.5V to VDD + 0.5V
Outputs, IO(LVDS)
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, JA 49.4C/W (0 mps)
Storage Temperature, TSTG -65Cto150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA= -40°C to 85°C
Table 4B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA= -40°C to 85°C
Table 4C. LVCMOS/LVTTL DC Characteristic, VDD = 3.3V ± 5% or 2.5V ± 5%, TA= -40°C to 85°C
Item Rating
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Power Supply Voltage 3.135 3.3 3.465 V
IDD Power Supply Current 140 175 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Power Supply Voltage 2.375 2.5 2.625 V
IDD Power Supply Current 135 170 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage VDD = 3.3V 2 VDD + 0.3 V
VDD = 2.5V 1.7 VDD + 0.3 V
VIL Input Low Voltage VDD = 3.3V -0.3 0.8 V
VDD = 2.5V -0.3 0.7 V
IIH Input High Current nOE VDD =V
IN = 3.465V or 2.625V 150 µA
IIL Input Low Current nOE VDD = 3.465V or 2.625V, VIN =0V -5 µA
IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO
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Table 4D. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA= -40°C to 85°C
Table 4E. LVDS DC Characteristics, VDD = 2.5V ± 5%, TA= -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD Differential Output Voltage 247 330 454 mV
VOD VOD Magnitude Change 50 mV
VOS Offset Voltage 1.14 1.23 1.31 V
VOS VOS Magnitude Change 50 mV
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD Differential Output Voltage 247 320 454 mV
VOD VOD Magnitude Change 50 mV
VOS Offset Voltage 1.13 1.22 1.30 V
VOS VOS Magnitude Change 50 mV
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AC Electrical Characteristics
Notes are continued on next page.
Table 5A. AC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA= -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fOUT Output Frequency Q, nQ 15.476 866.67 MHz
975 1,300 MHz
fIInitial Accuracy Measured @ 25°C, VC=V
DD/2 ±10 ppm
fSTemperature Stability
Option code=AorB ±100 ppm
Option code=EorF ±50 ppm
Option code=KorL ±20 ppm
fAAging Frequency drift over 10 year life ±3 ppm
Frequency drift over 15 year life ±5 ppm
fTTotal Stability
Option code A, B (10 year life) ±113 ppm
Option code E, F (10 year life) ±63 ppm
Option code K, L (10 year life) ±33 ppm
tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 6 14 ps
tjit(per) Period Jitter; NOTE 1 4 6 ps
tjit(Ø) RMS Phase Jitter (Random);
NOTE 2,3
156.25MHz, Integration Range:
12kHz - 20MHz 0.53 0.73 ps
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2,3
fXTAL = 114.285mhz
500MHz < fOUT 1300MHz0.46 0.67 ps
100MHz < fOUT 500MHz0.48 0.63 ps
15MHz fOUT 100MHz0.76 1.4 ps
N(100)
Single-side Band Phase
Noise,
100Hz from Carrier
156.25MHz -67 dBc/Hz
N(1k) Single-side Band Phase
Noise, 1kHz from Carrier 156.25MHz -89 dBc/Hz
N(10k) Single-side Band Phase
Noise, 10kHz from Carrier 156.25MHz -113 dBc/Hz
N(100k) Single-side Band Phase
Noise, 100kHz from Carrier 156.25MHz -118 dBc/Hz
N(1M) Single-side Band Phase
Noise, 1MHz from Carrier 156.25MHz -127 dBc/Hz
N(10M) Single-side Band Phase
Noise, 10MHz from Carrier 156.25MHz -137 dBc/Hz
PSNR Power Supply Noise
Rejection
50mV Sinusoidal Noise
1kHz - 50MHz -58.7 dBc
tR/t
FOutput Rise/Fall Time 20% to 80% 80 500 ps
odc Output Duty Cycle 45 55 %
tSTARTUP
Device Startup Time after
Power-up 15 ms
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NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
Notes continued on next page.
NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing.
NOTE: Characterized with VC=V
DD/2.
NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing.
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.
NOTE 2: Please refer to the phase noise plots.
NOTE 3: Please see the FemtoClock NG Ceramic 5x7 Modules Programming guide for more information on PLL feedback modes and the
optimum configuration for phase noise.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: VC= 10% to 90% of VDD.
NOTE 2: Nominal oscillator gain: Pull range divided by the control voltage tuning range of 3.3V. E.g. for ADC_GAIN [6:0] = 000001 the pull
range is ± 12.5ppm, resulting in an oscillator gain of 25ppm ÷ 3.3V = 7.57ppm/V.
NOTE 3: For best phase noise performance, use the lowest KVthat meets the requirements of the application.
NOTE 4: BSL = Best Straight Line Fit: Variation of the output frequency vs. control voltage VC, in percent. VCranges from 10% to 90% VDD.
Table 5B. VCXO Control Voltage Input (VC) Characteristics, VDD =3.3V±5%or 2.5V±5,T
A= -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
KV
Oscillator Gain, NOTE 1, 2, 3 VDD = 3.3V 7.57 477.27 ppm/V
Oscillator Gain, NOTE 1, 2, 3 VDD = 2.5V 10 630 ppm/V
LVC
Control Voltage Linearity;
NOTE 4 BSL Variation -1 ±0.1 +1 %
BW Modulation Bandwidth 100 kHz
ZVC VC Input Impedance 500 k
VCNOM Nominal Control Voltage VDD/2 V
VC
Control Voltage Tuning
Range; NOTE 4 0V
DD V
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IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO
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Typical Phase Noise at 156.25MHz (12kHz - 20MHz)
Noise Power (dBc/Hz)
Offset Frequency (Hz)
509 50:2 500 50g! Phase Noise Plot Nmse Powev Oflse‘ Frequency v RMS Phase Jiner : ‘ ‘ 5 7‘ I Area Undev Curve D ned by me Oilsel Fvequency Mavkers
IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO
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Parameter Measurement Information
2.5V LVDS Output Load AC Test Circuit
RMS Phase Jitter
Cycle-to-Cycle Jitter
3.3V LVDS Output Load AC Test Circuit
Period Jitter
Output Duty Cycle/Pulse Width/Period
SCOPE
Q
nQ
2.5V±5%
POWER SUPPL
+Float GND
VDD
nQ
Q
tcycle n tcycle n+1
tjit(cc) = tcycle n tcycle n+1
1000 Cycles
SCOPE
Q
nQ
3.3V±5%
POWER SUPPL
+Float GND
VDD
VOH
VREF
VOL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1σcontains 68.26% of all measurements
2σcontains 95.4% of all measurements
3σcontains 99.73% of all measurements
4σcontains 99.99366% of all measurements
6σcontains (100-1.973x10-7)% of all measurements
Histogram
tPW
tPERIOD
tPW
tPERIOD
odc = x 100%
nQ
Q
DC Inpm
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Parameter Measurement Information, continued
Output Rise/Fall Time
Differential Output Voltage Setup
Offset Voltage Setup
20%
80% 80%
20%
tRtF
VOD
nQ
Q
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Applications Information
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90and 132. The actual
value should be selected to match the differential impedance (Z0)of
your transmission line. A typical point-to-point LVDS design uses a
100parallel resistor at the receiver and a 100differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
standard termination schematic as shown in Figure 1A can be used
with either type of output structure. Figure 1B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
LVDS
Driver
LVDS
Driver
LVDS
Receiver
LVDS
Receiver
ZT
C
ZOZT
ZOZT
ZT
2
ZT
2
Figure 1A. Standard Termination
Figure 1B. Optional Termination
LVDS Termination
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IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO
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Schematic Layout
Figure 2 shows an example of IDT8N4SV76 application schematic.
In this example, the device is operated at VDD = 3.3V. As with any
high speed analog circuitry, the power supply pins are vulnerable to
random noise. To achieve optimum jitter performance, power supply
isolation is required.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1µF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10 kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure that the logic control inputs are
properly set.
Figure 2. IDT8N4SV76 Application Schematic
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Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8N4SV76.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the IDT8N4SV76 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)MAX =V
CC_MAX *I
EE_MAX = 3.465V * 175mA = 606mW
Power (outputs)MAX =30mW/Loaded Output pair
Total Power_MAX (3.3V, with all outputs switching) = 606mW + 30mW = 636.38mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 49.4°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.636W * 49.4°C/W = 116.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance JA for 6 Lead Ceramic VFQFN, Forced Convection
JA by Velocity
Meters per Second 012
Multi-Layer PCB, JEDEC Standard Test Boards 49.4°C/W 44.2°C/W 42.1°C/W
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Reliability Information
JA vs. Air Flow
Meters per Second 012
Multi-Layer PCB, JEDEC Standard Test Boards 49.4°C/W 44.2°C/W 42.1°C/W
Transistor Count
The transistor count for IDT8N4SV76 is: 47,414
Table 7. JA vs. Air Flow Table for a 6-lead Ceramic 5mm x 7mm Package
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Package Outline and Package Dimensions
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Ordering Information for FemtoClock NG Ceramic-Package XO and VCXO Products
The programmable VCXO and XO devices support a variety of
devices options such as the output type, number of default frequen-
cies, internal crystal frequency, power supply voltage, ambient
temperature range and the frequency accuracy. The device options,
default frequencies and default VCXO pull range must be specified at
the time of order and are programmed by IDT before the shipment.
Table 8 specifies the available order codes, including the device
options, the default frequency codes can be obtained from the
FemtoClock NG Ceramic-Package XO and VCXO Ordering Product
Information document. Example part number: the order code
8N4SV76FC-0001CDI specifies a programmable, quad
default-frequency VCXO with a voltage supply of 2.5V, a LVPECL
output, a 50 ppm crystal frequency accuracy, contains a
114.285MHz internal crystal as frequency source, industrial
temperature range, a lead-free (6/6 RoHS) 6-lead ceramic 5mm x
7mm x 1.55mm package and is factory-programmed to the default
frequencies of 100MHz, 122.88MHz, 125MHz and 156.25MHz and
to the VCXO pull range of min. 100 ppm.
Other default frequencies and order codes are available from IDT on
request.
Table 8. Order Codes
Shipping Package
8: Tape & Reel
(no letter): Tray
Ambient Temperature Range
I”: Industrial: (TA= -40°C to 85°C)
(no letter) : (TA= 0°C to 70°C)
Package Code
CD: Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm
Die Revision
C(opt. 208)
Option Code (Supply Voltage and Frequency-Stability)
A:V
CC = 3.3V±5%, ±100ppm
B:V
CC = 2.5V±5%, ±100ppm
E:V
CC = 3.3V±5%, ±50ppm
F:V
CC = 2.5V±5%, ±50ppm
K:V
CC = 3.3V±5%, ±20ppm
L:V
CC = 2.5V±5%, ±20ppm
Default-Frequency and VCXO Pull Range
See document FemtoClock NG Ceramic-Package XO and VCXO
Ordering Product Information.
Last digit = L: configuration pre-programmed and not
changeable
dddd fXTAL (MHz) PLL feedback Use for
0000 to 0999 114.285 Fractional VCXO, XO
1000 to 1999 100.000 Integer XO
2000 to 2999 Fractional XO
FemtoClock NG
I/O Identifier
0: LVCMOS
3: LVPECL
4: LVDS
Number of Default Frequencies
S: 1: Single
D: 2: Dual
Q: 4: Quad
Part Number
Function #pins OE fct. at
pin
001 XO 10 OE@2
003 XO 10 OE@1
V01 VCXO 10 OE@2
V03 VCXO 10 OE@1
V75 VCXO 6 OE@2
V76 VCXO 6 nOE@2
V85 VCXO 6
085 XO 6 OE@1
270 XO 6 OE@1
271 XO 6 OE@2
272 XO 6 nOE@2
273 XO 6 nOE@1
8N X X XXX X X - dddd XX X X
NOTE: For order information, also see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document.
Part/Order Number
IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO
Factory Datasheet. Contains Confidential Information. Do not send to customers.
Factory Datasheet. Contains Confidential Information. Do not send to customers.
IDT8N4SV76CCD
REVISION B NOVEMBER 20, 2013 18 ©2013 Integrated Device Technology, Inc.
Table 9. Device Marking
Marking
Industrial Temperature Range (TA= -40°C to 85°C) Commercial Temperature Range (TA= 0°C to 70°C)
IDT8N4SV76yC-
ddddCDI
IDT8N4SV76yC-
ddddCD
y= Option Code, dddd=Default-Frequency and VCXO Pull Range
IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO
Factory Datasheet. Contains Confidential Information. Do not send to customers.
Factory Datasheet. Contains Confidential Information. Do not send to customers.
IDT8N4SV76CCD
REVISION B NOVEMBER 20, 2013 19 ©2013 Integrated Device Technology, Inc.
Revision History Sheet
Rev Table Page Description of Change Date
A
T7
5
14
15
Absolute Maximum Ratings - Thermal Impedance changed from 41.4 to 41.9.
Power Considerations - corrected Thermal Resistance table and updated calculations.
Reliability Information - corrected thermal table.
4/25/12
B
T4D
T4E
6
6
3.3V LVDS DC Characteristics Table - updated specs.
2.5V LVDS DC Characteristics Table - updated specs.
Per PCN #N1206-02.
8/22/12
B 5A 7 RMS Phase Jitter, Test Conditions, corrected typos for 500MHz and 100MHz; ”to“” 11/20/2013
0ID'IZ www.lDT.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi-
cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2013. All rights reserved.
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San Jose, California 95138
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Fax: 408-284-2775
www.IDT.com/go/contactIDT
Technical Support Sales
netcom@idt.com
+480-763-2056
We’ve Got Your Timing Solution
IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO
Factory Datasheet. Contains Confidential Information. Do not send to customers.

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