MAX14611 Datasheet by Analog Devices Inc./Maxim Integrated

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MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
Typical Operating Circuit
19-6276; Rev 0; 4/12
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX14611.related.
General Description
The MAX14611 is a quad bidirectional logic-level transla-
tor that provides the level shifting necessary to allow data
transfer in a multivoltage system. Externally applied volt-
ages, VCC and VL, set the logic levels on either side of
the device. A low-voltage logic signal present on the VL
side of the device appears as a high-voltage logic signal
on the VCC side of the device, and vice-versa.
The device is ideal for I2C bus as well as MDIO bus appli-
cations where open-drain operation is often required. The
device features a three-state output mode (TS). Drive TS
high to connect the pullup to the powered I/O port. This
allows for continuous, undisrupted I2C operation on the
powered side of the device while the level translation
function is off. The MAX14611 is a pin-to-pin compatible
upgrade to the MAX3378E in the TDFN package.
The MAX14611 features enhanced high-electrostatic-
discharge (ESD) protection on all I/OVCC_ ports up to
±6kV HBM. The device operates over the -40NC to +85NC
extended temperature range and is available in 3mm x
3mm, 14-pin TDFN and 4.9mm x 5.1mm, 14-pin TSSOP
packages.
Applications
Benefits and Features
S Improved Interoperability
Meets I2C Specifications
10kI Internal Pullup Resistor
Pin-to-Pin Compatible with the MAX3377E and
the MAX3378E
0.9V Operation on Low Voltage Supply
S Robust Logic-Level Translation
±0.5V Tolerances on All Pins
±6kV Human Body Model ESD Protection on
I/OVCC_ Lines
Thermal Short-Circuit Protection
Short to Ground Fault Protection on All Pins
-40NC to +85NC Operating Temperature Range
S Increased Design Flexibility
Ultra-Low Supply Current
Pullup Resistor Enabled with a Single Power
Supply when TS = High
10I (max) Transmission Gate FET
Small, 14-Pin, 3.0mm x 3.0mm TDFN Package
and 14-Pin, 4.9mm x 5.1mm TSSOP Package
EVALUATION KIT AVAILABLE
SPI, I2C, and MDIO
Level Translation
Low-Voltage ASIC
Level Translation
Portable Electronics
Mobile Phones
POS Systems
Telecommunications
Equipment
I/OVL_DATA
TS
+1.8V +3.3V
VLVCC
+3.3V
SYSTEM
DATA
I/OVCC_
+1.8V SYSTEM
CONTROLLER
0.1µF 1µF
MAX14611
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
2Maxim Integrated
(All voltages referenced to GND.)
VCC .......................................................................... -0.5V to +6V
VL ..........................................................................-0.5V to +5.5V
TS ............................................................................-0.5V to +6V
I/OVCC_ .................................................... -0.5V to (VCC + 0.5V)
I/OVL_ .......................................................... -0.5V to (VL + 0.5V)
Short-Circuit Duration I/OVL_, I/OVCC_ to GND .......Continuous
Continuous Current ......................................................... Q50mA
Continuous Power Dissipation (TA = +70NC)
TDFN (derate 24.4mW/NC above +70NC) ...............1951.2mW
TSSOP (derate 10mW/NC above +70NC) ................. 796.8mW
Operating Temperature Range .......................... -40NC to +85NC
Maximum Junction Temperature .....................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) .....................................+260NC
TDFN-EP
Junction-to-Ambient Thermal Resistance (qJA) ........... 41°C/W
Junction-to-Case Thermal Resistance (qJC) ..................8°C/W
TSSOP
Junction-to-Ambient Thermal Resistance (qJA ) ...... 100.4°C/W
Junction-to-Case Thermal Resistance (qJC) ................30°C/W
ABSOLUTE MAXIMUM RATINGS
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
ELECTRICAL CHARACTERISTICS
(VCC = +1.65V to +5.5V, VL = 0.9V to the lesser of VCC + 0.3V and 5V. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical
values are at VCC = +3.3V, VL = +1.8V, TA = +25NC, unless otherwise noted.) (Notes 2, 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLIES
VL Supply Range VL0.9 5 V
VCC Supply Range VCC 1.65 5.5 V
VL Supply Current IVL I/OVCC_ = VCC, I/OVL_ = VL, TS = VL1FA
VCC Supply Current IVCC I/OVCC_ = VCC, I/OVL_ = VL, TS = VL35 FA
VCC Shutdown Mode Supply
Current ISHDN_VCC
TS = GND, I/OVCC = unconnected 0.1 1
FA
TS = VCC, VL = GND,
I/OVCC = unconnected 0.1 1
VL Shutdown Mode Supply
Current ISHDN_VL
TS = GND 0.1 1
FA
TS = VL, VCC = GND,
I/OVL_ = unconnected 0.1 1
I/OVCC_, I/OVL_, TS Leakage
Current ILEAK TA = +25NC, TS = GND 0.1 1 FA
TS Input Leakage Current ILEAK_TS TA = +25NC1FA
VL Shutdown Threshold VTH_VL 0.3 0.85 V
VCC Shutdown Threshold VTH_VCC 0.8 1.35 V
I/OVL_ Pullup Resistor RVL_PU 10 kI
I/OVCC_ Pullup Resistor RVCC_PU 10 kI
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
3Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +1.65V to +5.5V, VL = 0.9V to the lesser of VCC + 0.3V and 5V. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical
values are at VCC = +3.3V, VL = +1.8V, TA = +25NC, unless otherwise noted.) (Notes 2, 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I/OVL_ to I/OVCC_ DC
Resistance RIOVL_IOVCC Inferred from VOL measurements 5 10 I
I/OVL_ Input-Voltage High VIHL VL - 0.2 V
I/OVL_ Input-Voltage Low VILL 0.15 V
I/OVCC_ Input-Voltage High VIHC VCC - 0.4 V
I/OVCC_ Input-Voltage Low VILC 0.2 V
I/OVL_ Output-Voltage High VOHL I/OVL_ source current = 10FA0.7 x VLV
I/OVL_ Output-Voltage Low VOLL I/OVL_ sink current = 2mA,
VI/OVCC_ P 50mV 0.4 V
I/OVCC_ Output-Voltage High VOHC I/OVCC_ source current = 10FA0.7 x VCC V
I/OVCC_ Output Voltage Low VOLC I/OVCC_ sink current = 2mA,
VI/OVL_ P 150mV 0.4 V
TS Input-Voltage High Threshold VIH VL - 0.2 V
TS Input-Voltage Low Threshold VIL VL > 1.3V 0.2 V
Accelerator Pulse Duration Inferred from timing measurements 30 ns
VL Output Accelerator Source
Impedance
VL = 0.9V 70 I
VL = 3.3V 15
VCC Output Accelerator Source
Impedance
VCC = 1.65V 50 I
VCC = 5.0V 10
Thermal-Shutdown Threshold 20NC hysteresis +150 NC
ESD PROTECTION
I/OVCC_ Human Body Model, CVCC = 1FF,
CVL = 0.1FFQ6kV
All Other Pins Human Body Model Q2kV
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
4Maxim Integrated
TIMING CHARACTERISTICS
(VCC = +1.65V to +5.5V, VL = +0.9V to the lesser of VCC + 0.3V and 5V, TS = VL, RL = 1Mω, CVCC = 1µF, CVL = 0.1µF, CI/OVCC_ = 15pF,
CI/OVL_ = 15pF, TA = -40NC to +85NC, unless otherwise noted. Typical values are VCC = +3.3V, VL = +1.8V, and TA = +25NC.) (Note 4)
Note 2: All units are 100% production tested at TA = +25°C. Specifications over operating temperature range are guaranteed by
design.
Note 3: VL must be less than or equal to VCC during normal operation. However, VL can be greater than VCC during startup and
shutdown conditions.
Note 4: All timing is 10% to 90% for rise time and 90% to 10% for fall time.
Note 5: Not production tested; guaranteed by design.
Note 6: Requires the external pullup resistor.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I/OVCC_ Rise Time tRVCC
Push-pull driving (Figure 1) 40 ns
Open-drain driving (Figure 2, Note 5) 100
I/OVCC_ Fall Time tFVCC
Push-pull driving (Figure 1) 40 ns
Open-drain driving (Figure 2, Note 5) 50
I/OVL_ Rise Time tRVL
Push-pull driving (Figure 3) 30 ns
Open-drain driving (Figure 4, Note 5) 105
I/OVL_ Fall Time tFVL
Push-pull driving (Figure 3) 30 ns
Open-drain driving (Figure 4, Note 5) 30
Propagation Delay I/OVL-VCC Push-pull driving (Figure 1) 40 ns
I/OVL-VCC Open-drain driving (Figure 2, Note 5) 150
Propagation Delay I/OVCC-VL Push-pull driving (Figure 3) 30 ns
I/OVCC-VL Open-drain driving (Figure 4, Note 5) 105
Channel-to-Channel Skew tSKEW
Input rise time/fall time < 6ns, push-pull
driving 20
ns
Input rise time/fall time < 6ns, open-drain
driving 50
Maximum Data Rate Push-pull operation 20 Mbps
Open-drain operation (Notes 5, 6) 6
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
5Maxim Integrated
Figure 1. Push-Pull Driving I/OVL_
Figure 2. Open-Drain Driving I/OVL_
tRVCC
tPDLH tPDHL
tFVCC
90%90%
50%
10%
50%
50%
10%
50%
I/OVL_
TS
VLVCC
VLVCC
I/OVCC_
CI/OVCC_ RL
RS
50I
MAX14611
GND
I/OVL_
TS
VLVCC
VLVCC
I/OVCC_
GND CI/OVCC_ RL
1kI1kI
MAX14611
tRVCC tFVCC
tPDHL
tPDLH
50%
50%
90% 90%
50%
50%
10%
10%
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
6Maxim Integrated
Figure 3. Push-Pull Driving I/OVCC_
Figure 4. Open-Drain Driving I/OVCC_
I/OVL_
TS
VLVCC
VLVCC
I/OVCC_
RS
50I
CI/OVL_
RL
MAX14611
tRVL tFVL
tPDLH tPDHL
50%
50%
50%
10% 10%
50%
90% 90%
GND
tRVL
tPDLH tPDHL
90%90%
10% 10%
50%
50%
50%
50%
tFVL
I/OVL_
TS
VLVCC
VLVCC
I/OVCC_
MAX14611
CI/OVL_
RL
1kI
1kI
GND
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
7Maxim Integrated
Typical Operating Characteristics
(VCC = +3.3V, VL = 1.8V, RL = 1Mω, CL = 15pF, TA = +25°C, data rate = 500kbps in open-drain operation and 8Mbps in push-pull
operation, unless otherwise noted.)
VL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX14611 toc01
VCC (V)
SUPPLY CURRENT (µA)
4.954.402.20 2.75 3.30 3.85
25
50
75
100
125
150
175
200
0
1.65 5.50
DRIVING I/OVL_
VL = 1.8V
8Mbps,
PUSH-PULL
500kbps,
OPEN-DRAIN
VCC SUPPLY CURRENT
vs. TEMPERATURE
MAX14611 toc04
SUPPLY CURRENT (µA)
50
100
150
200
250
300
350
400
0
TEMPERATURE (°C)
603510-15-40 85
DRIVING I/OVCC_
8Mbps,
PUSH-PULL
500kbps,
OPEN-DRAIN
100
200
300
400
600
700
800
900
500
VCC SUPPLY CURRENT
vs. CAPACITIVE LOAD
MAX14611 toc06
SUPPLY CURRENT (µA)
1000
0
CAPACITIVE LOAD (pF)
4540353025 50
DRIVING I/OVL_
8Mbps,
PUSH-PULL
500kbps,
OPEN-DRAIN
20
40
60
80
120
140
160
180
100
VL SUPPLY CURRENT
vs. CAPACITIVE LOAD
MAX14611 toc05
SUPPLY CURRENT (µA)
200
0
CAPACITIVE LOAD (pF)
4540353025 50
DRIVING I/OVL_
8Mbps,
PUSH-PULL
500kbps,
OPEN-DRAIN
10
20
30
40
60
70
80
90
50
RISE/ FALL TIME
vs. CAPACITIVE LOAD
MAX14611 toc07
RISE/FALL TIME (ns)
100
0
CAPACITIVE LOAD (pF)
4540353025 50
DRIVING I/OVL_
500kbps, OPEN-DRAIN
tHL
tLH
200
400
600
800
1000
VCC SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX14611 toc02
VCC (V)
SUPPLY CURRENT (µA)
4.954.402.20 2.75 3.30 3.85
1200
0
1.65 5.50
DRIVING I/OVL_
VL = 1.8V
8Mbps,
PUSH-PULL 500kbps,
OPEN-DRAIN
VL SUPPLY CURRENT
vs. TEMPERATURE
MAX14611 toc03
SUPPLY CURRENT (µA)
25
50
75
100
125
150
175
200
0
TEMPERATURE (°C)
603510-15-40 85
DRIVING I/OVCC_ 8Mbps,
PUSH-PULL
500kbps,
OPEN-DRAIN
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
8Maxim Integrated
Typical Operating Characteristics (continued)
(VCC = +3.3V, VL = 1.8V, RL = 1Mω, CL = 15pF, TA = +25°C, data rate = 500kbps in open-drain operation and 8Mbps in push-pull
operation, unless otherwise noted.)
2
4
6
8
12
14
16
18
10
RISE/ FALL TIME
vs. CAPACITIVE LOAD
MAX14611 toc08
RISE/FALL TIME (ns)
20
0
CAPACITIVE LOAD (pF)
4540353025 50
DRIVING I/OVL_
8Mbps, PUSH-PULL
tLH
tHI
25
50
75
100
125
RISE/FALL TIME
vs. CAPACITIVE LOAD
MAX14611 toc11
RISE/FALL TIME (ns)
150
0
CAPACITIVE LOAD (pF)
4540353025 50
tLH
tHL
DRIVING I/OVCC_
500kbps, OPEN-DRAIN
1
2
3
4
5
PROPAGATION DELAY
vs. CAPACITIVE LOAD
MAX14611 toc13
PROPAGATION DELAY (ns)
6
0
CAPACITIVE LOAD (pF)
4540353025 50
tPHL
tPLH
DRIVING I/OVCC_
500kbps, OPEN-DRAIN
1
2
3
4
6
7
8
9
5
RISE/ FALL TIME
vs. CAPACITIVE LOAD
MAX14611 toc12
RISE/FALL TIME (ns)
10
0
CAPACITIVE LOAD (pF)
4540353025 50
DRIVING I/OVCC_
8Mbps, PUSH-PULL
tLH
tHL
PROPAGATION DELAY
vs. CAPACITIVE LOAD
MAX14611 toc14
PROPAGATION DELAY (ns)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
CAPACITIVE LOAD (pF)
4540353025 50
tPHL
tPLH
DRIVING I/OVCC_
8Mbps, PUSH-PULL
PROPAGATION DELAY
vs. CAPACITIVE LOAD
MAX14611 toc09
PROPAGATION DELAY (ns)
1
2
3
4
5
6
7
8
0
CAPACITIVE LOAD (pF)
4540353025 50
tPHL
tPLH
DRIVING I/OVL_
500kbps, OPEN-DRAIN
1
2
3
4
5
PROPAGATION DELAY
vs. CAPACITIVE LOAD
MAX14611 toc10
PROPAGATION DELAY (ns)
6
0
CAPACITIVE LOAD (pF)
4540353025 50
tPHL
tPLH
DRIVING I/OVL_
8Mbps, PUSH-PULL
WAL‘HM LUAD (DH WAL‘HM LUAD (DH M“
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
9Maxim Integrated
Typical Operating Characteristics (continued)
(VCC = +3.3V, VL = 1.8V, RL = 1Mω, CL = 15pF, TA = +25°C, data rate = 500kbps in open-drain operation and 8Mbps in push-pull
operation, unless otherwise noted.)
5
10
15
20
30
35
40
45
25
RISE/FALL TIME (ns)
50
0
RISE/FALL TIME
vs. CAPACITIVE LOAD
MAX14611 toc17
CAPACITIVE LOAD (pF)
4540353025 50
DRIVING I/OVL_
4Mbps, OPEN-DRAIN
1kI EXTERNAL PULLUP
tLH
tHL
5
10
15
20
30
35
40
45
25
RISE/ FALL TIME
vs. CAPACITIVE LOAD
MAX14611 toc15
RISE/FALL TIME (ns)
50
0
CAPACITIVE LOAD (pF)
4540353025 50
DRIVING I/OVCC_
4Mbps, OPEN-DRAIN
1kI EXTERNAL PULLUP
tLH
tHL
LOW-TO-HIGH TRANSITION,
OPEN-DRAIN ZOOM
MAX14611 toc19
4ns/div
-6
-2
0
2
4
-4
SUPPLY CURRENT (µA)
6
-8
PROPAGATION DELAY
vs. CAPACITIVE LOAD
MAX14611 toc18
CAPACITIVE LOAD (pF)
4540353025 50
DRIVING I/OVCC_
4Mbps, OPEN-DRAIN
1kI EXTERNAL PULLUP
50% I/O VCC_ TO 50% I/OVL_ (SEE TOC19)
tPHL
tPLH
4
8
12
16
PROPAGATION DELAY
vs. CAPACITIVE LOAD
MAX14611 toc16
PROPAGATION DELAY (ns)
20
0
CAPACITIVE LOAD (pF)
4540353025 50
DRIVING I/OVL_
4Mbps, OPEN-DRAIN
1kI EXTERNAL PULLUP
tPLH
tPHL
ENTERING AND EXITING THREE-STATE MODE
(DRIVING I/OVCC_, CLOAD = 50pF)
MAX14611 toc20
10ms/div
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
10Maxim Integrated
Pin Description
Pin Configurations
PIN NAME FUNCTION
TDFN-EP TSSOP
1 2 I/OVL1 Input/Output 1. Reference to VL.
2 3 I/OVL2 Input/Output 2. Reference to VL.
3 8 TS
Three-State Select Input. Drive TS low to place the device in three-state output mode. I/OVCC_
and I/OVL_ are high impedance in three-state output mode.
Note: Logic referenced to VL (for logic thresholds, see the Electrical Characteristics table).
4, 11 6,9 N.C. No Connection. Not internally connected.
5 4 I/OVL3 Input/Output 3. Reference to VL.
6 5 I/OVL4 Input/Output 4. Reference to VL.
7 7 GND Ground
8 10 I/OVCC4 Input/Output 4. Reference to VCC.
9 11 I/OVCC3 Input/Output 3. Reference to VCC.
10 1 VLLogic Supply Voltage Input, 0.9V P VL P min (5.0V, (VCC + 0.3V)). Connect a 0.1FF ceramic
capacitor as close as possible to the pin.
12 12 I/OVCC2 Input/Output 2. Reference to VCC.
13 13 I/OVCC1 Input/Output 1. Reference to VCC.
14 14 VCC Power Supply Input. The supply range is 1.65V P VCC P 5.5V. Bypass VCC with a 1FF ceramic
capacitor as close as possible to the pin to achieve higher ESD protection (Q6kV HBM).
EP Exposed Pad (TDFN Only). EP is internally connected to GND. Connect to a large ground
plane to maximize thermal performance. Not intended as an electrical connection point.
*EP
*CONNECT EXPOSED PAD TO GND.
TDFN
TOP VIEW
2
4
5
13
11
10
I/OVCC1
N.C.
VL
I/OVL2
N.C.
I/OVL3
1+14 VCC
I/OVL1
312 I/OVCC2TS
69I/OVCC3I/OVL4
78I/OVCC4GND
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCC
I/OVCC1
I/OVCC2
I/OVCC3I/OVL3
I/OVL2
I/OVL1
VL
MAX14611
MAX14611
I/OVCC4
N.C.
TSGND
N.C.
I/OVL4
TSSOP
+
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
11Maxim Integrated
Detailed Description
The MAX14611 ESD-protected level translator provides
the level shifting necessary to allow data transfer in a
multivoltage system. Externally applied voltages, VCC
and VL, set the logic levels on either side of the device.
A low-voltage logic signal present on the VL side of the
device appears as a high-voltage logic signal on the VCC
side of the device, and vice-versa.
The MAX14611 bidirectional level translator uti-
lizes a transmission-gate based design (see the
Functional Diagram) to allow data translation in either
direction (VL VCC) on any single data line. The device
accepts VL from +0.9V to +5.0V and VCC from +1.65V
to +5.5V, making it ideal for data transfer between low-
voltage ASICs/PLDs and higher voltage systems.
The device features a three-state output mode, thermal
short-circuit protection, and Q6kV ESD protection on the
VCC side for greater protection in applications that route
signals externally.
Level Translation
For proper operation, ensure that +1.65V P VCC P +5.5V,
0.9V P VL P 5.0V, and VL P (VCC + 0.3V). It is permissible
for VL to exceed (VCC + 0.3V) during power-up sequenc-
ing. During power-supply sequencing, when VCC is
disconnected and VL is powered up, a current can be
sourced without a latchup or any damage to the device.
The maximum data rate of the MAX14611 depends
heavily on load capacitance (see the Typical Operating
Characteristics), output impedance of the driver, and
the operational voltage (see the Timing Characteristics
table).
Speed-Up Circuitry
The device features a one-shot generator that decreases
the rise time of the output. When triggered following a ris-
ing edge, MOSFETs PU1 and PU2 turn on for a short time
to pull up I/OVL_ and I/OVCC_ to their respective sup-
plies (see the Functional Diagram). This greatly reduces
the rise time and propagation delay for the low-to-high
transition.
Functional Diagram
I/OVL_
PU1 PU2
VLTS VCC
I/OVCC_
MAX14611
ONE-SHOT
BLOCK
N
EN CONTROL
BLOCK
GATE
DRIVE
ONE-SHOT
BLOCK
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
12Maxim Integrated
Rise-Time Accelerators (Figure 5)
The device has internal rise-time accelerators, allowing
operation up to 20Mbps. The rise-time accelerators are
present on both sides of the device and act to speed
up the rise time of the input and output of the device,
regardless of the direction of the data. The triggering
mechanism for these accelerators is both level and edge
sensitive. To prevent false triggering of the rise-time
accelerators, and to take full advantage of them, signal
rise/fall times of less than 2ns/V are recommended for
both sides of the device. In open-drain driving, the rec-
ommendation only applies for fall time. Under less noisy
conditions, longer signal fall times can be acceptable.
Three-State Output Mode (TS)
Drive TS low to place the device in three-state output
mode. Connect TS to VL (logic-high) for normal opera-
tion. Activating the three-state output mode disconnects
the internal 10kI pullup resistors on the I/OVCC_ and
I/OVL_ lines. This forces the I/O lines to a high-impedance
state and decreases the supply current to less than 1FA.
The high-impedance I/O lines in three-state output mode
allow for use in a multidrop network. When in three-state
output mode, keep the I/OVL_ voltage below (VL + 0.3V),
and keep the I/OVCC_ voltage below (VCC + 0.3V).
Thermal Short-Circuit Protection
Thermal-overload detection protects the device from
short-circuit fault conditions. In the event of a short-circuit
fault and when the junction temperature (TJ) reaches
+150NC (typ), a thermal sensor signals the three-state
output mode logic to force the device into three-state out-
put mode. When TJ has cooled to +130NC (typ), normal
operation resumes.
High ESD Protection
As with all Maxim devices, ESD-protection structures are
incorporated on all pins to protect against electrostatic
discharges encountered during handling and assembly.
The I/OVCC_ lines have extra protection against static
electricity. Maxim’s engineers have developed state-of-
the-art structures to protect these pins against ESD of
±6kV without damage.
The ESD structures withstand high ESD in all states:
normal operation, three-state output mode, and powered
down. After an ESD event, the device keeps working
without latchup, whereas competing products can latch
and must be powered down to remove latchup. ESD pro-
tection can be tested in various ways. The I/OVCC_ lines
of this product family are characterized for protection.to
±6kV using the Human Body Model.
ESD Test Conditions
Contact Maxim for a reliability report that documents test
setup, test methodology, and test results.
Applications Information
Power-Supply Decoupling
Bypass VL to ground with a 0.1FF capacitor to reduce
ripple and ensure correct data transmission. See the
Typical Operating Circuit. To ensure full Q6kV ESD
protection, bypass VCC to ground with a 1FF capacitor.
Place all capacitors as close as possible to the power-
supply pins (VCC
and V L).
Push-Pull vs. Open-Drain Driving
The device can be driven in a push-pull configuration.
The device includes internal 10kI resistors that pull
up I/OVL_ and I/OVCC_ to their respective power sup-
plies, allowing operation of the I/O lines with open-drain
devices. See the Timing Characteristics table for maxi-
mum data rates when using open-drain drivers (Figure 1,
Figure 2, Figure 3, Figure 4).
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
13Maxim Integrated
Applications Circuit
Figure 5. Open-Drain Operation
TS
I/OVL1
I/OVL2
I/OVL3
DATA DATA
I/OVL4
I/OVCC1
+1.8V +3.3V
VLVCC
+3.3V
SYSTEM
I/OVCC2
I/OVCC3
I/OVCC4
+1.8V SYSTEM
CONTROLLER
0.1µF 1µF
MAX14611
TS
I/OVL1
I/OVL2
I/OVL3
I/OVL4
EN
SDA SDA
I/OVCC1
SCL
SDA
SCL
VL
VL = +1.8V VCC = +3.3V
VLVCC
GNDGND GND
+3.3V
SYSTEM
VCC
VL
VL
VL
SCL
SDA
SCL
I/OVCC2
I/OVCC3
I/OVCC4
VCC
VCC
+1.8V SYSTEM
CONTROLLER
0.1µF 1µF
VCC
MAX14611
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
14Maxim Integrated
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
**Future product—contact factory for availability.
Ordering Information
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PART TEMP RANGE PIN-PACKAGE
MAX14611ETD+ -40NC to +85NC14 TDFN-EP*
MAX14611EUD+** -40NC to +85NC14 TSSOP
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
14 TDFN-EP T1433+2 21-0137 90-0063
14 TSSOP U14+1 21-0066 90-0113
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 15
© 2012 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 4/12 Initial release

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