C8051F300-05 Datasheet by Silicon Labs

SILIEEIN LABS 8-b11 500 ksps ADC TEMP SENSOR
Mixed Signal ISP Flash MCU Family
C8051F300/1/2/3/4/5
Rev. 2.9 7/08 Copyright © 2008 by Silicon Laboratories C8051F300/1/2/3/4/5
Analog Peripherals
-8-Bit ADC ('F300/2 only)
Up to 500 ksps
Up to 8 external inputs
Programmable amplifier gains of 4, 2, 1, & 0.5
VREF from external pin or VDD
Built-in temperature sensor
External conversion start input
-Comparator
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current (<0.5 µA)
On-chip Debug
-On-chip debug circuitry facilitates full speed,
non-intrusive in-system debug (no emulator
required)
-Provides breakpoints, single stepping,
inspect/modify memory and registers
-Superior performance to emulation systems using
ICE-chips, target pods, and sockets
-Complete development kit
Supply Voltage 2.7 to 3.6 V
-Typical operating current: 6.6 mA @ 25 MHz;
14 µA @ 32 kHz
-Typical stop mode current: 0.1 µA
-Temperature range: –40 to +85 °C
High Speed 8051 µc Core
-Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
-Up to 25 MIPS throughput with 25 MHz clock
-Expanded interrupt handler
Memory
-256 bytes internal data RAM
-Up to 8 kB (‘F300/1/2/3), 4 kB (‘F304), or 2 kB
(‘F305) Flash; 512 bytes are reserved in the 8 kB
devices
Digital Peripherals
-8 Port I/O; All 5 V tolerant with high sink current
-Hardware enhanced UART and SMBus™ serial
ports
-Three general-purpose 16-bit counter/timers
-16-bit programmable counter array (PCA) with three
capture/compare modules
-Real time clock mode using PCA or timer and
external clock source
Clock Sources
-Internal oscillator: 24.5 MHz with ±2% accuracy
supports UART operation
-External oscillator: Crystal, RC, C, or clock (1 or 2
pin modes)
-Can switch between clock sources on-the-fly; Useful
in power saving modes
11-Pin QFN or 14-Pin SOIC Package
-QFN Size = 3x3 mm
ANALOG
PERIPHERALS
PGA
8/4/2 kBytes
ISP Flash 256 B SRAM
POR
DEBUG
CIRCUITRY
12
INTERRUPTS
8051 CPU
(25MIPS)
DIGITAL I/O
PROGRAMMABLE PRECISION INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
A
M
U
X
I/O Port
CROSSBAR
UART
SMBus
PCA
Timer 0
Timer 1
Timer 2
VOLTAGE COMPARATOR
+
-
WDT
8-bit
500 ksps
ADC
TEMP
SENSOR
C8051F300/2 only
, . SILIEUN LABS
C8051F300/1/2/3/4/5
2 Rev. 2.9
NOTES:
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 3
Table of Contents
1. System Overview.................................................................................................... 13
1.1. CIP-51™ Microcontroller Core.......................................................................... 16
1.1.1. Fully 8051 Compatible.............................................................................. 16
1.1.2. Improved Throughput............................................................................... 16
1.1.3. Additional Features .................................................................................. 17
1.2. On-Chip Memory............................................................................................... 18
1.3. On-Chip Debug Circuitry................................................................................... 19
1.4. Programmable Digital I/O and Crossbar........................................................... 19
1.5. Serial Ports ....................................................................................................... 20
1.6. Programmable Counter Array........................................................................... 21
1.7. 8-Bit Analog to Digital Converter (C8051F300/2 Only)..................................... 22
1.8. Comparator....................................................................................................... 23
2. Absolute Maximum Ratings .................................................................................. 24
3. Global Electrical Characteristics .......................................................................... 25
4. Pinout and Package Definitions............................................................................ 27
5. ADC0 (8-Bit ADC, C8051F300/2)............................................................................ 35
5.1. Analog Multiplexer and PGA............................................................................. 36
5.2. Temperature Sensor......................................................................................... 36
5.3. Modes of Operation .......................................................................................... 39
5.3.1. Starting a Conversion............................................................................... 39
5.3.2. Tracking Modes........................................................................................ 40
5.3.3. Settling Time Requirements..................................................................... 41
5.4. Programmable Window Detector...................................................................... 45
5.4.1. Window Detector In Single-Ended Mode ................................................. 45
5.4.2. Window Detector In Differential Mode...................................................... 46
6. Voltage Reference (C8051F300/2)......................................................................... 49
7. Comparator0 ........................................................................................................... 51
8. CIP-51 Microcontroller ........................................................................................... 57
8.1. Instruction Set................................................................................................... 58
8.1.1. Instruction and CPU Timing ..................................................................... 58
8.1.2. MOVX Instruction and Program Memory ................................................. 59
8.2. Memory Organization........................................................................................ 63
8.2.1. Program Memory...................................................................................... 63
8.2.2. Data Memory............................................................................................ 64
8.2.3. General Purpose Registers...................................................................... 64
8.2.4. Bit Addressable Locations........................................................................ 65
8.2.5. Stack ....................................................................................................... 65
8.2.6. Special Function Registers....................................................................... 65
8.2.7. Register Descriptions ............................................................................... 68
8.3. Interrupt Handler............................................................................................... 72
8.3.1. MCU Interrupt Sources and Vectors ........................................................ 72
8.3.2. External Interrupts.................................................................................... 73
8.3.3. Interrupt Priorities..................................................................................... 73
, . SILIEUN LABS
C8051F300/1/2/3/4/5
4 Rev. 2.9
8.3.4. Interrupt Latency ...................................................................................... 73
8.3.5. Interrupt Register Descriptions................................................................. 75
8.4. Power Management Modes.............................................................................. 80
8.4.1. Idle Mode.................................................................................................. 80
8.4.2. Stop Mode................................................................................................ 81
9. Reset Sources......................................................................................................... 83
9.1. Power-On Reset ............................................................................................... 84
9.2. Power-Fail Reset/VDD Monitor......................................................................... 84
9.3. External Reset .................................................................................................. 85
9.4. Missing Clock Detector Reset........................................................................... 85
9.5. Comparator0 Reset........................................................................................... 85
9.6. PCA Watchdog Timer Reset............................................................................. 85
9.7. Flash Error Reset.............................................................................................. 86
9.8. Software Reset ................................................................................................. 86
10.Flash Memory ......................................................................................................... 89
10.1.Programming The Flash Memory..................................................................... 89
10.1.1.Flash Lock and Key Functions................................................................. 89
10.1.2.Flash Erase Procedure ............................................................................ 89
10.1.3.Flash Write Procedure ............................................................................. 90
10.2.Non-Volatile Data Storage................................................................................ 90
10.3.Security Options ............................................................................................... 90
10.4.Flash Write and Erase Guidelines.................................................................... 94
10.4.1.VDD Maintenance and the VDD monitor ................................................... 94
10.4.2.PSWE Maintenance................................................................................. 94
10.4.3.System Clock ........................................................................................... 95
11.Oscillators............................................................................................................... 97
11.1.Programmable Internal Oscillator..................................................................... 97
11.2.External Oscillator Drive Circuit........................................................................ 99
11.3.System Clock Selection.................................................................................... 99
11.4.External Crystal Example ............................................................................... 101
11.5.External RC Example ..................................................................................... 102
11.6.External Capacitor Example........................................................................... 102
12.Port Input/Output.................................................................................................. 103
12.1.Priority Crossbar Decoder .............................................................................. 104
12.2.Port I/O Initialization ....................................................................................... 106
12.3.General Purpose Port I/O............................................................................... 108
13.SMBus ................................................................................................................... 111
13.1.Supporting Documents................................................................................... 112
13.2.SMBus Configuration...................................................................................... 112
13.3.SMBus Operation ........................................................................................... 112
13.3.1.Arbitration............................................................................................... 113
13.3.2.Clock Low Extension.............................................................................. 114
13.3.3.SCL Low Timeout................................................................................... 114
13.3.4.SCL High (SMBus Free) Timeout .......................................................... 114
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 5
13.4.Using the SMBus............................................................................................ 115
13.4.1.SMBus Configuration Register............................................................... 116
13.4.2.SMB0CN Control Register ..................................................................... 119
13.4.3.Data Register ......................................................................................... 122
13.5.SMBus Transfer Modes.................................................................................. 123
13.5.1.Master Transmitter Mode....................................................................... 123
13.5.2.Master Receiver Mode........................................................................... 124
13.5.3.Slave Receiver Mode............................................................................. 125
13.5.4.Slave Transmitter Mode......................................................................... 126
13.6.SMBus Status Decoding................................................................................. 127
14.UART0.................................................................................................................... 131
14.1.Enhanced Baud Rate Generation................................................................... 132
14.2.Operational Modes ......................................................................................... 133
14.2.1.8-Bit UART............................................................................................. 133
14.2.2.9-Bit UART............................................................................................. 134
14.3.Multiprocessor Communications .................................................................... 135
15.Timers.................................................................................................................... 143
15.1.Timer 0 and Timer 1 ....................................................................................... 143
15.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 143
15.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 145
15.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 145
15.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 146
15.2.Timer 2 .......................................................................................................... 151
15.2.1.16-bit Timer with Auto-Reload................................................................ 151
15.2.2.8-bit Timers with Auto-Reload................................................................ 152
16.Programmable Counter Array ............................................................................. 155
16.1.PCA Counter/Timer ........................................................................................ 156
16.2.Capture/Compare Modules ............................................................................ 157
16.2.1.Edge-triggered Capture Mode................................................................ 158
16.2.2.Software Timer (Compare) Mode........................................................... 159
16.2.3.High Speed Output Mode....................................................................... 160
16.2.4.Frequency Output Mode ........................................................................ 161
16.2.5.8-Bit Pulse Width Modulator Mode......................................................... 162
16.2.6.16-Bit Pulse Width Modulator Mode....................................................... 163
16.3.Watchdog Timer Mode ................................................................................... 164
16.3.1.Watchdog Timer Operation.................................................................... 164
16.3.2.Watchdog Timer Usage ......................................................................... 165
16.4.Register Descriptions for PCA........................................................................ 167
17.C2 Interface........................................................................................................... 173
17.1.C2 Interface Registers.................................................................................... 173
17.2.C2 Pin Sharing ............................................................................................... 175
Document Change List............................................................................................. 176
Contact Information.................................................................................................. 178
, . SILIEUN LABS
C8051F300/1/2/3/4/5
6 Rev. 2.9
NOTES:
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 7
List of Figures
1. System Overview
Figure 1.1. C8051F300/2 Block Diagram................................................................. 15
Figure 1.2. C8051F301/3/4/5 Block Diagram........................................................... 15
Figure 1.3. Comparison of Peak MCU Execution Speeds ....................................... 16
Figure 1.4. On-Chip Clock and Reset ...................................................................... 17
Figure 1.5. On-chip Memory Map (C8051F300/1/2/3 Shown) ................................. 18
Figure 1.6. Development/In-System Debug Diagram............................................... 19
Figure 1.7. Digital Crossbar Diagram....................................................................... 20
Figure 1.8. PCA Block Diagram ............................................................................... 21
Figure 1.9. PCA Block Diagram ............................................................................... 21
Figure 1.10. 8-Bit ADC Block Diagram..................................................................... 22
Figure 1.11. Comparator Block Diagram.................................................................. 23
2. Absolute Maximum Ratings
3. Global Electrical Characteristics
4. Pinout and Package Definitions
Figure 4.1. QFN-11 Pinout Diagram (Top View) ...................................................... 28
Figure 4.2. QFN-11 Package Drawing ..................................................................... 29
Figure 4.3. Typical QFN-11 Solder Paste Mask....................................................... 30
Figure 4.4. Typical QFN-11 Landing Diagram.......................................................... 31
Figure 4.5. SOIC-14 Pinout Diagram (Top View)..................................................... 32
Figure 4.6. SOIC-14 Package Drawing.................................................................... 33
Figure 4.7. SOIC-14 PCB Land Pattern ................................................................... 34
5. ADC0 (8-Bit ADC, C8051F300/2)
Figure 5.1. ADC0 Functional Block Diagram............................................................ 35
Figure 5.2. Typical Temperature Sensor Transfer Function..................................... 37
Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V).... 38
Figure 5.4. 8-Bit ADC Track and Conversion Example Timing ................................ 40
Figure 5.5. ADC0 Equivalent Input Circuits.............................................................. 41
Figure 5.6. ADC Window Compare Examples, Single-Ended Mode........................ 45
Figure 5.7. ADC Window Compare Examples, Differential Mode............................ 46
6. Voltage Reference (C8051F300/2)
Figure 6.1. Voltage Reference Functional Block Diagram ....................................... 49
7. Comparator0
Figure 7.1. Comparator0 Functional Block Diagram ................................................ 51
Figure 7.2. Comparator Hysteresis Plot ................................................................... 52
8. CIP-51 Microcontroller
Figure 8.1. CIP-51 Block Diagram............................................................................ 57
Figure 8.2. Program Memory Maps.......................................................................... 63
Figure 8.3. Data Memory Map.................................................................................. 64
9. Reset Sources
Figure 9.1. Reset Sources........................................................................................ 83
Figure 9.2. Power-On and VDD Monitor Reset Timing ............................................ 84
, . SILIEUN LABS
C8051F300/1/2/3/4/5
8 Rev. 2.9
10.Flash Memory
Figure 10.1. Flash Program Memory Map................................................................ 91
11.Oscillators
Figure 11.1. Oscillator Diagram................................................................................ 97
Figure 11.2. 32.768 kHz External Crystal Example................................................ 101
12.Port Input/Output
Figure 12.1. Port I/O Functional Block Diagram..................................................... 103
Figure 12.2. Port I/O Cell Block Diagram ............................................................... 103
Figure 12.3. Crossbar Priority Decoder with XBR0 = 0x00 .................................... 104
Figure 12.4. Crossbar Priority Decoder with XBR0 = 0x44 .................................... 105
13.SMBus
Figure 13.1. SMBus Block Diagram ....................................................................... 111
Figure 13.2. Typical SMBus Configuration............................................................. 112
Figure 13.3. SMBus Transaction............................................................................ 113
Figure 13.4. Typical SMBus SCL Generation......................................................... 117
Figure 13.5. Typical Master Transmitter Sequence................................................ 123
Figure 13.6. Typical Master Receiver Sequence.................................................... 124
Figure 13.7. Typical Slave Receiver Sequence...................................................... 125
Figure 13.8. Typical Slave Transmitter Sequence.................................................. 126
14.UART0
Figure 14.1. UART0 Block Diagram ....................................................................... 131
Figure 14.2. UART0 Baud Rate Logic.................................................................... 132
Figure 14.3. UART Interconnect Diagram .............................................................. 133
Figure 14.4. 8-Bit UART Timing Diagram............................................................... 133
Figure 14.5. 9-Bit UART Timing Diagram............................................................... 134
Figure 14.6. UART Multi-Processor Mode Interconnect Diagram .......................... 135
15.Timers
Figure 15.1. T0 Mode 0 Block Diagram.................................................................. 144
Figure 15.2. T0 Mode 2 Block Diagram.................................................................. 145
Figure 15.3. T0 Mode 3 Block Diagram.................................................................. 146
Figure 15.4. Timer 2 16-Bit Mode Block Diagram .................................................. 151
Figure 15.5. Timer 2 8-Bit Mode Block Diagram .................................................... 152
16.Programmable Counter Array
Figure 16.1. PCA Block Diagram............................................................................ 155
Figure 16.2. PCA Counter/Timer Block Diagram.................................................... 156
Figure 16.3. PCA Interrupt Block Diagram ............................................................. 157
Figure 16.4. PCA Capture Mode Diagram.............................................................. 158
Figure 16.5. PCA Software Timer Mode Diagram.................................................. 159
Figure 16.6. PCA High Speed Output Mode Diagram............................................ 160
Figure 16.7. PCA Frequency Output Mode ............................................................ 161
Figure 16.8. PCA 8-Bit PWM Mode Diagram ......................................................... 162
Figure 16.9. PCA 16-Bit PWM Mode...................................................................... 163
Figure 16.10. PCA Module 2 with Watchdog Timer Enabled ................................. 164
17.C2 Interface
Figure 17.1. Typical C2 Pin Sharing....................................................................... 175
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 9
List of Tables
1. System Overview
Table 1.1. Product Selection Guide ......................................................................... 14
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings .................................................................... 24
3. Global Electrical Characteristics
Table 3.1. Global Electrical Characteristics ............................................................. 25
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F300/1/2/3/4/5 ........................................... 27
Table 4.2. QFN-11 Package Dimensions ................................................................ 29
Table 4.3. QFN-11 Landing Diagram Dimensions ................................................... 31
Table 4.4. SOIC-14 Package Dimensions ............................................................... 33
Table 4.5. SOIC-14 PCB Land Pattern Dimensions ................................................ 34
5. ADC0 (8-Bit ADC, C8051F300/2)
Table 5.1. ADC0 Electrical Characteristics .............................................................. 47
6. Voltage Reference (C8051F300/2)
Table 6.1. External Voltage Reference Circuit Electrical Characteristics ................ 50
7. Comparator0
Table 7.1. Comparator0 Electrical Characteristics .................................................. 55
8. CIP-51 Microcontroller
Table 8.1. CIP-51 Instruction Set Summary ............................................................ 59
Table 8.2. Special Function Register (SFR) Memory Map ...................................... 66
Table 8.3. Special Function Registers ..................................................................... 66
Table 8.4. Interrupt Summary .................................................................................. 74
9. Reset Sources
Table 9.1. User Code Space Address Limits ........................................................... 86
Table 9.2. Reset Electrical Characteristics .............................................................. 86
10.Flash Memory
Table 10.1. Flash Electrical Characteristics ............................................................ 90
Table 10.2. Security Byte Decoding ........................................................................ 91
11.Oscillators
Table 11.1. Internal Oscillator Electrical Characteristics ......................................... 99
12.Port Input/Output
Table 12.1. Port I/O DC Electrical Characteristics ................................................. 110
13.SMBus
Table 13.1. SMBus Clock Source Selection .......................................................... 116
Table 13.2. Minimum SDA Setup and Hold Times ................................................ 117
Table 13.3. Sources for Hardware Changes to SMB0CN ..................................... 121
Table 13.4. SMBus Status Decoding ..................................................................... 127
14.UART0
Table 14.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator .............................................. 138
Table 14.2. Timer Settings for Standard Baud Rates
Using an External 25 MHz Oscillator .................................................. 138
, . SILIEUN LABS
C8051F300/1/2/3/4/5
10 Rev. 2.9
Table 14.3. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator ......................................... 139
Table 14.4. Timer Settings for Standard Baud Rates
Using an External 18.432 MHz Oscillator ........................................... 140
Table 14.5. Timer Settings for Standard Baud Rates
Using an External 11.0592 MHz Oscillator ......................................... 141
Table 14.6. Timer Settings for Standard Baud Rates
Using an External 3.6864 MHZ Oscillator .......................................... 142
15.Timers
16.Programmable Counter Array
Table 16.1. PCA Timebase Input Options ............................................................. 156
Table 16.2. PCA0CPM Register Settings for PCA Capture/Compare Modules .... 157
Table 16.3. Watchdog Timer Timeout Intervals ..................................................... 166
17.C2 Interface
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 11
List of Registers
SFR Definition 5.1. AMX0SL: AMUX0 Channel Select (C8051F300/2) . . . . . . . . . . . . 42
SFR Definition 5.2. ADC0CF: ADC0 Configuration (C8051F300/2) . . . . . . . . . . . . . . . 43
SFR Definition 5.3. ADC0: ADC0 Data Word (C8051F300/2) . . . . . . . . . . . . . . . . . . . 43
SFR Definition 5.4. ADC0CN: ADC0 Control (C8051F300/2) . . . . . . . . . . . . . . . . . . . . 44
SFR Definition 5.5. ADC0GT: ADC0 Greater-Than Data Byte (C8051F300/2) . . . . . . 46
SFR Definition 5.6. ADC0LT: ADC0 Less-Than Data Byte (C8051F300/2) . . . . . . . . . 46
SFR Definition 6.1. REF0CN: Reference Control Register . . . . . . . . . . . . . . . . . . . . . . 50
SFR Definition 7.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . . 54
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . . 54
SFR Definition 8.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
SFR Definition 8.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SFR Definition 8.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SFR Definition 8.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
SFR Definition 8.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SFR Definition 8.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SFR Definition 8.7. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SFR Definition 8.8. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SFR Definition 8.9. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . . . 77
SFR Definition 8.10. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . . 78
SFR Definition 8.11. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . 79
SFR Definition 8.12. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SFR Definition 9.1. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
SFR Definition 10.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . . 92
SFR Definition 10.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SFR Definition 10.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SFR Definition 11.1. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . . 98
SFR Definition 11.2. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . . 98
SFR Definition 11.3. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 100
SFR Definition 12.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 107
SFR Definition 12.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 107
SFR Definition 12.3. XBR2: Port I/O Crossbar Register 2 . . . . . . . . . . . . . . . . . . . . . 108
SFR Definition 12.4. P0: Port0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SFR Definition 12.5. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SFR Definition 12.6. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 110
SFR Definition 13.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 118
SFR Definition 13.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
SFR Definition 13.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SFR Definition 14.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 136
SFR Definition 14.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 137
SFR Definition 15.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SFR Definition 15.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
SFR Definition 15.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
, . SILIEUN LABS
C8051F300/1/2/3/4/5
12 Rev. 2.9
SFR Definition 15.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
SFR Definition 15.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
SFR Definition 15.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
SFR Definition 15.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
SFR Definition 15.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SFR Definition 15.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 154
SFR Definition 15.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 154
SFR Definition 15.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
SFR Definition 15.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
SFR Definition 16.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
SFR Definition 16.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
SFR Definition 16.3. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 169
SFR Definition 16.4. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 170
SFR Definition 16.5. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . 170
SFR Definition 16.6. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 171
SFR Definition 16.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 171
C2 Register Definition 17.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
C2 Register Definition 17.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 173
C2 Register Definition 17.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 174
C2 Register Definition 17.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 174
C2 Register Definition 17.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 174
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 13
1. System Overview
C8051F300/1/2/3/4/5 devices are fully integrated mixed-signal system-on-a-chip MCUs. Highlighted fea-
tures are listed below. Refer to Table 1.1 on page 14 for specific product feature selection.
High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
True 8-bit 500 ksps 11-channel ADC with programmable gain pre-amplifier and analog multiplexer
(C8051F300/2 only)
Precision programmable 25 MHz internal oscillator
Up to 8 kB of on-chip Flash memory
256 bytes of on-chip RAM
•SMBus/I
2C and Enhanced UART serial interfaces implemented in hardware
Three general-purpose 16-bit timers
Programmable counter/timer array (PCA) with three capture/compare modules and watchdog timer
function
On-chip power-on reset, VDD monitor, and temperature sensor
On-chip voltage comparator
Byte-wide I/O port (5 V tolerant)
With on-chip Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the
C8051F300/1/2/3/4/5 devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can
be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of
the 8051 firmware. User software has complete control of all peripherals, and may individually shut down
any or all peripherals for power savings.
The on-chip Silicon Laboratories 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging with-
out occupying package pins.
Each device is specified for 2.7 to 3.6 V operation over the industrial temperature range (–45 to +85 °C).
The Port I/O and RST pins are tolerant of input signals up to 5 V. The C8051F300/1/2/3/4/5 are available in
3 x 3 mm 11-pin QFN or 14-pin SOIC packaging.
, ‘ SILIEIJN LABS
C8051F300/1/2/3/4/5
14 Rev. 2.9
Table 1.1. Product Selection Guide
Ordering Part Number
MIPS (Peak)
Flash Memory
RAM
Calibrated Internal Oscillator
SMBus/I2C
UART
Timers (16-bit)
Programmable Counter Array
Digital Port I/Os
8-bit 500ksps ADC
Temperature Sensor
Analog Comparators
Lead-free (RoHS compliant)
Package
C8051F300-GM 25 8 k 256  38  1QFN-11
C8051F300-GS 25 8 k 256  38  1SOIC-14
C8051F301-GM 25 8 k 256  38 — — 1 QFN-11
C8051F301-GS 25 8 k 256  38 — — 1 SOIC-14
C8051F302-GM 25 8 k 256   38  1QFN-11
C8051F302-GS 25 8 k 256   38  1SOIC-14
C8051F303-GM 25 8 k 256   38 — — 1 QFN-11
C8051F303-GS 25 8 k 256   38 — — 1 SOIC-14
C8051F304-GM 25 4 k 256   38 — — 1 QFN-11
C8051F304-GS 25 4 k 256   38 — — 1 SOIC-14
C8051F305-GM 25 2 k 256   38 — — 1 QFN-11
C8051F305-GS 25 2 k 256   38 — — 1 SOIC-14
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 15
Figure 1.1. C8051F300/2 Block Diagram
Figure 1.2. C8051F301/3/4/5 Block Diagram
Port 0
Latch
UART
8kbyte
FLASH
256 byte
SRAM
POR
SFR Bus
8
0
5
1
C
o
r
e
Timer 0, 1
PCA/
WDT
8-bit
500ksps
ADC
A
M
U
X
AIN0-AIN7
P
0
D
r
v
VREF
X
B
A
R
Port I/O Mode
& Config.
XBAR
Control
Reset
XTAL1
XTAL2
External
Oscillator
Circuit
System Clock
Precision
Internal
Oscillator
Clock & Reset
Configuration
Analog/Digital
Power
Debug HW
VDD
ADC
Config. &
Control
SMBus
x2
x4
x2
C2D
C2D
CP0
PGA
+
-
Temp
CP0
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/C2D
VDD
GND
/RST/C2CK
Brown-
Out
VDD
CNVSTR
Port 0
Latch
UART
8k/4k/2k
byte
FLASH
256 byte
SRAM
POR
SFR Bus
8
0
5
1
C
o
r
e
Timer 0, 1
PCA/
WDT
P
0
D
r
v
X
B
A
R
Port I/O Mode
& Config.
XBAR
Control
Reset
XTAL1
XTAL2
External
Oscillator
Circuit
System Clock
Precision
Internal
Oscillator
Clock & Reset
Configuration
Analog/Digital
Power
Debug HW
SMBus
x2
x4
x2
C2D
C2D
CP0
+
-
CP0
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6
P0.7/C2D
VDD
GND
/RST/C2CK
Brown-
Out
II-1 , ‘ SILIEIJN LABS
C8051F300/1/2/3/4/5
16 Rev. 2.9
1.1. CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F300/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51
is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can
be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052,
including two standard 16-bit counter/timers, one enhanced 16-bit counter/timer with external oscillator
input, a full-duplex UART with extended baud rate configuration, 256 bytes of internal RAM, 128 byte Spe-
cial Function Register (SFR) address space, and a byte-wide I/O Port.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12 to 24 MHz. By contrast, the CIP-51 core exe-
cutes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.3
shows a comparison of peak throughputs for various 8-bit microcontroller cores with their maximum sys-
tem clocks.
Figure 1.3. Comparison of Peak MCU Execution Speeds
Clocks to Execute 1 2 2/3 33/4 44/5 5 8
Number of Instructions 26 50 514 73121
5
10
15
20
ADuC812
8051
(16 MHz clk)
Philips
80C51
(33 MHz clk)
Microchip
PIC17C75x
(33 MHz clk)
Silicon Labs
CIP-51
(25 MHz clk)
MIPS
25
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 17
1.1.3. Additional Features
The C8051F300/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and periph-
erals to improve performance and ease of use in end applications.
The extended interrupt handler provides 12 interrupt sources into the CIP-51 (as opposed to 7 for the stan-
dard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven
system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt
sources are very useful when building multitasking, real-time systems.
Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset
when power supply voltage drops below 2.7 V), a Watchdog Timer, a Missing Clock Detector, a voltage
level detection from Comparator0, a forced software reset, an external reset pin, and an illegal Flash
read/write protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash protection
may be disabled by the user in software. The WDT may be permanently enabled in software after a power-
on reset during MCU initialization.
The internal oscillator is available as a factory calibrated 24.5 MHz ±2% (C8051F300/1 devices); an uncal-
ibrated version is available on C8051F302/3/4/5 devices. On all C8051F300/1/2/3/4/5 devices, the internal
oscillator period may be user programmed in ~0.5% increments. An external oscillator drive circuit is also
included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate
the system clock. If desired, the system clock source may be switched on-the-fly to the external oscillator
circuit. An external oscillator can be extremely useful in low power applications, allowing the MCU to run
from a slow (power saving) external crystal source, while periodically switching to the fast (up to 25 MHz)
internal oscillator as needed.
Figure 1.4. On-Chip Clock and Reset
PCA
WDT
Missing
Clock
Detector
(one-
shot) (Software Reset)
System Reset
Reset
Funnel
P0.x
P0.y
EN
SWRSF
Internal
Oscillator System
Clock
CIP-51
Microcontroller
Core
Extended Interrupt
Handler
Clock Select
EN
WDT
Enable
MCD
Enable
XTAL1
XTAL2
External
Oscillator
Drive
Illegal
FLASH
Operation
+
-
Comparator 0
C0RSEF
/RST
(wired-OR)
Power On
Reset
+
-
VDD
Supply
Monitor
Enable
'0'
, . SILIEUN LABS
C8051F300/1/2/3/4/5
18 Rev. 2.9
1.2. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
The C8051F300/1/2/3 includes 8k bytes of Flash program memory (the C8051F304 includes 4k bytes; the
C8051F305 includes 2k bytes). This memory may be reprogrammed in-system in 512 byte sectors, and
requires no special off-chip programming voltage. See Figure 1.5 for the C8051F300/1/2/3 system memory
map.
Figure 1.5. On-chip Memory Map (C8051F300/1/2/3 Shown)
PROGRAM MEMORY
(Direct and Indirect
Addressing)
0x00
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
0x80
0xFF Special Function
Register's
(Direct Addressing Only)
DATA MEMORY
General Purpose
Registers
0x1F
0x20
0x2F Bit Addressable
Lower 128 RAM
(Direct and Indirect
Addressing)
0x30
INTERNAL DATA ADDRESS SPACE
8k bytes
FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
RESERVED
0x1E00
0x1DFF
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 19
1.3. On-Chip Debug Circuitry
The C8051F300/1/2/3/4/5 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides
non-intrusive, full-speed, in-circuit debugging of the production part installed in the end application.
Silicon Labs' debugging system supports inspection and modification of memory and registers, break-
points, and single stepping. No additional target RAM, program memory, timers, or communications chan-
nels are required. All the digital and analog peripherals are functional and work correctly while debugging.
All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single
stepping, or at a breakpoint in order to keep them synchronized.
The C8051F300DK development kit provides all the hardware and software necessary to develop applica-
tion code and perform in-circuit debugging with the C8051F300/1/2/3/4/5 MCUs. The kit includes software
with a developer's studio and debugger, an integrated 8051 assembler, and a C2 debug adapter. It also
has a target application board with the associated MCU installed and large prototyping area, plus the nec-
essary communication cables and wall-mount power supply. The Development Kit requires a computer
with Windows® 98 SE or later. The Silicon Labs IDE interface is a vastly superior developing and debug-
ging configuration, compared to standard MCU emulators that use onboard "ICE Chips" and require the
MCU in the application board to be socketed. Silicon Labs' debug paradigm increases ease of use and
preserves the performance of the precision analog peripherals.
Figure 1.6. Development/In-System Debug Diagram
1.4. Programmable Digital I/O and Crossbar
C8051F300/1/2/3/4/5 devices include a byte-wide I/O Port that behaves like a typical 8051 Port with a few
enhancements. Each Port pin may be configured as an analog input or a digital I/O pin. Pins selected as
digital I/Os may additionally be configured for push-pull or open-drain output. The “weak pull-ups” that are
fixed on typical 8051 devices may be globally disabled, providing power savings capabilities.
, . SILIEUN LABS
C8051F300/1/2/3/4/5
20 Rev. 2.9
Perhaps the most unique Port I/O enhancement is the Digital Crossbar. This is essentially a digital switch-
ing network that allows mapping of internal digital system resources to Port I/O pins (See Figure 1.7). On-
chip counter/timers, serial buses, HW interrupts, comparator output, and other digital signals in the control-
ler can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This allows
the user to select the exact mix of general purpose Port I/O and digital resources needed for the particular
application.
Figure 1.7. Digital Crossbar Diagram
1.5. Serial Ports
The C8051F300/1/2/3/4/5 Family includes an SMBus/I2C interface and a full-duplex UART with enhanced
baud rate configuration. Each of the serial buses is fully implemented in hardware and makes extensive
use of the CIP-51's interrupts, thus requiring very little CPU intervention.
XBR0, XBR1,
XBR2 Registers
Digital
Crossbar
Priority
Decoder
SYSCLK
2
2
(Internal Digital Signals)
Highest
Priority
Lowest
Priority
P0
I/O
Cells
P0.0
P0.7
8
P0MDOUT,
P0MDIN Registers
SMBus
UART
T0, T1 2
4
PCA
P0Port Latch (P0.0-P0.7)
8
CP0
Outputs
2
SSSSSSSSSSS
C8051F300/1/2/3/4/5
Rev. 2.9 21
1.6. Programmable Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the three 16-bit general
purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with three pro-
grammable capture/compare modules. The PCA clock is derived from one of six sources: the system clock
divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system
clock, or the external oscillator clock source divided by 8. The external clock source selection is useful for
real-time clock functionality, where the PCA is clocked by an external source while the internal oscillator
drives the system clock.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture,
Software Timer, High Speed Output, 8- or 16-bit Pulse Width Modulator, or Frequency Output. Additionally,
Capture/Compare Module 2 offers watchdog timer (WDT) capabilities. Following a system reset, Module 2
is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input
may be routed to Port I/O via the Digital Crossbar.
Figure 1.9. PCA Block Diagram
16-Bit Counter/Timer
CEX1
ECI
Digital Crossbar
CEX2
CEX0
Port I/O
Capture/Compare
Module 1
Capture/Compare
Module 0 Capture/Compare
Module 2
PCA
CLOCK
MUX
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
, . SILIEUN LABS
C8051F300/1/2/3/4/5
22 Rev. 2.9
1.7. 8-Bit Analog to Digital Converter (C8051F300/2 Only)
The C8051F300/2 includes an on-chip 8-bit SAR ADC with a 10-channel differential input multiplexer and
programmable gain amplifier. With a maximum throughput of 500 ksps, the ADC offers true 8-bit accuracy
with an INL of ±1LSB. The ADC system includes a configurable analog multiplexer that selects both posi-
tive and negative ADC inputs. Each Port pin is available as an ADC input; additionally, the on-chip Tem-
perature Sensor output and the power supply voltage (VDD) are available as ADC inputs. User firmware
may shut down the ADC to save power.
The integrated programmable gain amplifier (PGA) amplifies the ADC input by 0.5, 1, 2, or 4 as defined by
user software. The gain stage is especially useful when different ADC input channels have widely varied
input voltage signals, or when it is necessary to "zoom in" on a signal with a large DC offset.
Conversions can be started in five ways: a software command, an overflow of Timer 0, 1, or 2, or an exter-
nal convert start signal. This flexibility allows the start of conversion to be triggered by software events, a
periodic signal (timer overflows), or external HW signals. Conversion completions are indicated by a status
bit and an interrupt (if enabled). The resulting 8-bit data word is latched into an SFR upon completion of a
conversion.
Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is
either within or outside of a specified range. The ADC can monitor a key voltage continuously in back-
ground mode, but not interrupt the controller unless the converted data is within/outside the specified
range.
Figure 1.10. 8-Bit ADC Block Diagram
X
VDD
8
9-to-1
AMUX
Temp
Sensor
10-to-1
AMUX
VDD
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
DGND
Programmable Gain
Amplifier
Start
Conversion
Window Compare
Logic
Window
Compare
Interrupt
+
-
Configuration, Control, and Data Registers
Analog Multiplexer
T0 Overflow
TMR2 Overflow
T1 Overflow
Software Write
External
Convert Start
8-Bit
SAR
ADC
End of
Conversion
Interrupt
ADC Data
Register
$5 fig SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 23
1.8. Comparator
C8051F300/1/2/3/4/5 devices include an on-chip voltage comparator that is enabled/disabled and config-
ured via user software. All Port I/O pins may be configurated as comparator inputs. Two comparator out-
puts may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output.
Comparator response time is programmable, allowing the user to select between high-speed and low-
power modes. Positive and negative hysteresis is also configurable.
Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these inter-
rupts may be used as a “wake-up” source. The comparator may also be configured as a reset source.
Figure 1.11. Comparator Block Diagram
Reset
Decision
Tree
+
-
Crossbar
Interrupt
Handler
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP0 +
P0.0
P0.2
P0.4
P0.6
CP0 -
P0.1
P0.3
P0.5
P0.7
VDD
, . SILIEUN LABS
C8051F300/1/2/3/4/5
24 Rev. 2.9
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings*
Parameter Conditions Min Typ Max Units
Ambient temperature under bias –55 125 °C
Storage Temperature –65 150 °C
Voltage on any Port I/O Pin or RST with respect to
GND –0.3 5.8 V
Voltage on VDD with respect to GND –0.3 4.2 V
Maximum Total current through VDD and GND 500 mA
Maximum output current sunk by RST or any Port pin 100 mA
*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 25
3. Global Electrical Characteristics
Table 3.1. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter Conditions Min Typ Max Units
Digital Supply Voltage VRST13.0 3.6 V
Digital Supply RAM Data
Retention Voltage —1.5— V
SYSCLK (System Clock)
(Note 2)
0—25MHz
TSYSH (SYSCLK High Time) 18 ns
TSYSL (SYSCLK Low Time) 18 ns
Specified Operating
Temperature Range –40 — +85 °C
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash)
IDD (Note 3) VDD = 3.6 V, F = 25 MHz 9.4 10.2 mA
VDD = 3.0 V, F = 25 MHz 6.6 7.2 mA
VDD = 3.0 V, F = 1 MHz 0.45 mA
VDD = 3.0 V, F = 80 kHz 36 µA
IDD Supply Sensitivity (Note 3) F = 25 MHz 69 %/V
F = 1 MHz 51 %/V
IDD Frequency Sensitivity
(Note 3, Note 4)
VDD = 3.0 V, F <= 15 MHz, T = 25 °C 0.45 — mA/MHz
VDD = 3.0 V, F > 15 MHz, T = 25 °C 0.16 — mA/MHz
VDD = 3.6 V, F <= 15 MHz, T = 25 °C 0.69 — mA/MHz
VDD = 3.6 V, F > 15 MHz, T = 25 °C 0.20 — mA/MHz
Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash)
IDD (Note 3) VDD = 3.6 V, F = 25 MHz 3.3 4.0 mA
VDD = 3.0 V, F = 25 MHz 2.5 3.2 mA
VDD = 3.0 V, F = 1 MHz 0.10 mA
VDD = 3.0 V, F = 80 kHz 8 µA
, . SILIEUN LABS
C8051F300/1/2/3/4/5
26 Rev. 2.9
IDD Supply Sensitivity (Note 3) F = 25 MHz 47 %/V
F = 1 MHz 59 %/V
IDD Frequency Sensitivity
(Note 3, Note 5)
VDD = 3.0 V, F <= 1 MHz, T = 25 °C 0.27 — mA/MHz
VDD = 3.0 V, F > 1 MHz, T = 25 °C 0.10 — mA/MHz
VDD = 3.6 V, F <= 1 MHz, T = 25 °C 0.35 — mA/MHz
VDD = 3.6 V, F > 1 MHz, T = 25 °C 0.12 — mA/MHz
Digital Supply Current
(Stop Mode, shutdown) Oscillator not running,
VDD Monitor Disabled —< 0.1— µA
Notes:
1. Given in Table 9.2 on page 86.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Based on device characterization data; Not production tested.
4. Normal IDD can be estimated for frequencies <= 15 MHz by simply multiplying the frequency of interest by
the frequency sensitivity number for that range. When using these numbers to estimate IDD for >15 MHz, the
estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity
number.
For example: VDD = 3.0 V; F = 20 MHz, IDD = 6.6 mA(25 MHz20 MHz) x 0.16 mA/MHz = 5.8 mA.
5. Idle IDD can be estimated for frequencies <= 1 MHz by simply multiplying the frequency of interest by the
frequency sensitivity number for that range. When using these numbers to estimate Idle IDD for >1 MHz, the
estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity
number.
For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 3.3 mA(25 MHz – 5 MHz) x 0.10 mA/MHz = 1.3 mA.
Table 3.1. Global Electrical Characteristics (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter Conditions Min Typ Max Units
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 27
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F300/1/2/3/4/5
Name Pin
F300/1/2/3/4/5
GM
Pin
F300/1/2/3/4/5
GP
Type Description
VREF /
P0.0
1 5 A In
D I/O or
A In
External Voltage Reference Input.
Port 0.0. See Section 12 for complete description.
P0.1 2 6 D I/O or
A In Port 0.1. See Section 12 for complete description.
VDD 3 7 Power Supply Voltage.
XTAL1 /
P0.2
4 8 A In
D I/O or
A In
Crystal Input. This pin is the external oscillator cir-
cuit return for a crystal or ceramic resonator. See
Section 11.2.
Port 0.2. See Section 12 for complete description.
XTAL2 /
P0.3
510 A Out
D I/O
Crystal Input/Output. For an external crystal or res-
onator, this pin is the excitation driver. This pin is
the external clock input for CMOS, capacitor, or RC
network configurations. See Section 11.2.
Port 0.3. See Section 12 for complete description.
P0.4 612 D I/O or
A In Port 0.4. See Section 12 for complete description.
P0.5 713 D I/O or
A In Port 0.5. See Section 12 for complete description.
C2CK /
RST
814 D I/O
D I/O
Clock signal for the C2 Development Interface.
Device Reset. Open-drain output of internal POR or
VDD monitor. An external source can initiate a sys-
tem reset by driving this pin low for at least 10 µs.
P0.6 /
CNVSTR
9 1 D I/O or
A In
D I/O
Port 0.6. See Section 12 for complete description.
ADC External Convert Start Input Strobe.
C2D /
P0.7
10 2D I/O
D I/O or
A In
Data signal for the C2 Development Interface.
Port 0.7. See Section 12 for complete description.
GND 11 3Ground.
N.C. pins for F30x GP packages: 4, 9, 11
SILIEUN LABS
C8051F300/1/2/3/4/5
28 Rev. 2.9
Figure 4.1. QFN-11 Pinout Diagram (Top View)
VREF /
P0.0
P0.1
VDD
XTAL1 /
P0.2
XTAL2 /
P0.3 P0.4
P0.5
C2CK /
/RST
P0.6 /
CNVSTR
C2D /
P0.7
GND
[ g3 :‘ C :, :3 3 ‘: 71 ‘74‘ r HT ’HWWH‘ VMV _n# \mm 1: , . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 29
Figure 4.2. QFN-11 Package Drawing
Table 4.2. QFN-11 Package Dimensions
Dimension Min Nom Max Dimension Min Nom Max
A0.80 0.90 1.00 E3.00 BSC.
A1 0.03 0.07 0.11 E2 2.20 2.25 2.30
A3 0.25 REF L.45 .55 .65
b0.18 0.25 0.30 aaa -- -- 0.15
D3.00 BSC. bbb -- -- 0.15
D2 1.30 1.35 1.40 ddd -- -- 0.05
e0.50 BSC. eee -- -- 0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-243, variation VEED except for custom features D2, E2, and L
which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
, . SILIEUN LABS
C8051F300/1/2/3/4/5
30 Rev. 2.9
Figure 4.3. Typical QFN-11 Solder Paste Mask
0.50 mm
LT
e
E
D
e
LB
k
D2
b
L
D4
0.10 mm
0.50 mm
0.35 mm
0.30 mm
0.10 mm
0.20 mm
0.30 mm 0.20 mm
0.60 mm 0.70 mm
D4
b
0.30 mm
0.35 mm
E2
0.20 mm
IIBIE ‘ +57 ++»\,E , . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 31
.
Figure 4.4. Typical QFN-11 Landing Diagram
Table 4.3. QFN-11 Landing Diagram Dimensions
Dimension MIN MAX
C1 2.75 2.85
C2 2.75 2.85
E 0.50 BSC
X1 0.20 0.30
X2 1.40 1.50
Y1 0.65 0.75
Y2 2.30 2.40
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
Notes: Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to
assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A 3 x 1 array of 1.30 x 0.60 mm openings on 0.80 mm pitch should be used for the center
ground pad.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for
Small Body Components.
33:3333 SILIEUN LABS O 33:33::
C8051F300/1/2/3/4/5
32 Rev. 2.9
Figure 4.5. SOIC-14 Pinout Diagram (Top View)
2
1
4
3
5
6
7
13
14
11
12
10
9
8
TOP VIEW
C2D/P0.7
P0.6
GND
N/C
P0.0
P0.1
VDD
P0.3
P0.5
C2CK/RST
P0.4
N/C
N/C
P0.2
'¥‘ \ mp 1|: , . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 33
Figure 4.6. SOIC-14 Package Drawing
Table 4.4. SOIC-14 Package Dimensions
Dimension Min Max Dimension Min Max
A- - - 1.75 L0.40 1.27
A1 0.10 0.25 L2 0.25 BSC
b0.33 0.51 Q 0°8°
c0.17 0.25 aaa 0.10
D8.65 BSC bbb 0.20
E6.00 BSC ccc 0.10
E1 3.90 BSC ddd 0.25
e1.27 BSC
Notes:
1. All dimensions shown are in millimeters (mm).
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MS012, variation AB.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for
Small Body Components.
My , . SILIEUN LABS
C8051F300/1/2/3/4/5
34 Rev. 2.9
Figure 4.7. SOIC-14 PCB Land Pattern
Table 4.5. SOIC-14 PCB Land Pattern Dimensions
Dimension Min Max
C1 5.30 5.40
E1.27 BSC
X1 0.50 0.60
Y1 1.45 1.55
SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 35
5. ADC0 (8-Bit ADC, C8051F300/2)
The ADC0 subsystem for the C8051F300/2 consists of two analog multiplexers (referred to collectively as
AMUX0) with 11 total input selections, a differential programmable gain amplifier (PGA), and a 500 ksps, 8-
bit successive-approximation-register ADC with integrated track-and-hold and programmable window
detector (see block diagram in Figure 5.1). The AMUX0, PGA, data conversion modes, and window detec-
tor are all configurable under software control via the Special Function Registers shown in Figure 5.1.
ADC0 operates in both Single-ended and Differential modes, and may be configured to measure any Port
pin, the Temperature Sensor output, or VDD with respect to any Port pin or GND. The ADC0 subsystem is
enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 sub-
system is in low power shutdown when this bit is logic 0.
Figure 5.1. ADC0 Functional Block Diagram
AMUX0
+
-
X
VDD
ADC0CF
AMP0GN0
AMP0GN1
AD0SC0
AD0SC1
AD0SC2
AD0SC3
AD0SC4
8-Bit
SAR
ADC
REF
8
SYSCLK
ADC0
16
ADC0CN
AD0CM0
AD0CM1
AD0CM2
AD0WINT
AD0BUSY
AD0INT
AD0TM
AD0EN
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
Start
Conversion
000 AD0BUSY (W)
VDD
ADC0GT
ADC0LT
9-to-1
AMUX
AD0WINT
Temp
Sensor
10-to-1
AMUX
VDD
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
GND
001
010
011
1xx CNVSTR Input
Comb.
Logic
AMX0SL
AMX0P0
AMX0P1
AMX0P2
AMX0N3
AMX0N2
AMX0N1
AMX0N0
AMX0P3
, . SILIEUN LABS
C8051F300/1/2/3/4/5
36 Rev. 2.9
5.1. Analog Multiplexer and PGA
The analog multiplexers (AMUX0) select the positive and negative inputs to the PGA, allowing any Port pin
to be measured relative to any other Port pin or GND. Additionally, the on-chip temperature sensor or the
positive power supply (VDD) may be selected as the positive PGA input. When GND is selected as the
negative input, ADC0 operates in Single-ended Mode; all other times, ADC0 operates in Differential
Mode. The ADC0 input channels are selected in the AMX0SL register as described in SFR Definition 5.1.
The conversion code format differs in Single-ended versus Differential modes, as shown below. When in
Single-ended Mode (negative input is selected GND), conversion codes are represented as 8-bit unsigned
integers. Inputs are measured from ‘0’ to VREF x 255/256. Example codes are shown below.
When in Differential Mode (negative input is not selected as GND), conversion codes are represented as
8-bit signed 2s complement numbers. Inputs are measured from –VREF to VREF x 127/128. Example
codes are shown below.
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to ‘0’ the corresponding bit in register P0MDIN. To force the Crossbar to skip a Port pin, set to ‘1’
the corresponding bit in register XBR0. See Section “12. Port Input/Output” on page 103 for more Port
I/O configuration details.
The PGA amplifies the AMUX0 output signal as defined by the AMP0GN1-0 bits in the ADC0 Configuration
register (SFR Definition 5.2). The PGA is software-programmable for gains of 0.5, 1, 2, or 4. The gain
defaults to 0.5 on reset.
5.2. Temperature Sensor
The typical temperature sensor transfer function is shown in Figure 5.2. The output voltage (VTEMP) is the
positive PGA input when the temperature sensor is selected by bits AMX0P2-0 in register AMX0SL; this
voltage will be amplified by the PGA according to the user-programmed PGA settings.
Input Voltage ADC0 Output (Conversion Code)
VREF x 255/256 0xFF
VREF x 128/256 0x80
VREF x 64/256 0x40
00x00
Input Voltage ADC0 Output (Conversion Code)
VREF x 127/128 0x7F
VREF x 64/128 0x40
00x00
–VREF x 64/128 0xC0
–VREF 0x80
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 37
Figure 5.2. Typical Temperature Sensor Transfer Function
The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature mea-
surements (see Table 5.1 for linearity specifications). For absolute temperature measurements, gain and/
or offset calibration is recommended. Typically a 1-point calibration includes the following steps:
Step 1. Control/measure the ambient temperature (this temperature must be known).
Step 2. Power the device, and delay for a few seconds to allow for self-heating.
Step 3. Perform an ADC conversion with the temperature sensor selected as the positive input
and GND selected as the negative input.
Step 4. Calculate the offset and/or gain characteristics, and store these values in non-volatile
memory for use with subsequent temperature sensor measurements.
Figure 5.3 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Note that
parameters which affect ADC measurement, in particular the voltage reference value, will also
affect temperature measurement.
0-50 50 100
(Celsius)
V
TEMP
= 3.35*(TEMP
C
) + 897 mV
700
800
900
1000
1100
(mV)
1200
40 on 720 no 000 20 on 40 no so on so on ‘5’ SILIEUN LABS
C8051F300/1/2/3/4/5
38 Rev. 2.9
Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V)
-40.00 -20.00 0.00 20.00 40.00 60.00 80.00
Temperature (degrees C)
Error (degrees C)
-5.00
-4.00
-3.00
-2.00
-1.00
0.00
1.00
2.00
3.00
4.00
5.00
-5.00
-4.00
-3.00
-2.00
-1.00
0.00
1.00
2.00
3.00
4.00
5.00
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 39
5.3. Modes of Operation
ADC0 has a maximum conversion speed of 500 ksps. The ADC0 conversion clock is a divided version of
the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by
(AD0SC + 1) for 0 AD0SC 31).
5.3.1. Starting a Conversion
A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the fol-
lowing:
1. Writing a ‘1’ to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e. timed continuous conversions)
3. A Timer 2 overflow
4. A Timer 1 overflow
5. A rising edge on the CNVSTR input signal (pin P0.6)
Writing a ‘1’ to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-
demand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)
should be used. Converted data is available in the ADC0 data register, ADC0, when bit AD0INT is logic 1.
Note that when Timer 2 overflows are used as the conversion source, Timer 2 Low Byte overflows are
used if Timer 2 is in 8-bit mode; Timer 2 High byte overflows are used if Timer 2 is in 16-bit mode. See Sec-
tion “15. Timers” on page 143 for timer configuration.
Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.6. When the
CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital
Crossbar. To configure the Crossbar to skip P0.6, set to ‘1’ Bit6 in register XBR0. See Section “12. Port
Input/Output” on page 103 for details on Port I/O configuration.
, . SILIEUN LABS
C8051F300/1/2/3/4/5
40 Rev. 2.9
5.3.2. Tracking Modes
According to Table 5.1 on page 47, each ADC0 conversion must be preceded by a minimum tracking time
for the converted result to be accurate. The AD0TM bit in register ADC0CN controls the ADC0 track-and-
hold mode. In its default state, the ADC0 input is continuously tracked except when a conversion is in prog-
ress. When the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold mode. In this mode,
each conversion is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal).
When the CNVSTR signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only
when CNVSTR is low; conversion begins on the rising edge of CNVSTR (see Figure 5.4). Tracking can
also be disabled (shutdown) when the device is in low power standby or sleep modes. Low-power track-
and-hold mode is also useful when AMUX or PGA settings are frequently changed, due to the settling time
requirements described in Section “5.3.3. Settling Time Requirements” on page 41.
Figure 5.4. 8-Bit ADC Track and Conversion Example Timing
Write '1' to AD0BUSY,
Timer 0, Timer 2, Timer 1 Overflow
(AD0CM[2:0]=000, 001, 010, 011)
AD0TM=1 Track Convert Low Power
Mode
AD0TM=0 Track or
Convert Convert Track
Low Power
or Convert
SAR
Clocks
SAR
Clocks
B. ADC Timing for Internal Trigger Source
123456789
CNVSTR
(AD0CM[2:0]=1xx)
AD0TM=1
A. ADC Timing for External Trigger Source
SAR Clocks
Track or Convert Convert TrackAD0TM=0
Track Convert Low Power
Mode
Low Power
or Convert
10 11 12
12345678910 11 12
12345678910 11 12
13 14 15
XJ “‘ f E KP T w P , . SILIEUN LABS H J
C8051F300/1/2/3/4/5
Rev. 2.9 41
5.3.3. Settling Time Requirements
When the ADC0 input configuration is changed (i.e., a different AMUX0 or PGA selection is made), a mini-
mum tracking time is required before an accurate conversion can be performed. This tracking time is deter-
mined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the
accuracy required for the conversion. Note that in low-power tracking mode, three SAR clocks are used for
tracking at the start of every conversion. For most applications, these three SAR clocks will meet the mini-
mum tracking time requirements.
Figure 5.5 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes. Notice
that the equivalent time constant for both input circuits is the same. The required ADC0 settling time for a
given settling accuracy (SA) may be approximated by Equation 5.1. When measuring the Temperature
Sensor output or VDD with respect to GND, RTOTAL reduces to RMUX. See Table 5.1 for ADC0 minimum
settling time (track/hold time) requirements.
Equation 5.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
RTOTAL is the sum of the AMUX0 resistance and any external source resistance.
n is the ADC resolution in bits (8).
Figure 5.5. ADC0 Equivalent Input Circuits
t2n
SA
-------

RTOTALCSAMPLE
×ln=
R
MUX
= 5k
RC
Input
= R
MUX
* C
SAMPLE
R
MUX
= 5k
C
SAMPLE
= 5pF
C
SAMPLE
= 5pF
MUX Select
MUX Select
Differential Mode
P0.x
P0.y
R
MUX
= 5k
C
SAMPLE
= 5pF
RC
Input
= R
MUX
* C
SAMPLE
MUX Select
Single-Ended Mode
P0.x
Note: When the PGA gain is set to 0.5, C
SAMPLE
= 3pF
, . SILIEUN LABS
C8051F300/1/2/3/4/5
42 Rev. 2.9
SFR Definition 5.1. AMX0SL: AMUX0 Channel Select (C8051F300/2)
Bits7–4: AMX0N3–0: AMUX0 Negative Input Selection.
Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended
mode. For all other Negative Input selections, ADC0 operates in Differential mode.
0000–1000b: ADC0 Negative Input selected per the chart below.
Bits3–0: AMX0P3–0: AMUX0 Positive Input Selection.
0000–1001b: ADC0 Positive Input selected per the chart below.
1010–1111b: RESERVED.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AMX0N3 AMX0N2 AMX0N1 AMX0N0 AMX0P3 AMX0P2 AMX0P1 AMX0P0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xBB
AMX0N3–0 ADC0 Negative Input
0000 P0.0
0001 P0.1
0010 P0.2
0011 P0.3
0100 P0.4
0101 P0.5
0110 P0.6
0111 P0.7
1xxx GND (ADC in Single-Ended Mode)
AMX0P3–0 ADC0 Positive Input
0000 P0.0
0001 P0.1
0010 P0.2
0011 P0.3
0100 P0.4
0101 P0.5
0110 P0.6
0111 P0.7
1000 Temperature Sensor
1001 VDD
SA R , . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 43
SFR Definition 5.2. ADC0CF: ADC0 Configuration (C8051F300/2)
SFR Definition 5.3. ADC0: ADC0 Data Word (C8051F300/2)
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements
are given in Table 5.1.
Bit2: UNUSED. Read = 0b; Write = don’t care.
Bits1–0: AMP0GN1–0: ADC0 Internal Amplifier Gain (PGA).
00: Gain = 0.5
01: Gain = 1
10: Gain = 2
11: Gain = 4
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AMP0GN1 AMP0GN0 11111000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xBC
AD0SC SYSCLK
CLKSAR
----------------------1=
Bits7–0: ADC0 Data Word.
ADC0 holds the output data byte from the last ADC0 conversion. When in Single-ended
mode, ADC0 holds an 8-bit unsigned integer. When in Differential mode, ADC0 holds a 2’s
complement signed 8-bit integer.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xBE
, . SILIEUN LABS
C8051F300/1/2/3/4/5
44 Rev. 2.9
SFR Definition 5.4. ADC0CN: ADC0 Control (C8051F300/2)
Bit7: AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
Bit6: AD0TM: ADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion
is in progress.
1: Low-power Track Mode: Tracking Defined by AD0CM2-0 bits (see below).
Bit5: AD0INT: ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since the last time AD0INT was cleared.
1: ADC0 has completed a data conversion.
Bit4: AD0BUSY: ADC0 Busy Bit.
Read: Unused.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if AD0CM2-0 = 000b
Bit3: AD0WINT: ADC0 Window Compare Interrupt Flag.
0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC0 Window Comparison Data match has occurred.
Bits2–0: AD0CM2-0: ADC0 Start of Conversion Mode Select.
When AD0TM = 0:
000: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 1.
1xx: ADC0 conversion initiated on rising edge of external CNVSTR.
When AD0TM = 1:
000: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR clocks, followed by con-
version.
001: Tracking initiated on overflow of Timer 0 and lasts 3 SAR clocks, followed by conver-
sion.
010: Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks, followed by conver-
sion.
011: Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conver-
sion.
1xx: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising
CNVSTR edge.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable) 0xE8
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 45
5.4. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output to user-programmed
limits, and notifies the system when a desired condition is detected. This is especially effective in an inter-
rupt-driven system, saving code space and CPU bandwidth while delivering faster system response times.
The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in polled mode. The
ADC0 Greater-Than (ADC0GT) and Less-Than (ADC0LT) registers hold the comparison values. Example
comparisons for Single-ended and Differential modes are shown in Figure 5.6 and Figure 5.7, respectively.
Notice that the window detector flag can be programmed to indicate when measured data is inside or out-
side of the user-programmed limits depending on the contents of the ADC0LT and ADC0GT registers.
5.4.1. Window Detector In Single-Ended Mode
Figure 5.6 shows two example window comparisons for Single-ended mode, with ADC0LT = 0x20 and
ADC0GT = 0x10. Notice that in Single-ended mode, the codes vary from 0 to VREF x (255/256) and are
represented as 8-bit unsigned integers. In the left example, an AD0WINT interrupt will be generated if the
ADC0 conversion word (ADC0) is within the range defined by ADC0GT and ADC0LT
(if 0x10 < ADC0 < 0x20). In the right example, and AD0WINT interrupt will be generated if ADC0 is outside
of the range defined by ADC0GT and ADC0LT (if ADC0 < 0x10 or ADC0 > 0x20).
Figure 5.6. ADC Window Compare Examples, Single-Ended Mode
0xFF
0x21
0x20
0x1F
0x11
0x10
0x0F
0x00
0
Input Voltage
(P0.x - GND)
REF x (255/256)
REF x (32/256)
REF x (16/256)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LT
ADC0GT
0xFF
0x21
0x20
0x1F
0x11
0x10
0x0F
0x00
0
Input Voltage
(P0.x - GND)
REF x (255/256)
REF x (32/256)
REF x (16/256)
AD0WINT
not affected
ADC0GT
ADC0LT
AD0WINT=1
AD0WINT=1
ADC0 ADC0
, . SILIEUN LABS
C8051F300/1/2/3/4/5
46 Rev. 2.9
5.4.2. Window Detector In Differential Mode
Figure 5.7 shows two example window comparisons for differential mode, with ADC0LT = 0x10 (+16d) and
ADC0GT = 0xFF (–1d). Notice that in Differential mode, the codes vary from –VREF to VREF x (127/128)
and are represented as 8-bit 2’s complement signed integers. In the left example, an AD0WINT interrupt
will be generated if the ADC0 conversion word (ADC0L) is within the range defined by ADC0GT and
ADC0LT (if 0xFF (–1d) < ADC0 < 0x10 (16d)). In the right example, an AD0WINT interrupt will be gener-
ated if ADC0 is outside of the range defined by ADC0GT and ADC0LT (if ADC0 < 0xFF (–1d) or ADC0 >
0x10 (+16d)).
Figure 5.7. ADC Window Compare Examples, Differential Mode
SFR Definition 5.5. ADC0GT: ADC0 Greater-Than Data Byte (C8051F300/2)
SFR Definition 5.6. ADC0LT: ADC0 Less-Than Data Byte (C8051F300/2)
0x7F (127d)
0x11 (17d)
0x10 (16d)
0x0F (15d)
0x00 (0d)
0xFF (-1d)
0xFE (-2d)
0x80 (-128d)
-REF
Input Voltage
(P0.x - P0.y)
REF x (127/128)
REF x (16/128)
REF x (-1/256)
0x7F (127d)
0x11 (17d)
0x10 (16d)
0x0F (15d)
0x00 (0d)
0xFF (-1d)
0xFE (-2d)
0x80 (-128d)
-REF
Input Voltage
(P0.x - P0.y)
REF x (127/128)
REF x (16/128)
REF x (-1/256)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LT
ADC0GT
AD0WINT
not affected
ADC0GT
ADC0LT
AD0WINT=1
AD0WINT=1
ADC0ADC0
Bits7–0: ADC0 Greater-Than Data Word.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xC4
Bits7–0: ADC0 Less-Than Data Word.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xC6
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 47
Table 5.1. ADC0 Electrical Characteristics
VDD = 3.0 V, VREF = 2.40 V (REFSL = 0), PGA Gain = 1, –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
DC Accuracy
Resolution 8bits
Integral Nonlinearity ±0.5 ±1 LSB
Differential Nonlinearity Guaranteed Monotonic ±0.5 ±1 LSB
Offset Error –5.0 0.5 5.0 LSB
Full Scale Error Differential mode –5.0 –1 5.0 LSB
Dynamic Performance (10 kHz Sine-wave Differential Input, 1 dB below Full Scale, 500 ksps)
Signal-to-Noise Plus Distortion 45 48 dB
Total Harmonic Distortion Up to the 5th harmonic –56 dB
Spurious-Free Dynamic Range 58 dB
Conversion Rate
SAR Conversion Clock — — 6 MHz
Conversion Time in SAR Clocks 11 — — clocks
Track/Hold Acquisition Time 300 — — ns
Throughput Rate 500 ksps
Analog Inputs
Input Voltage Range 0 VREF V
Input Capacitance — 5 — pF
Temperature Sensor ———
Linearity1,2,3 ±0.5 °C
Gain1,2,3 3350
±110
µV / °C
Offset1,2,3 (Temp = 0 °C) 897±31 mV
Power Specifications
Power Supply Current
(VDD supplied to ADC0) Operating Mode, 500 ksps 400 900 µA
Power Supply Rejection ±0.3 mV/V
Notes:
1. Represents one standard deviation from the mean.
2. Measured with PGA Gain = 2.
3. Includes ADC offset, gain, and linearity variations.
, . SILIEUN LABS
C8051F300/1/2/3/4/5
48 Rev. 2.9
NOTES:
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 49
6. Voltage Reference (C8051F300/2)
The voltage reference MUX on C8051F300/2 devices is configurable to use an externally connected volt-
age reference or the power supply voltage, VDD (see Figure 6.1). The REFSL bit in the Reference Control
register (REF0CN) selects the reference source. For an external source, REFSL should be set to ‘0’; For
VDD as the reference source, REFSL should be set to ‘1’.
The BIASE bit enables the internal voltage bias generator, which is used by the ADC, Temperature Sensor,
and Internal Oscillator. This bit is forced to logic 1 when any of the aforementioned peripherals is enabled.
The bias generator may be enabled manually by writing a ‘1’ to the BIASE bit in register REF0CN; see
SFR Definition 6.1 for REF0CN register details. The electrical specifications for the voltage reference cir-
cuit are given in Table 6.1.
Important Note About the VREF Input: Port pin P0.0 is used as the external VREF input. When using an
external voltage reference, P0.0 should be configured as analog input and skipped by the Digital Crossbar.
To configure P0.0 as analog input, set to ‘1’ Bit0 in register P0MDIN. To configure the Crossbar to skip
P0.0, set to ‘1’ Bit0 in register XBR0. Refer to Section “12. Port Input/Output” on page 103 for complete
Port I/O configuration details. The external reference voltage must be within the range 0 VREF VDD.
On C8051F300/2 devices, the temperature sensor connects to the highest order input of the ADC0 positive
input multiplexer (see Section “5.1. Analog Multiplexer and PGA” on page 36 for details). The TEMPE
bit in register REF0CN enables/disables the temperature sensor. While disabled, the temperature sensor
defaults to a high impedance state and any ADC0 measurements performed on the sensor result in mean-
ingless data.
Figure 6.1. Voltage Reference Functional Block Diagram
Internal
VREF
(to ADC)
To Analog Mux
VDD
VREF
R1
VDD External
Voltage
Reference
Circuit
GND
REF0CN
REFSL
TEMPE
BIASE
Temp Sensor
EN
Bias Generator To ADC, Internal
Oscillator,
Temperature Sensor
EN
IOSCEN
0
1
, . SILIEUN LABS
C8051F300/1/2/3/4/5
50 Rev. 2.9
SFR Definition 6.1. REF0CN: Reference Control Register
Table 6.1. External Voltage Reference Circuit Electrical Characteristics
VDD = 3.0 V; –40 to +85°C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Input Voltage Range 0 — VDD V
Input Current Sample Rate = 500 ksps;
VREF = 3.0 V 12 µA
Bits7–3: UNUSED. Read = 00000b; Write = don’t care.
Bit3: REFSL: Voltage Reference Select.
This bit selects the source for the internal voltage reference.
0: VREF input pin used as voltage reference.
1: VDD used as voltage reference.
Bit2: TEMPE: Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
Bit1: BIASE: Internal Analog Bias Generator Enable Bit. (Must be ‘1’ if using ADC).
0: Internal Bias Generator off.
1: Internal Bias Generator on.
Bit0: UNUSED. Read = 0b. Write = don’t care.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
— — — — REFSL TEMPE BIASE 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xD1
SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 51
7. Comparator0
C8051F300/1/2/3/4/5 devices include an on-chip programmable voltage comparator, which is shown in
Figure 7.1. Comparator0 offers programmable response time and hysteresis, an analog input multiplexer,
and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an
asynchronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system
clock is not active. This allows Comparator0 to operate and generate an output with the device in STOP
mode. When assigned to a Port pin, the Comparator0 output may be configured as open drain or push-pull
(see Section “12.2. Port I/O Initialization” on page 106). Comparator0 may also be used as a reset
source (see Section “9.5. Comparator0 Reset” on page 85).
The inputs for Comparator0 are selected in the CPT0MX register (SFR Definition 7.2). The CMX0P1-CMX-
0P0 bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 nega-
tive input.
Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be con-
figured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “12.3. General Purpose Port I/O” on page 108).
Figure 7.1. Comparator0 Functional Block Diagram
VDD
CPT0CN
Reset
Decision
Tree
+
-
Crossbar
Interrupt
Logic
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP0 +
P0.0
P0.2
P0.4
P0.6
CP0 -
P0.1
P0.3
P0.5
P0.7
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CPT0MX
CMX0N1
CMX0N0
CMX0P1
CMX0P0
CPT0MD
CP0MD1
CP0MD0
CP0
Rising-edge
Interrupt Flag
CP0
Falling-edge
Interrupt Flag
CP0
CP0A
, . SILIEUN LABS
C8051F300/1/2/3/4/5
52 Rev. 2.9
The output of Comparator0 can be polled in software, used as an interrupt source, and/or routed to a Port
pin. When routed to a Port pin, the Comparator0 output is available asynchronous or synchronous to the
system clock; the asynchronous output is available even in STOP mode (with no system clock active).
When disabled, the Comparator0 output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic
low state, and its supply current falls to less than 100 nA. See Section “12.1. Priority Crossbar
Decoder” on page 104 for details on configuring the Comparator0 output via the digital Crossbar. Com-
parator0 inputs can be externally driven from –0.25 to (VDD) + 0.25 V without damage or upset. The com-
plete electrical specifications for Comparator0 are given in Table 7.1.
The Comparator0 response time may be configured in software via the CP0MD1-0 bits in register
CPT0MD (see SFR Definition 7.3). Selecting a longer response time reduces the amount of power con-
sumed by Comparator0. See Table 7.1 for complete timing and power consumption specifications.
Figure 7.2. Comparator Hysteresis Plot
The hysteresis of Comparator0 is software-programmable via its Comparator0 Control register (CPT0CN).
The user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive
and negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator0 hysteresis is programmed using Bits3–0 in the Comparator0 Control Register CPT0CN
(shown in SFR Definition 7.1). The amount of negative hysteresis voltage is determined by the settings of
the CP0HYN bits. As shown in Figure 7.2, settings of 20, 10 or 5 mV of negative hysteresis can be pro-
grammed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is
determined by the setting the CP0HYP bits.
Positive Hysteresis Voltage
(Programmed with CP0HYP Bits)
Negative Hysteresis Voltage
(Programmed by CP0HYN Bits)
VIN-
VIN+
INPUTS
CIRCUIT CONFIGURATION
+
_
CP0+
CP0- CP0
VIN+
VIN-
OUT
V
OH
Positive Hysteresis
Disabled Maximum
Positive Hysteresis
Negative Hysteresis
Disabled Maximum
Negative Hysteresis
OUTPUT
V
OL
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 53
Comparator0 interrupts can be generated on both rising-edge and falling-edge output transitions. (For
Interrupt enable and priority control, see Section “8.3. Interrupt Handler” on page 72). The CP0FIF flag
is set to logic 1 upon a Comparator0 falling-edge interrupt, and the CP0RIF flag is set to logic 1 upon the
Comparator0 rising-edge interrupt. Once set, these bits remain set until cleared by software. The output
state of Comparator0 can be obtained at any time by reading the CP0OUT bit. Comparator0 is enabled by
setting the CP0EN bit to logic 1, and is disabled by clearing this bit to logic 0.
SFR Definition 7.1. CPT0CN: Comparator0 Control
Bit7: CP0EN: Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
Bit6: CP0OUT: Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
Bit5: CP0RIF: Comparator0 Rising-Edge Interrupt Flag.
0: No Comparator0 Rising Edge Interrupt has occurred since this flag was last cleared.
1: Comparator0 Rising Edge Interrupt has occurred.
Bit4: CP0FIF: Comparator0 Falling-Edge Interrupt Flag.
0: No Comparator0 Falling-Edge Interrupt has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge Interrupt has occurred.
Bits3–2: CP0HYP1–0: Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
Bits1–0: CP0HYN1–0: Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
R/W R R/W R/W R/W R/W R/W R/W Reset Value
CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable) 0xF8
, . SILIEUN LABS
C8051F300/1/2/3/4/5
54 Rev. 2.9
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection
Bits7–6: UNUSED. Read = 00b, Write = don’t care.
Bits6–4: CMX0N1–CMX0N0: Comparator0 Negative Input MUX Select.
These bits select which Port pin is used as the Comparator0 negative input.
Bits3–2: UNUSED. Read = 00b, Write = don’t care.
Bits1–0: CMX0P1–CMX0P0: Comparator0 Positive Input MUX Select.
These bits select which Port pin is used as the Comparator0 positive input.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
— — CMX0N1 CMX0N0 — — CMX0P1 CMX0P0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x9F
CMX0N1 CMX0N0 Negative Input
00 P0.1
01 P0.3
10 P0.5
11 P0.7
CMX0P1 CMX0P0 Positive Input
00 P0.0
01 P0.2
10 P0.4
11 P0.6
Bits7–2: UNUSED. Read = 000000b, Write = don’t care.
Bits1–0: CP0MD1–CP0MD0: Comparator0 Mode Select.
These bits select the response time for Comparator0.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
— — — — — — CP0MD1 CP0MD0 00000010
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x9D
Mode CP0MD1 CP0MD0 CP0 Response Time (TYP)
0 0 0 Fastest Response Time
101 —
210 —
3 1 1 Lowest Power Consumption
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 55
Table 7.1. Comparator0 Electrical Characteristics
VDD = 3.0 V, –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Response Time:
Mode 0, Vcm* = 1.5 V
CP0+ – CP0 = 100 mV 100 ns
CP0+ – CP0 = –100 mV 250 ns
Response Time:
Mode 1, Vcm* = 1.5 V
CP0+ – CP0 = 100 mV 175 ns
CP0+ – CP0 = –100 mV 500 ns
Response Time:
Mode 2, Vcm* = 1.5 V
CP0+ – CP0 = 100 mV 320 ns
CP0+ – CP0 = –100 mV 1100 ns
Response Time:
Mode 3, Vcm* = 1.5 V
CP0+ – CP0 = 100 mV 1050 ns
CP0+ – CP0 = –100 mV 5200 ns
Common-Mode Rejection
Ratio 1.5 4mV/V
Positive Hysteresis 1 CP0HYP1–0 = 00 — 0 1 mV
Positive Hysteresis 2 CP0HYP1–0 = 01 357 mV
Positive Hysteresis 3 CP0HYP1–0 = 10 710 15 mV
Positive Hysteresis 4 CP0HYP1–0 = 11 15 20 25 mV
Negative Hysteresis 1 CP0HYN1–0 = 00 — 0 1 mV
Negative Hysteresis 2 CP0HYN1–0 = 01 357 mV
Negative Hysteresis 3 CP0HYN1–0 = 10 710 15 mV
Negative Hysteresis 4 CP0HYN1–0 = 11 15 20 25 mV
Inverting or Non-Inverting
Input Voltage Range –0.25 — VDD +
0.25 V
Input Capacitance — 7 — pF
Input Bias Current –5 0.001 +5 nA
Input Offset Voltage –5 +5 mV
Power Supply
Power Supply Rejection 0.1 1mV/V
Power-up Time 10 µs
Supply Current at DC
Mode 0 7.6 µA
Mode 1 3.2 µA
Mode 2 1.3 µA
Mode 3 0.4 µA
*Note: Vcm is the common-mode voltage on CP0+ and CP0–.
, . SILIEUN LABS
C8051F300/1/2/3/4/5
56 Rev. 2.9
NOTES:
lilil , . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 57
8. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
three 16-bit counter/timers (see description in Section 15), an enhanced full-duplex UART (see description
in Section 14), 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space (Sec-
tion 8.2.6), and one byte-wide I/O Port (see description in Section 12). The CIP-51 also includes on-chip
debug hardware (see description in Section 17), and interfaces directly with the analog and digital subsys-
tems providing a complete data acquisition or control-system solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 8.1 for a block diagram).
The CIP-51 includes the following features:
Figure 8.1. CIP-51 Block Diagram
- Fully Compatible with MCS-51 Instruction Set - Extended Interrupt Handler
- 25 MIPS Peak Throughput with 25 MHz Clock - Reset Input
- 0 to 25 MHz Clock Frequency - Power Management Modes
- 256 Bytes of Internal RAM - On-chip Debug Logic
- Byte-Wide I/O Port - Program and Data Memory Security
DATA BUS
TMP1 TMP2
PRGM. ADDRESS REG.
PC INCREMENTER
ALU
PSW
DATA BUS
DATA BUS
MEMORY
INTERFACE
MEM_ADDRESS
D8
PIPELINE
BUFFER
DATA POINTER
INTERRUPT
INTERFACE
SYSTEM_IRQs
EMULATION_IRQ
MEM_CONTROL
CONTROL
LOGIC
A16
PROGRAM COUNTER (PC)
STOP
CLOCK
RESET
IDLE POWER CONTROL
REGISTER
DATA BUS
SFR
BUS
INTERFACE
SFR_ADDRESS
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
D8
D8
B REGISTER
D8
D8
ACCUMULATOR
D8
D8
D8
D8
D8
D8
D8
D8
MEM_WRITE_DATA
MEM_READ_DATA
D8
SRAM
ADDRESS
REGISTER
SRAM
(256 X 8)
D8
STACK POINTER
D8
, . SILIEUN LABS
C8051F300/1/2/3/4/5
58 Rev. 2.9
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execu-
tion time.
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2). Note that the re-program-
mable Flash can also be read and changed a single byte at a time by the application software using the
MOVC and MOVX instructions. This feature allows program memory to be used for non-volatile data stor-
age as well as updating program code under software control.
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and mem-
ory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
other on-chip resources. C2 details can be found in Section “17. C2 Interface” on page 173.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro-
vides an integrated development environment (IDE) including editor, macro assembler, debugger and pro-
grammer. The IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast
and efficient in-system device programming and debugging. Third party macro assemblers and C compil-
ers are also available.
8.1. Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc-
tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan-
dard 8051.
8.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 8.1 is the
Clocks to Execute 1 2 2/3 33/4 44/5 5 8
Number of Instructions 26 50 514 73121
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 59
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
8.1.2. MOVX Instruction and Program Memory
The MOVX instruction is typically used to access external data memory (Note: the C8051F300/1/2/3/4/5
does not support external data or program memory). In the CIP-51, the MOVX instruction accesses the on-
chip program memory space implemented as re-programmable Flash memory. This feature provides a
mechanism for the CIP-51 to update program code and use the program memory space for non-volatile
data storage. Refer to Section “10. Flash Memory” on page 89 for further details.
Table 8.1. CIP-51 Instruction Set Summary
Mnemonic Description Bytes Clock
Cycles
Arithmetic Operations
ADD A, Rn Add register to A 1 1
ADD A, direct Add direct byte to A 2 2
ADD A, @Ri Add indirect RAM to A 1 2
ADD A, #data Add immediate to A 2 2
ADDC A, Rn Add register to A with carry 1 1
ADDC A, direct Add direct byte to A with carry 2 2
ADDC A, @Ri Add indirect RAM to A with carry 1 2
ADDC A, #data Add immediate to A with carry 2 2
SUBB A, Rn Subtract register from A with borrow 1 1
SUBB A, direct Subtract direct byte from A with borrow 2 2
SUBB A, @Ri Subtract indirect RAM from A with borrow 1 2
SUBB A, #data Subtract immediate from A with borrow 2 2
INC A Increment A 1 1
INC Rn Increment register 1 1
INC direct Increment direct byte 2 2
INC @Ri Increment indirect RAM 1 2
DEC A Decrement A 1 1
DEC Rn Decrement register 1 1
DEC direct Decrement direct byte 2 2
DEC @Ri Decrement indirect RAM 1 2
INC DPTR Increment Data Pointer 1 1
MUL AB Multiply A and B 1 4
DIV AB Divide A by B 1 8
DA A Decimal adjust A 1 1
Logical Operations
ANL A, Rn AND Register to A 1 1
ANL A, direct AND direct byte to A 2 2
ANL A, @Ri AND indirect RAM to A 1 2
ANL A, #data AND immediate to A 2 2
, ‘ SILIEIJN LABS
C8051F300/1/2/3/4/5
60 Rev. 2.9
ANL direct, A AND A to direct byte 2 2
ANL direct, #data AND immediate to direct byte 3 3
ORL A, Rn OR Register to A 1 1
ORL A, direct OR direct byte to A 2 2
ORL A, @Ri OR indirect RAM to A 1 2
ORL A, #data OR immediate to A 2 2
ORL direct, A OR A to direct byte 2 2
ORL direct, #data OR immediate to direct byte 3 3
XRL A, Rn Exclusive-OR Register to A 1 1
XRL A, direct Exclusive-OR direct byte to A 2 2
XRL A, @Ri Exclusive-OR indirect RAM to A 1 2
XRL A, #data Exclusive-OR immediate to A 2 2
XRL direct, A Exclusive-OR A to direct byte 2 2
XRL direct, #data Exclusive-OR immediate to direct byte 3 3
CLR A Clear A 1 1
CPL A Complement A 1 1
RL A Rotate A left 1 1
RLC A Rotate A left through Carry 1 1
RR A Rotate A right 1 1
RRC A Rotate A right through Carry 1 1
SWAP A Swap nibbles of A 1 1
Data Transfer
MOV A, Rn Move Register to A 1 1
MOV A, direct Move direct byte to A 2 2
MOV A, @Ri Move indirect RAM to A 1 2
MOV A, #data Move immediate to A 2 2
MOV Rn, A Move A to Register 1 1
MOV Rn, direct Move direct byte to Register 2 2
MOV Rn, #data Move immediate to Register 2 2
MOV direct, A Move A to direct byte 2 2
MOV direct, Rn Move Register to direct byte 2 2
MOV direct, direct Move direct byte to direct byte 3 3
MOV direct, @Ri Move indirect RAM to direct byte 2 2
MOV direct, #data Move immediate to direct byte 3 3
MOV @Ri, A Move A to indirect RAM 1 2
MOV @Ri, direct Move direct byte to indirect RAM 2 2
MOV @Ri, #data Move immediate to indirect RAM 2 2
MOV DPTR, #data16 Load DPTR with 16-bit constant 3 3
MOVC A, @A+DPTR Move code byte relative DPTR to A 1 3
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 61
MOVC A, @A+PC Move code byte relative PC to A 1 3
MOVX A, @Ri Move external data (8-bit address) to A 1 3
MOVX @Ri, A Move A to external data (8-bit address) 1 3
MOVX A, @DPTR Move external data (16-bit address) to A 1 3
MOVX @DPTR, A Move A to external data (16-bit address) 1 3
PUSH direct Push direct byte onto stack 2 2
POP direct Pop direct byte from stack 2 2
XCH A, Rn Exchange Register with A 1 1
XCH A, direct Exchange direct byte with A 2 2
XCH A, @Ri Exchange indirect RAM with A 1 2
XCHD A, @Ri Exchange low nibble of indirect RAM with A 1 2
Boolean Manipulation
CLR C Clear Carry 1 1
CLR bit Clear direct bit 2 2
SETB C Set Carry 1 1
SETB bit Set direct bit 2 2
CPL C Complement Carry 1 1
CPL bit Complement direct bit 2 2
ANL C, bit AND direct bit to Carry 2 2
ANL C, /bit AND complement of direct bit to Carry 2 2
ORL C, bit OR direct bit to carry 2 2
ORL C, /bit OR complement of direct bit to Carry 2 2
MOV C, bit Move direct bit to Carry 2 2
MOV bit, C Move Carry to direct bit 2 2
JC rel Jump if Carry is set 22/3
JNC rel Jump if Carry is not set 22/3
JB bit, rel Jump if direct bit is set 33/4
JNB bit, rel Jump if direct bit is not set 33/4
JBC bit, rel Jump if direct bit is set and clear bit 33/4
Program Branching
ACALL addr11 Absolute subroutine call 2 3
LCALL addr16 Long subroutine call 3 4
RET Return from subroutine 1 5
RETI Return from interrupt 1 5
AJMP addr11 Absolute jump 2 3
LJMP addr16 Long jump 3 4
SJMP rel Short jump (relative address) 2 3
JMP @A+DPTR Jump indirect relative to DPTR 1 3
JZ rel Jump if A equals zero 22/3
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
, ‘ SILIEIJN LABS
C8051F300/1/2/3/4/5
62 Rev. 2.9
JNZ rel Jump if A does not equal zero 22/3
CJNE A, direct, rel Compare direct byte to A and jump if not equal 33/4
CJNE A, #data, rel Compare immediate to A and jump if not equal 33/4
CJNE Rn, #data, rel Compare immediate to Register and jump if not
equal 33/4
CJNE @Ri, #data, rel Compare immediate to indirect and jump if not
equal 34/5
DJNZ Rn, rel Decrement Register and jump if not zero 22/3
DJNZ direct, rel Decrement direct byte and jump if not zero 33/4
NOP No operation 1 1
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
Notes on Registers, Operands and Addressing Modes:
Rn - Register R0-R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through R0 or R1.
rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00-
0x7F) or an SFR (0x80-0xFF).
#data - 8-bit constant
#data16 - 16-bit constant
bit - Direct-accessed bit in Data RAM or SFR
addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same
2K-byte page of program memory as the first byte of the following instruction.
addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within
the 8K-byte program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 63
8.2. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The CIP-51 memory organization is
shown in Figure 8.2 and Figure 8.3.
8.2.1. Program Memory
The CIP-51 core has a 64k-byte program memory space. The C8051F300/1/2/3 implements 8192 bytes of
this program memory space as in-system, reprogrammable Flash memory, organized in a contiguous
block from addresses 0x0000 to 0x1FFF. Note: 512 bytes (0x1E00 - 0x1FFF) of this memory are reserved
for factory use and are not available for user program storage. The C8051F304 implements 4096 bytes of
reprogrammable Flash program memory space; the C8051F305 implements 2048 bytes of reprogramma-
ble Flash program memory space. Figure 8.2 shows the program memory maps for C8051F300/1/2/3/4/5
devices.
Figure 8.2. Program Memory Maps
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature pro-
vides a mechanism for the CIP-51 to update program code and use the program memory space for non-
volatile data storage. Refer to Section “10. Flash Memory” on page 89 for further details.
FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
RESERVED
0x1000
0x0FFF
C8051F304
(4k FLASH)
C8051F300/1/2/3
(8k FLASH)
FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
RESERVED
0x1E00
0x1DFF
FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
RESERVED
0x0800
0x07FF
C8051F305
(2k FLASH)
, . SILIEUN LABS
C8051F300/1/2/3/4/5
64 Rev. 2.9
8.2.2. Data Memory
The CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through
0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad mem-
ory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Loca-
tions 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting
of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as
bytes or as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 8.3 illustrates the data memory organization of the CIP-51.
Figure 8.3. Data Memory Map
8.2.3. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen-
eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 8.4). This allows
fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes
use registers R0 and R1 as index registers.
(Direct and Indirect
Addressing)
0x00
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
0x80
0xFF Special Function
Register's
(Direct Addressing Only)
General Purpose
Registers
0x1F
0x20
0x2F Bit Addressable
Lower 128 RAM
(Direct and Indirect
Addressing)
0x30
INTERNAL DATA ADDRESS SPACE
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 65
8.2.4. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destina-
tion).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
8.2.5. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is desig-
nated using the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value
pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to
location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the
first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be
initialized to a location in the data memory not being used for data storage. The stack depth can extend up
to 256 bytes.
8.2.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the subsystems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set. Table 8.2 lists the SFRs imple-
mented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the datasheet, as indicated in Table 8.3,
for a detailed description of each register.
, ‘ SILIEIJN LABS
C8051F300/1/2/3/4/5
66 Rev. 2.9
Table 8.2. Special Function Register (SFR) Memory Map
F8 CPT0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0
F0 BP0MDIN EIP1
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 RSTSRC
E0 ACC XBR0 XBR1 XBR2 IT01CF EIE1
D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2
D0 PSW REF0CN
C8 TMR2CN TMR2RLL TMR2RLH TMR2L TMR2H
C0 SMB0CN SMB0CF SMB0DAT ADC0GT ADC0LT
B8 IP AMX0SL ADC0CF ADC0
B0 OSCXCN OSCICN OSCICL FLSCL FLKEY
A8 IE
A0 P0MDOUT
98 SCON0 SBUF0 CPT0MD CPT0MX
90
88 TCON TMOD TL0 TL1 TH0 TH1 CKCON PSCTL
80 P0 SP DPL DPH PCON
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
(bit addressable)
Table 8.3. Special Function Registers*
Register Address Description Page
No.
ACC 0xE0 Accumulator 71
ADC0CF 0xBC ADC0 Configuration 43
ADC0CN 0xE8 ADC0 Control 44
ADC0GT 0xC4 ADC0 Greater-Than Compare Word 46
ADC0LT 0xC6 ADC0 Less-Than Compare Word 46
ADC0 0xBE ADC0 Data Word 43
AMX0SL 0xBB ADC0 Multiplexer Channel Select 42
B0xF0 B Register 71
CKCON 0x8E Clock Control 149
CPT0CN 0xF8 Comparator0 Control 53
CPT0MD 0x9D Comparator0 Mode Selection 54
CPT0MX 0x9F Comparator0 MUX Selection 54
DPH 0x83 Data Pointer High 69
DPL 0x82 Data Pointer Low 68
EIE1 0xE6 Extended Interrupt Enable 1 77
EIP1 0xF6 External Interrupt Priority 1 78
FLKEY 0xB7 Flash Lock and Key 93
*Note: SFRs are listed in alphabetical order. All undefined SFR locations are reserved
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 67
FLSCL 0xB6 Flash Scale 93
IE 0xA8 Interrupt Enable 75
IP 0xB8 Interrupt Priority 76
IT01CF 0xE4 INT0/INT1 Configuration Register 79
OSCICL 0xB3 Internal Oscillator Calibration 98
OSCICN 0xB2 Internal Oscillator Control 98
OSCXCN 0xB1 External Oscillator Control 100
P0 0x80 Port 0 Latch 109
P0MDIN 0xF1 Port 0 Input Mode Configuration 109
P0MDOUT 0xA4 Port 0 Output Mode Configuration 110
PCA0CN 0xD8 PCA Control 167
PCA0MD 0xD9 PCA Mode 168
PCA0CPH0 0xFC PCA Capture 0 High 171
PCA0CPH1 0xEA PCA Capture 1 High 171
PCA0CPH2 0xEC PCA Capture 2 High 171
PCA0CPL0 0xFB PCA Capture 0 Low 171
PCA0CPL1 0xE9 PCA Capture 1 Low 171
PCA0CPL2 0xEB PCA Capture 2 Low 171
PCA0CPM0 0xDA PCA Module 0 Mode Register 169
PCA0CPM1 0xDB PCA Module 1 Mode Register 169
PCA0CPM2 0xDC PCA Module 2 Mode Register 169
PCA0H 0xFA PCA Counter High 170
PCA0L 0xF9 PCA Counter Low 170
PCON 0x87 Power Control 81
PSCTL 0x8F Program Store R/W Control 92
PSW 0xD0 Program Status Word 70
REF0CN 0xD1 Voltage Reference Control 49
RSTSRC 0xEF Reset Source Configuration/Status 87
SBUF0 0x99 UART 0 Data Buffer 137
SCON0 0x98 UART 0 Control 136
SMB0CF 0xC1 SMBus Configuration 118
SMB0CN 0xC0 SMBus Control 120
SMB0DAT 0xC2 SMBus Data 122
SP 0x81 Stack Pointer 69
TMR2CN 0xC8 Timer/Counter 2 Control 154
TCON 0x88 Timer/Counter Control 147
TH0 0x8C Timer/Counter 0 High 150
Table 8.3. Special Function Registers* (Continued)
Register Address Description Page
No.
*Note: SFRs are listed in alphabetical order. All undefined SFR locations are reserved
, . SILIEUN LABS
C8051F300/1/2/3/4/5
68 Rev. 2.9
8.2.7. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the datasheet associated with their corresponding sys-
tem function.
SFR Definition 8.1. DPL: Data Pointer Low Byte
TH1 0x8D Timer/Counter 1 High 150
TL0 0x8A Timer/Counter 0 Low 150
TL1 0x8B Timer/Counter 1 Low 150
TMOD 0x89 Timer/Counter Mode 148
TMR2RLH 0xCB Timer/Counter 2 Reload High 154
TMR2RLL 0xCA Timer/Counter 2 Reload Low 154
TMR2H 0xCD Timer/Counter 2 High 154
TMR2L 0xCC Timer/Counter 2 Low 154
XBR0 0xE1 Port I/O Crossbar Control 0 107
XBR1 0xE2 Port I/O Crossbar Control 1 107
XBR2 0xE3 Port I/O Crossbar Control 2 108
0x97, 0xAE, 0xAF, 0xB4,
0xB6, 0xBF, 0xCE, 0xD2,
0xD3, 0xD4, 0xD5, 0xD6,
0xD7, 0xDD, 0xDE, 0xDF,
0xF5
Reserved
Table 8.3. Special Function Registers* (Continued)
Register Address Description Page
No.
*Note: SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Bits7–0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed Flash memory.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x82
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 69
SFR Definition 8.2. DPH: Data Pointer High Byte
SFR Definition 8.3. SP: Stack Pointer
Bits7–0: DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed Flash memory.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x83
Bits7–0: SP: Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented
before every PUSH operation. The SP register defaults to 0x07 after reset.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x81
, . SILIEUN LABS
C8051F300/1/2/3/4/5
70 Rev. 2.9
SFR Definition 8.4. PSW: Program Status Word
Bit7: CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtraction). It is cleared to logic 0 by all other arithmetic operations.
Bit6: AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic opera-
tions.
Bit5: F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
Bits4–3: RS1-RS0: Register Bank Select.
These bits select which register bank is used during register accesses.
Bit2: OV: Overflow Flag.
This bit is set to 1 under the following circumstances:
An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
A MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
Bit1: F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
Bit0: PARITY: Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the
sum is even.
R/W R/W R/W R/W R/W R/W R/W R Reset Value
CY AC F0 RS1 RS0 OV F1 PARITY 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable) 0xD0
RS1 RS0 Register Bank Address
0 0 0 0x00–0x07
0 1 1 0x08–0x0F
1 0 2 0x10–0x17
1 1 3 0x18–0x1F
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 71
SFR Definition 8.5. ACC: Accumulator
SFR Definition 8.6. B: B Register
Bits7–0: ACC: Accumulator.
This register is the accumulator for arithmetic operations.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable) 0xE0
Bits7–0: B: B Register.
This register serves as a second accumulator for certain arithmetic operations.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable) 0xF0
, . SILIEUN LABS
C8051F300/1/2/3/4/5
72 Rev. 2.9
8.3. Interrupt Handler
The CIP-51 includes an extended interrupt system supporting a total of 12 interrupt sources with two prior-
ity levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies
according to the specific version of the device. Each interrupt source has one or more associated interrupt-
pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition,
the associated interrupt-pending flag is set to logic 1.
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a prede-
termined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regard-
less of the interrupt's enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE-EIE1). However, interrupts must first be globally enabled by setting the EA bit
(IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables
all interrupt sources regardless of the individual interrupt-enable settings.
Note: Any instruction that clears the EA bit should be immediately followed by an instruction that
has two or more opcode bytes. For example:
// in 'C':
EA = 0; // clear EA bit
EA = 0; // ... followed by another 2-byte opcode
; in assembly:
CLR EA ; clear EA bit
CLR EA ; ... followed by another 2-byte opcode
If an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction which clears
the EA bit), and the instruction is followed by a single-cycle instruction, the interrupt may be taken. How-
ever, a read of the EA bit will return a '0' inside the interrupt service routine. When the "CLR EA" opcode is
followed by a multi-cycle instruction, the interrupt will not be taken.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will reenter the ISR after
the completion of the next instruction.
8.3.1. MCU Interrupt Sources and Vectors
The MCUs support 12 interrupt sources. Software can simulate an interrupt by setting any interrupt-pend-
ing flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU
will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associ-
ated vector addresses, priority order and control bits are summarized in Table 8.4 on page 74. Refer to the
datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 73
8.3.2. External Interrupts
The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensi-
tive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “15.1. Timer 0 and Timer 1” on page 143) select level
or edge sensitive. The table below lists the possible configurations.
/INT0 and /INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 8.11).
Note that /INT0 and /INT0 Port pin assignments are independent of any Crossbar assignments. /INT0 and
/INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin
via the Crossbar. To assign a Port pin only to /INT0 and/or /INT1, configure the Crossbar to skip the
selected pin(s). This is accomplished by setting the associated bit in register XBR0 (see Section
“12.1. Priority Crossbar Decoder” on page 104 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the /INT0 and /INT1 external
interrupts, respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corre-
sponding interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR.
When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as
defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inac-
tive. The external interrupt source must hold the input active until the interrupt request is recognized. It
must then deactivate the interrupt request before execution of the ISR completes or another interrupt
request will be generated.
8.3.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP1) used to configure
its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in Table 8.4.
8.3.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
IT0 IN0PL /INT0 Interrupt IT1 IN1PL /INT1 Interrupt
1 0 Active low, edge sensitive 10
Active low, edge sensitive
1 1 Active high, edge sensitive 11
Active high, edge sensitive
0 0 Active low, level sensitive 00
Active low, level sensitive
0 1 Active high, level sensitive 01
Active high, level sensitive
, . SILIEUN LABS
C8051F300/1/2/3/4/5
74 Rev. 2.9
Table 8.4. Interrupt Summary
Interrupt Source Interrupt
Vector Priority
Order Pending Flag
Bit addressable?
Cleared by HW?
Enable
Flag Priority
Control
Reset 0x0000 Top None N/A N/A Always
Enabled Always
Highest
External Interrupt 0 (/INT0) 0x0003 0IE0 (TCON.1) YY
EX0 (IE.0) PX0 (IP.0)
Timer 0 Overflow 0x000B 1TF0 (TCON.5) YY
ET0 (IE.1) PT0 (IP.1)
External Interrupt 1 (/INT1) 0x0013 2IE1 (TCON.3) YY
EX1 (IE.2) PX1 (IP.2)
Timer 1 Overflow 0x001B 3TF1 (TCON.7) YY
ET1 (IE.3) PT1 (IP.3)
UART0 0x0023 4RI0 (SCON0.0)
TI0 (SCON0.1)
YN
ES0 (IE.4) PS0 (IP.4)
Timer 2 Overflow 0x002B 5TF2H
(TMR2CN.7)
TF2L
(TMR2CN.6)
YN
ET2 (IE.5) PT2 (IP.5)
SMBus Interface 0x0033 6SI (SMB0CN.0) YN
ESMB0
(EIE1.0) PSMB0
(EIP1.0)
ADC0 Window Compare 0x003B 7AD0WINT
(ADC0CN.3)
YN
EWADC0
(EIE1.1) PWADC0
(EIP1.1)
ADC0 Conversion Com-
plete 0x0043 8AD0INT
(ADC0CN.5)
YN
EADC0C
(EIE1.2) PADC0C
(EIP1.2)
Programmable Counter
Array 0x004B 9CF (PCA0CN.7)
CCFn
(PCA0CN.n)
YN
EPCA0
(EIE1.3) PPCA0
(EIP1.3)
Comparator0 Falling Edge 0x0053 10 CP0FIF
(CPT0CN.4)
NN
ECP0F
(EIE1.4) PCP0F
(EIP1.4)
Comparator0 Rising Edge 0x005B 11 CP0RIF
(CPT0CN.5)
NN
ECP0R
(EIE1.5) PCP0R
(EIP1.5)
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 75
8.3.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the
datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
SFR Definition 8.7. IE: Interrupt Enable
Bit7: EA: Enable All Interrupts.
This bit globally enables/disables all interrupts. It overrides the individual interrupt mask set-
tings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
Bit6: IEGF0: General Purpose Flag 0.
This is a general purpose flag for use under software control.
Bit5: ET2: Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
Bit4: ES0: Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
Bit3: ET1: Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
Bit2: EX1: Enable External Interrupt 1.
This bit sets the masking of external interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 input.
Bit1: ET0: Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
Bit0: EX0: Enable External Interrupt 0.
This bit sets the masking of external interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the /INT0 input.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
EA IEGF0 ET2 ES0 ET1 EX1 ET0 EX0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable) 0xA8
, . SILIEUN LABS
C8051F300/1/2/3/4/5
76 Rev. 2.9
SFR Definition 8.8. IP: Interrupt Priority
Bits7–6: UNUSED. Read = 11b, Write = don't care.
Bit5: PT2: Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupts set to low priority level.
1: Timer 2 interrupts set to high priority level.
Bit4: PS0: UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupts set to low priority level.
1: UART0 interrupts set to high priority level.
Bit3: PT1: Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupts set to low priority level.
1: Timer 1 interrupts set to high priority level.
Bit2: PX1: External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
Bit1: PT0: Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupts set to low priority level.
1: Timer 0 interrupts set to high priority level.
Bit0: PX0: External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
PT2 PS0 PT1 PX1 PT0 PX0 11000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable) 0xB8
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 77
SFR Definition 8.9. EIE1: Extended Interrupt Enable 1
Bits7–6: UNUSED. Read = 00b. Write = don’t care.
Bit5: ECP0R: Enable Comparator0 (CP0) Rising Edge Interrupt.
This bit sets the masking of the CP0 Rising Edge interrupt.
0: Disable CP0 Rising Edge interrupt.
1: Enable interrupt requests generated by the CP0RIF flag.
Bit4: ECP0F: Enable Comparator0 (CP0) Falling Edge Interrupt.
This bit sets the masking of the CP0 Falling Edge interrupt.
0: Disable CP0 Falling Edge interrupt.
1: Enable interrupt requests generated by the CP0FIF flag.
Bit3: EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
Bit2: EADC0C: Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
Bit1: EWADC0: Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag.
Bit0: ESMB0: Enable SMBus Interrupt.
This bit sets the masking of the SMBus interrupt.
0: Disable all SMBus interrupts.
1: Enable interrupt requests generated by the SI flag.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
ECP0R ECP0F EPCA0 EADC0C EWADC0 ESMB0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xE6
, . SILIEUN LABS
C8051F300/1/2/3/4/5
78 Rev. 2.9
SFR Definition 8.10. EIP1: Extended Interrupt Priority 1
Bits7–6: UNUSED. Read = 11b. Write = don’t care.
Bit5: PCP0R: Comparator0 (CP0) Rising Interrupt Priority Control.
This bit sets the priority of the CP0 rising-edge interrupt.
0: CP0 rising interrupt set to low priority level.
1: CP0 rising interrupt set to high priority level.
Bit4: PCP0F: Comparator0 (CP0) Falling Interrupt Priority Control.
This bit sets the priority of the CP0 falling-edge interrupt.
0: CP0 falling interrupt set to low priority level.
1: CP0 falling interrupt set to high priority level.
Bit3: PPCA0: Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
Bit2: PADC0C ADC0 Conversion Complete Interrupt Priority Control
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
Bit1: PWADC0: ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
Bit0: PSMB0: SMBus Interrupt Priority Control.
This bit sets the priority of the SMBus interrupt.
0: SMBus interrupt set to low priority level.
1: SMBus interrupt set to high priority level.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
PCP0R PCP0F PPCA0 PADC0C PWADC0 PSMB0 11000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xF6
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 79
SFR Definition 8.11. IT01CF: INT0/INT1 Configuration
Bit7: IN1PL: /INT1 Polarity
0: /INT1 input is active low.
1: /INT1 input is active high.
Bits6–4: IN1SL2–0: /INT1 Port Pin Selection Bits
These bits select which Port pin is assigned to /INT1. Note that this pin assignment is inde-
pendent of the Crossbar; /INT1 will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by
setting to ‘1’ the corresponding bit in register XBR0).
Bit3: IN0PL: /INT0 Polarity
0: /INT0 interrupt is active low.
1: /INT0 interrupt is active high.
Bits2–0: INT0SL2–0: /INT0 Port Pin Selection Bits
These bits select which Port pin is assigned to /INT0. Note that this pin assignment is inde-
pendent of the Crossbar. /INT0 will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by
setting to ‘1’ the corresponding bit in register XBR0).
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
IN1PL IN1SL2 IN1SL1 IN1SL0 IN0PL IN0SL2 IN0SL1 IN0SL0 00000001
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xE4
Note: Refer to SFR Definition 15.1 for INT0/1 edge- or level-sensitive interrupt selection.
IN1SL2–0 /INT1 Port Pin
000 P0.0
001 P0.1
010 P0.2
011 P0.3
100 P0.4
101 P0.5
110 P0.6
111 P0.7
IN0SL2–0 /INT0 Port Pin
000 P0.0
001 P0.1
010 P0.2
011 P0.3
100 P0.4
101 P0.5
110 P0.6
111 P0.7
, . SILIEUN LABS
C8051F300/1/2/3/4/5
80 Rev. 2.9
8.4. Power Management Modes
The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode
halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all inter-
rupts and timers (except the Missing Clock Detector) are inactive, and the system clock is stopped (analog
peripherals remain in their selected states). Since clocks are running in Idle mode, power consumption is
dependent upon the system clock frequency and the number of peripherals left in active mode before
entering Idle. Stop mode consumes the least power. SFR Definition 8.12 describes the Power Control Reg-
ister (PCON) used to control the CIP-51's power management modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power
management of the entire MCU is better accomplished by enabling/disabling individual peripherals as
needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital
peripherals, such as timers or serial buses, draw little power when they are not in use. Turning off the oscil-
lators lowers power consumption considerably; however a reset is required to restart the MCU.
8.4.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes execution. All internal registers and memory maintain their
original data. All analog and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby termi-
nate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This pro-
vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi-
nitely, waiting for an external stimulus to wake up the system. Refer to Section “16.3. Watchdog Timer
Mode” on page 164 for more information on the use and configuration of the WDT.
Note: Any instruction that sets the IDLE bit should be immediately followed by an instruction that
has 2 or more opcode bytes. For example:
// in 'C':
PCON |= 0x01; // set IDLE bit
PCON = PCON; // ... followed by a 3-cycle dummy instruction
; in assembly:
ORL PCON, #01h ; set IDLE bit
MOV PCON, PCON ; ... followed by a 3-cycle dummy instruction
If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs during
the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from IDLE mode when
a future interrupt occurs.
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 81
8.4.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc-
tion that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital periph-
erals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop
mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout of 100 µsec.
SFR Definition 8.12. PCON: Power Control
Bits7–2: GF5–GF0: General Purpose Flags 5-0.
These are general purpose flags for use under software control.
Bit1: STOP: Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: CPU goes into Stop mode (turns off internal oscillator).
Bit0: IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode (shuts off clock to CPU, but clock to Timers, Interrupts, Serial
Ports, and Analog Peripherals are still active).
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
GF5 GF4 GF3 GF2 GF1 GF0 STOP IDLE 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x87
, . SILIEUN LABS
C8051F300/1/2/3/4/5
82 Rev. 2.9
NOTES:
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 83
9. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled
during and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. Refer to Section “11. Oscillators” on page 97 for information on selecting and configuring
the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock
source (Section “16.3. Watchdog Timer Mode” on page 164 details the use of the Watchdog Timer).
Once the system clock source is stable, program execution begins at location 0x0000.
Figure 9.1. Reset Sources
PCA
WDT
Missing
Clock
Detector
(one-
shot) (Software Reset)
System Reset
Reset
Funnel
P0.x
P0.y
EN
SWRSF
Internal
Oscillator System
Clock
CIP-51
Microcontroller
Core
Extended Interrupt
Handler
Clock Select
EN
WDT
Enable
MCD
Enable
XTAL1
XTAL2
External
Oscillator
Drive
Illegal
FLASH
Operation
+
-
Comparator 0
C0RSEF
/RST
(wired-OR)
Power On
Reset
+
-
VDD
Supply
Monitor
Enable
'0'
, . SILIEUN LABS
C8051F300/1/2/3/4/5
84 Rev. 2.9
9.1. Power-On Reset
During powerup, the device is held in a reset state and the RST pin is driven low until VDD settles above
VRST. An additional delay occurs before the device is released from reset; the delay decreases as the VDD
ramp time increases (VDD ramp time is defined as how fast VDD ramps from 0 V to VRST). For valid ramp
times (less than 1 ms), the power-on reset delay (TPORDelay) is typically less than 0.3 ms.
Note: The maximum VDD ramp time is 1 ms; slower ramp times may cause the device to be
released from reset before VDD reaches the VRST level.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a powerup was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The VDD monitor is disabled following a
power-on reset.
Figure 9.2. Power-On and VDD Monitor Reset Timing
9.2. Power-Fail Reset/VDD Monitor
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 9.2). When VDD returns
to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data
memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below
the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The VDD
monitor is disabled after power-on resets; however its defined state (enabled/disabled) is not altered by
any other reset source. For example, if the VDD monitor is enabled and a software reset is performed, the
VDD monitor will still be enabled after the reset. The VDD monitor is enabled by writing a ‘1’ to the PORSF
Power-On
Reset
VDD
Monitor
Reset
/RST
t
volts
1.0
2.0
Logic HIGH
Logic LOW T
PORDelay
VDD
2.70
2.55
V
RST
VDD
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 85
bit in register RSTSRC. See Figure 9.2 for VDD monitor timing; note that the reset delay is not incurred
after a VDD monitor reset. See Table 9.2 for electrical characteristics of the VDD monitor.
Important Note: Enabling the VDD monitor will immediately generate a system reset. The device will then
return from the reset state with the VDD monitor enabled. Writing a logic ‘1’ to the PORSF flag when the
VDD monitor is enabled does not cause a system reset.
9.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 9.2 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
9.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise,
this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables
it. The state of the RST pin is unaffected by this reset.
9.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5). Com-
parator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter
on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting
input voltage (on CP0+) is less than the inverting input voltage (on CP0–), the device is put into the reset
state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read ‘1’ signifying Comparator0 as the
reset source; otherwise, this bit reads ‘0’. The state of the RST pin is unaffected by this reset.
9.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “16.3. Watchdog Timer Mode” on
page 164; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to ‘1’. The state of the RST pin is unaffected by this reset.
, . SILIEUN LABS
C8051F300/1/2/3/4/5
86 Rev. 2.9
9.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
A Flash write or erase is attempted above user code space. This occurs when PSWE is set to ‘1’ and a
MOVX operation is attempted above the user code space address limit.
A Flash read is attempted above user code space. This occurs when a MOVC operation is attempted
above the user code space address limit.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the user code space address limit.
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
9.8. Software Reset
Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
Table 9.1. User Code Space Address Limits
Device User Code Space Address Limit
C8051F300/1/2/3 0x1DFF
C8051F304 0x0FFF
C8051F305 0x07FF
Table 9.2. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
RST Output Low Voltage IOL = 8.5 mA, VDD = 2.7 V to
3.6 V 0.6 V
RST Input High Voltage 0.7 x VDD — — V
RST Input Low Voltage 0.3 x VDD
RST Input Leakage Current RST = 0.0 V 25 40 µA
VDD Monitor Threshold (VRST)2.40 2.55 2.70 V
Missing Clock Detector Timeout Time from last system clock ris-
ing edge to reset initiation 100 220 500 µs
Reset Time Delay Delay between release of any
reset source and code execution
at location 0x0000
5.0 — — µs
Minimum RST Low Time to
Generate a System Reset 15 — — µs
VDD Ramp Time VDD = 0 to VRST — — 1 ms
, . SILIEUN LABS
C8051F300/1/2/3/4/5
Rev. 2.9 87
SFR Definition 9.1. RSTSRC: Reset Source
(Note: Do not use read-modify-write operations (ORL, ANL) on this register)
Bit7: UNUSED. Read = 0. Write = don’t care.
Bit6: FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a Flash read/write/erase error.
Bit5: C0RSEF: Comparator0 Reset Enable and Flag.
Write
0: Comparator0 is not a reset source.
1: Comparator0 is a reset source (active-low).
Read
0: Source of last reset was not Comparator0.
1: Source of last reset was Comparator0.
Bit4: SWRSF: Software Reset Force and Flag.
Write
0: No Effect.
1: Forces a system reset.
Read
0: Source of last reset was not a write to the SWRSF bit.
1: Source of last was a write to the SWRSF bit.
Bit3: WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
Bit2: MCDRSF: Missing Clock Detector Flag.
Write:
0: Missing Clock Detector disabled.
1: Missing Clock Detector enabled; triggers a reset if a missing clock condition is detected.
Read:
0: Source of last reset was not a Missing Clock Detector timeout.
1: Source of last reset was a Missing Clock Detector timeout.
Bit1: PORSF: Power-On Reset Force and Flag.
This bit is set anytime a power-on reset occurs. This may be due to a true power-on reset or
a VDD monitor reset. In either case, data memory should be considered indeterminate fol-
lowing the reset. Writing this bit enables/disables the VDD monitor.
Write:
0: VDD monitor disabled.
1: VDD monitor enabled.
Read:
0: Last reset was not a power-on or VDD monitor reset.
1: Last reset was a power-on or VDD monitor reset; all other reset flags indeterminate.
Bit0: PINRSF: HW Pin Reset Flag.
0: Source of last reset was not RST pin.
1: Source of last reset was RST pin.
R R R/W R/W R R/W R/W R Reset Value
FERROR C0RSEF SWRSF WDTRSF MCDRSF PORSF PINRSF Variable
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xEF
, . SILIEUN LABS
C8051F300/1/2/3/4/5
88 Rev. 2.9
NOTES:
, . SILIEUN LABS
C8051F300/1/2/3/4/5
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10. Flash Memory
On-chip, reprogrammable Flash memory is included for program code and non-volatile data storage. The
Flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by soft-
ware using the MOVX instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic
1. Flash bytes would typically be erased (set to 0xFF) before being reprogrammed. The write and erase
operations are automatically timed by hardware for proper execution; data polling to determine the end of
the write/erase operation is not required. Code execution is stalled during a Flash write/erase operation.
Refer to Table 10.1 for complete Flash memory electrical characteristics.
10.1. Programming The Flash Memory
The simplest means of programming the Flash memory is through the C2 interface using programming
tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initial-
ized device. For details on the C2 commands to program Flash memory, see Section “17. C2 Interface”
on page 173.
To ensure the integrity of Flash contents, it is strongly recommended that the on-chip VDD Monitor
be enabled in any system that includes code that writes and/or erases Flash memory from soft-
ware.
10.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function; Flash reads by user
software are unrestricted. The Flash Lock and Key Register (FLKEY) must be written with the correct key
codes, in sequence, before Flash operations may be performed. The key codes are: 0xA5, 0xF1. The tim-
ing does not matter, but the codes must be written in order. If the key codes are written out of order, or the
wrong codes are written, Flash writes and erases will be disabled until the next system reset. Flash writes
and erases will also be disabled if a Flash write or erase is attempted before the key codes have been writ-
ten properly. The Flash lock resets after each write or erase; the key codes must be written again before a
following Flash operation can be performed. The FLKEY register is detailed in SFR Definition 10.2.
10.1.2. Flash Erase Procedure
The Flash memory can be programmed by software using the MOVX instruction with the address and data
byte to be programmed provided as normal operands. Before writing to Flash memory using MOVX, Flash
write operations must be enabled by: (1) setting the PSWE Program Store Write Enable bit (PSCTL.0) to
logic 1 (this directs the MOVX writes to target Flash memory); and (2) Writing the Flash key codes in
sequence to the Flash Lock register (FLKEY). The PSWE bit remains set until cleared by software.
A write to Flash memory can clear bits but cannot set them; only an erase operation can set bits in Flash.
A byte location to be programmed should be erased before a new value is written. The 8k byte Flash
memory is organized in 512-byte pages. The erase operation applies to an entire page (setting all bytes in
the page to 0xFF). To erase an entire 512-byte page, perform the following steps:
Step 1. Disable interrupts (recommended).
Step 2. Set the Program Store Erase Enable bit (PSEE in the PSCTL register).
Step 3. Set the Program Store Write Enable bit (PSWE in the PSCTL register).
Step 4. Write the first key code to FLKEY: 0xA5.
Step 5. Write the second key code to FLKEY: 0xF1.
Step 6. Using the MOVX instruction, write a data byte to any location within the 512-byte page to
be erased.
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10.1.3. Flash Write Procedure
Flash bytes are programmed by software with the following sequence:
Step 1. Disable interrupts (recommended).
Step 2. Erase the 512-byte Flash page containing the target location, as described in Section
10.1.2.
Step 3. Set the PSWE bit in PSCTL.
Step 4. Clear the PSEE bit in PSCTL.
Step 5. Write the first key code to FLKEY: 0xA5.
Step 6. Write the second key code to FLKEY: 0xF1.
Step 7. Using the MOVX instruction, write a single data byte to the desired location within the 512-
byte sector.
Steps 5–7 must be repeated for each byte to be written. After Flash writes are complete, PSWE should be
cleared so that MOVX instructions do not target program memory. Writing to and erasing the Reserved
area of Flash should be avoided.
10.2. Non-Volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
instruction and read using the MOVC instruction.
10.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft-
ware as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly
set to ‘1’ before software can modify the Flash memory; both PSWE and PSEE must be set to ‘1’ before
software can erase Flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
A security lock byte stored at the last byte of Flash user space protects the Flash program memory from
being read or altered across the C2 interface. See Table 10.2 for the security byte description; see
Figure 10.1 for a program memory map and the security byte locations for each device.
Table 10.1. Flash Electrical Characteristics
Parameter Conditions Min Typ Max Units
Flash Size
C8051F300/1/2/3 8192* bytes
C8051F304 4096 bytes
C8051F305 2048 bytes
Endurance 20k 100k Erase/Write
Erase Cycle Time 25 MHz System Clock 10 15 20 ms
Write Cycle Time 25 MHz System Clock 40 55 70 µs
SYSCLK Frequency (Flash
writes from application code) 100 kHz
*Note: 512 bytes at location 0x1E00 to 0x1FFF are reserved.
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The lock bits can always be read and cleared to logic 0 regardless of the security settings.
Important note: The only means of removing a lock (write or read/write) once set is to erase the
entire program memory space via a C2 Device Erase command.
Figure 10.1. Flash Program Memory Map
The level of Flash security depends on the Flash access method. The three Flash access methods that
can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on
unlocked pages, and user firmware executing on locked pages.
Accessing Flash from the C2 debug interface:
1. Any unlocked page may be read, written, or erased.
2. Locked pages cannot be read, written, or erased.
3. The page containing the Lock Byte may be read, written, or erased if it is unlocked.
4. Reading the contents of the Lock Byte is always permitted only if no pages are locked.
5. Locking additional pages (changing ‘1’s to ‘0’s in the Lock Byte) is not permitted.
6. Unlocking Flash pages (changing ‘0s to ‘1’s in the Lock Byte) requires the C2 Device Erase com-
mand, which erases all Flash pages including the page containing the Lock Byte and the Lock
Byte itself.
7. The Reserved Area cannot be read, written, or erased.
Table 10.2. Security Byte Decoding
Bits Description
7–4 Write Lock: Clearing any of these bits to logic 0 prevents all Flash
memory from being written or page-erased across the C2 interface
3–0 Read/Write Lock: Clearing any of these bits to logic 0 prevents all
Flash memory from being read, written, or page-erased across the
C2 interface.
C8051F300/1/2/3
0x0000
0x1DFF
Lock Byte
Reserved
0x1DFE
FLASH memory
organized in 512-byte
pages
0x1E00
0x0000
0x0FFF
Reserved
0x0FFE
FLASH memory
organized in 512-byte
pages
0x1000
0x0000
0x07FF
Lock Byte
Reserved
0x07FE
FLASH memory
organized in 512-byte
pages
0x0800
Lock Byte
C8051F304
C8051F305
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Accessing Flash from user firmware executing from an unlocked page:
1. Any unlocked page except the page containing the Lock Byte may be read, written, or erased.
2. Locked pages cannot be read, written, or erased. An erase attempt on the page containing the
Lock Byte will result in a Flash Error device reset.
3. The page containing the Lock Byte cannot be erased. It may be read or written only if it is
unlocked. An erase attempt on the page containing the Lock Byte will result in a Flash Error device
reset.
4. Reading the contents of the Lock Byte is always permitted.
5. Locking additional pages (changing ‘1’s to ‘0’s in the Lock Byte) is not permitted.
6. Unlocking Flash pages (changing ‘0’s to ‘1’s in the Lock Byte) is not permitted.
7. The Reserved Area cannot be read, written, or erased. Any attempt to access the reserved area,
or any other locked page, will result in a Flash Error device reset.
Accessing Flash from user firmware executing from a locked page:
1. Any unlocked page except the page containing the Lock Byte may be read, written, or erased.
2. Any locked page except the page containing the Lock Byte may be read, written, or erased. An
erase attempt on the page containing the Lock Byte will result in a Flash Error device reset.
3. The page containing the Lock Byte cannot be erased. It may only be read or written. An erase
attempt on the page containing the Lock Byte will result in a Flash Error device reset.
4. Reading the contents of the Lock Byte is always permitted.
5. Locking additional pages (changing ‘1’s to ‘0’s in the Lock Byte) is not permitted.
6. Unlocking Flash pages (changing ‘0’s to ‘1’s in the Lock Byte) is not permitted.
7. The Reserved Area cannot be read, written, or erased. Any attempt to access the reserved area,
or any other locked page, will result in a Flash Error device reset.
SFR Definition 10.1. PSCTL: Program Store R/W Control
Bits7–2: UNUSED: Read = 000000b, Write = don’t care.
Bit1: PSEE: Program Store Erase Enable
Setting this bit (in combination with PSWE) allows an entire page of Flash program memory
to be erased. If this bit is logic 1 and Flash writes are enabled (PSWE is logic 1), a write to
Flash memory using the MOVX instruction will erase the entire page that contains the loca-
tion addressed by the MOVX instruction. The value of the data byte written does not matter.
0: Flash program memory erasure disabled.
1: Flash program memory erasure enabled.
Bit0: PSWE: Program Store Write Enable
Setting this bit allows writing a byte of data to the Flash program memory using the MOVX
instruction. The Flash location should be erased before writing data.
0: Writes to Flash program memory disabled.
1: Writes to Flash program memory enabled; the MOVX instruction targets Flash memory.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
— — — — — — PSEE PSWE 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x8F
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SFR Definition 10.2. FLKEY: Flash Lock and Key
SFR Definition 10.3. FLSCL: Flash Scale
Bits7–0: FLKEY: Flash Lock and Key Register
Write:
This register must be written to before Flash writes or erases can be performed. Flash
remains locked until this register is written to with the following key codes: 0xA5, 0xF1. The
timing of the writes does not matter, as long as the codes are written in order. The key codes
must be written for each Flash write or erase operation. Flash will be locked until the next
system reset if the wrong codes are written or if a Flash operation is attempted before the
codes have been written correctly.
Read:
When read, bits 1–0 indicate the current Flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writes/erases disabled until the next reset.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xB7
Bits7: FOSE: Flash One-shot Enable
This bit enables the 50 ns Flash read one-shot. When the Flash one-shot disabled, the
Flash sense amps are enabled for a full clock cycle during Flash reads.
0: Flash one-shot disabled.
1: Flash one-shot enabled.
Bits6–0: RESERVED. Read = 0. Must Write 0.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
FOSE Reserved Reserved Reserved Reserved Reserved Reserved Reserved 10000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xB6
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10.4. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash modi-
fying code can result in alteration of Flash memory contents causing a system failure that is only recover