XC4000(E),(X),(XL) Series Datasheet by Xilinx Inc.

View All Related Products | Download PDF Datasheet
XXILINX“
R
DS005 (v2.0) March 1, 2013 - Product Specification 6-73
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Product Obsolete/Under Obsolescence
XC4000XL Electrical Specifications
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device
families. Values are subject to change. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.
Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions.
All specifications subject to change without notice.
XC4000XL D.C. Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Description Units
VCC Supply voltage relative to Ground -0.5 to 4.0 V
VIN Input voltage relative to Ground (Note 1) -0.5 to 5.5 V
VTS Voltage applied to 3-state output (Note 1) -0.5 to 5.5 V
VCCt Longest Supply Voltage Rise Time from 1 V to 3V 50 ms
TSTG Storage temperature (ambient) -65 to +150 °C
TSOL Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 °C
TJJunction Temperature Ceramic packages +150 °C
Plastic packages +125 °C
Note 1: Maximum DC excursion above Vcc or below Ground must be limited to either 0.5 V or 10 mA, whichever is easier to
achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot toVCC +2.0 V, provided this over or
undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
Symbol Description Min Max Units
VCC
Supply voltage relative to Gnd, TJ = 0 °C to +85°CCommercial 3.0 3.6 V
Supply voltage relative to Gnd, TJ = -40°C to +100°CIndustrial 3.0 3.6 V
VIH High-level input voltage 50% of VCC 5.5 V
VIL Low-level input voltage 030% of VCC V
TIN Input signal transition time 250 ns
Notes: At junction temperatures above those listed above, all delay parameters increase by 0.35% per °C.
Input and output measurement threshold is ~50% of VCC.
X XILINXB
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-74 DS005 (v2.0) March 1, 2013 - Product Specification
Product Obsolete/Under Obsolescence
D.C. Characteristics Over Recommended Operating Conditions
Power-0n Power Supply Requirements
Xilinx FPGAs require a minimum rated power supply current capacity to insure proper initialization, and the power supply
ramp-up time does affect the current required. A fast ramp-up time requires more current than a slow ramp-up time. The
slowest ramp-up time is 50 ms. Current capacity is not specified for a ramp-up time faster than 2ms. The current capacity
varies linealy with ramp-up time, e.g., an XC4036XL with a ramp-up time of 25 ms would require a capacity predicted by the
point on the straight line drawn from 1A at 120 μs to 500 mA at 50 ms at the 25 ms time mark. This point is approximately
750 mA .
Symbol Description Min Max Units
VOH
High-level output voltage @ IOH = -4.0 mA, VCC min (LVTTL) 2.4 V
High-level output voltage @ IOH = -500 μA, (LVCMOS) 90% VCC V
VOL Low-level output voltage @ IOL = 12.0 mA, VCC min (LVTTL) (Note 1) 0.4 V
Low-level output voltage @ IOL = 1500 μA, (LVCMOS) 10% VCC V
VDR Data Retention Supply Voltage (below which configuration data may be lost) 2.5 V
ICCO Quiescent FPGA supply current (Note 2) 5mA
ILInput or output leakage current -10 +10 μA
CIN
Input capacitance (sample tested) BGA, SBGA, PQ, HQ, MQ
packages
10 pF
PGA packages 16 pF
IRPU Pad pull-up (when selected) @ Vin = 0 V (sample tested) 0.02 0.25 mA
IRPD Pad pull-down (when selected) @ Vin = 3.6 V (sample tested) 0.02 0.15 mA
IRLL Horizontal Longline pull-up (when selected) @ logic Low 0.3 2.0 mA
Note 1: With up to 64 pins simultaneously sinking 12 mA.
Note 2: With no output current loads, no active input or Longline pull-up resistors, all I/O pins Tri-stated and floating.
Product Description Ramp-up Time
Fast (120 μs) Slow (50 ms)
XC4005 - 36XL Minimum required current supply 1 A 500 mA
XC4044- 62XL Minimum required current supply 2 A 500 mA
XC4085XL1Minimum required current supply 2 A1500 mA
Notes: 1. The XC4085XL fast ramp-up time is 5 ms.
Devices are guaranteed to initialize properly with the minimum current listed above. A larger capacity power supply may
result in a larger initialization current.
This specification applies to Commercial and Industrial grade products only.
Ramp-up Time is measured from 0 VDC to 3.6 VDC. Peak current required lasts less than 3 ms, and occurs near the
internal power on reset threshold voltage. After initialization and before configuration, ICCmax is less than 10 mA.
XXILINX“
R
DS005 (v2.0) March 1, 2013 - Product Specification 6-75
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Product Obsolete/Under Obsolescence
XC4000XL A.C. Characteristics
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven
from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static
timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature. Values apply to all XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
Global Low Skew Buffer to Clock K
Speed Grade All -3 -2 -1 -09 -08 Units
Description Symbol Device Min Max Max Max Max Max
Delay from pad through GLS buffer to
any clock input, K
TGLS XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
0.3
0.4
0.5
0.6
0.7
0.9
1.1
1.2
1.3
1.4
1.6
2.1
2.7
3.2
3.6
4.0
4.4
4.8
5.3
5.7
6.3
7.2
1.8
2.3
2.8
3.1
3.5
3.8
4.2
4.6
5.0
5.4
6.2
1.6
2.0
2.4
2.7
3.0
3.3
3.6
4.0
4.5
4.7
5.7
1.5
1.9
2.3
2.6
2.9
3.2
3.5
3.9
4.4
4.6
5.5
2.3
3.1
4.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
X XILINXG
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-76 DS005 (v2.0) March 1, 2013 - Product Specification
Product Obsolete/Under Obsolescence
Global Early BUFGEs 1, 2, 5, and 6 to IOB Clock
Global Early BUFGEs 3, 4, 7, and 8 to IOB Clock
Speed Grade All -3 -2 -1 -09 -08 Units
Description Symbol Device Min Max Max Max Max Max
Delay from pad through GE buffer to any
IOB clock input.
TGE XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
0.1
0.3
0.3
0.4
0.4
0.3
0.3
0.2
0.3
0.3
0.4
1.6
1.9
2.2
2.4
2.6
2.8
3.1
3.5
4.0
4.9
5.8
1.4
1.8
1.9
2.1
2.2
2.4
2.7
3.0
3.5
4.3
5.1
1.3
1.7
1.7
1.8
2.1
2.1
2.3
2.6
3.0
3.7
4.7
1.2
1.6
1.7
1.7
2.0
2.0
2.2
2.4
3.0
3.4
4.3
1.5
1.9
3.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Speed Grade All -3 -2 -1 -09 -08 Units
Description Symbol Device Min Max Max Max Max Max
Delay from pad through GE buffer to any
IOB clock input.
TGE XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
0.5
0.7
0.7
0.7
0.8
0.9
0.9
1.0
1.1
1.2
1.3
2.8
3.1
3.5
3.8
4.1
4.4
4.7
5.1
5.5
5.9
6.8
2.5
2.8
3.1
3.3
3.6
3.9
4.2
4.5
4.8
5.2
6.0
2.1
2.7
2.8
2.9
3.4
3.4
3.7
4.0
4.3
4.8
5.5
1.7
2.5
2.7
2.8
3.2
3.3
3.6
3.7
4.3
4.5
5.2
2.4
3.1
4.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XXILINX“
R
DS005 (v2.0) March 1, 2013 - Product Specification 6-77
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Product Obsolete/Under Obsolescence
XC4000XL CLB Characteristics
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
CLB Switching Characteristic Guidelines
Speed Grade -3 -2 -1 -09 -08
Description Symbol Min Max Min Max Min Max Min Max Min Max
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H’ to X/Y outputs
F/G inputs via transparent latch to Q outputs
C inputs via SR/H0 via H to X/Y outputs
C inputs via H1 via H to X/Y outputs
C inputs via DIN/H2 via H to X/Y outputs
C inputs via EC, DIN/H2 to YQ, XQ output (bypass)
TILO
TIHO
TITO
THH0O
THH1O
THH2O
TCBYP
1.6
2.7
2.9
2.5
2.4
2.5
1.5
1.5
2.4
2.6
2.2
2.1
2.2
1.3
1.3
2.2
2.2
2.0
1.9
2.0
1.1
1.2
2.0
2.0
1.8
1.6
1.8
1.0
1.1
1.9
1.8
1.8
1.5
1.8
0.9
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to COUT
Add/Subtract input (F3) to COUT
Initialization inputs (F1, F3) to COUT
CIN through function generators to X/Y outputs
CIN to COUT, bypass function generators
Carry Net Delay, COUT to CIN
TOPCY
TASCY
TINCY
TSUM
TBYP
TNET
2.7
3.3
2.0
2.8
0.26
0.32
2.3
2.9
1.8
2.6
0.23
0.28
2.0
2.5
1.5
2.4
0.20
0.25
1.6
1.8
1.0
1.7
0.14
0.24
1.6
1.8
0.9
1.5
0.14
0.24
Sequential Delays
Clock K to Flip-Flop outputs Q
Clock K to Latch outputs Q
TCKO
TCKLO
2.1
2.1
1.9
1.9
1.6
1.6
1.5
1.5
1.4
1.4
Setup Time before Clock K
F/G inputs
F/G inputs via H
C inputs via H0 through H
C inputs via H1 through H
C inputs via H2 through H
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
CIN input via F/G
CIN input via F/G and H
TICK
TIHCK
THH0CK
THH1CK
THH2CK
TDICK
TECCK
TRCK
TCCK
TCHCK
1.1
2.2
2.0
1.9
2.0
0.9
1.0
0.6
2.3
3.4
1.0
1.9
1.7
1.6
1.7
0.8
0.9
0.5
2.1
3.0
0.9
1.7
1.6
1.4
1.6
0.7
0.8
0.5
1.9
2.7
0.8
1.6
1.4
1.2
1.4
0.6
0.7
0.4
1.3
2.1
0.8
1.5
1.4
1.1
1.4
0.6
0.7
0.4
1.2
2.0
Hold Time after Clock K
F/G inputs
F/G inputs via H
C inputs via SR/H0 through H
C inputs via H1 through H
C inputs via DIN/H2 through H
C inputs via DIN/H2
C inputs via EC
C inputs via SR, going Low (inactive)
TCKI
TCKIH
TCKHH0
TCKHH1
TCKHH2
TCKDI
TCKEC
TCKR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Clock
Clock High time
Clock Low time
TCH
TCL
3.0
3.0
2.8
2.8
2.5
2.5
2.3
2.3
2.1
2.1
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
TRPW
TRIO
3.0
3.7
2.8
3.2
2.5
2.8
2.3
2.7
2.3
2.6
Global Set/Reset
Minimum GSR Pulse Width TMRW 19.8 17.3 15.0 14.0 14.0
Delay from GSR input to any Q TMRQ See Table on page 85 for TRRI values per device.
Toggle Frequency (MHz) (for export control) FTOG (MHz) 166 179 200 217 238
X XILINXB
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-78 DS005 (v2.0) March 1, 2013 - Product Specification
Product Obsolete/Under Obsolescence
CLB Single-Port RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
Single Port RAM Speed Grade -3 -2 -1 -09 -08
Size Symbol Min Max Min Max Min Max Min Max Min Max
Write Operation
Address write cycle time (clock K period) 16x2
32x1
TWCS
TWCTS
9.0
9.0
8.4
8.4
7.7
7.7
7.4
7.4
7.4
7.4
Clock K pulse width (active edge) 16x2
32x1
TWPS
TWPTS
4.5
4.5
4.2
4.2
3.9
3.9
3.7
3.7
3.7
3.7
Address setup time before clock K 16x2
32x1
TASS
TASTS
2.2
2.2
2.0
2.0
1.7
1.7
1.7
1.7
1.6
1.7
Address hold time after clock K 16x2
32x1
TAHS
TAHTS
0
0
0
0
0
0
0
0
0
0
DIN setup time before clock K 16x2
32x1
TDSS
TDSTS
2.0
2.5
1.9
2.3
1.7
2.1
1.7
2.1
1.7
2.1
DIN hold time after clock K 16x2
32x1
TDHS
TDHTS
0
0
0
0
0
0
0
0
0
0
WE setup time before clock K 16x2
32x1
TWSS
TWSTS
2.0
1.8
1.8
1.7
1.6
1.5
1.6
1.5
1.6
1.5
WE hold time after clock K 16x2
32x1
TWHS
TWHTS
0
0
0
0
0
0
0
0
0
0
Data valid after clock K 16x2
32x1
TWOS
TWOTS
6.8
8.1
6.3
7.5
5.8
6.9
5.8
6.7
5.7
6.7
Read Operation
Address read cycle time 16x2
32x1
TRC
TRCT
4.5
6.5
3.1
5.5
2.6
3.8
2.6
3.8
2.6
3.8
Data Valid after address change (no
Write Enable)
16x2
32x1
TILO
TIHO
1.6
2.7
1.5
2.4
1.3
2.2
1.2
2.0
1.1
1.9
Address setup time before clock K 16x2
32x1
TICK
TIHCK
1.1
2.2
1.0
1.9
0.9
1.7
0.8
1.6
0.8
1.5
XXILINX“
R
DS005 (v2.0) March 1, 2013 - Product Specification 6-79
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Product Obsolete/Under Obsolescence
CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
CLB RAM Synchronous (Edge-Triggered) Write Timing Waveforms
Dual Port RAM Speed Grade -3 -2 --1 -09 -08
Size Symbol Min Max Min Max Min Max Min Max Min Max
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
TWCDS
TWPDS
TASDS
TAHDS
TDSDS
TDHDS
TWSDS
TWHDS
TWODS
9.0
4.5
2.5
0
2.5
0
1.8
0
7.8
8.4
4.2
2.0
0
2.3
0
1.7
0
7.3
7.7
3.9
1.7
0
2.0
0
1.6
0
6.7
7.4
3.7
1.7
0
2.0
0
1.6
0
6.7
7.4
3.7
1.6
0
2.0
0
1.6
0
6.6
X6461
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT OLD NEW
TDSS TDHS
TASS TAHS
TWSS
TWPS
TWHS
TWOS
TILO
TILO
WCLK (K)
WE
ADDRESS
DATA IN
T
DSDS
T
DHDS
T
ASDS
T
AHDS
T
WSDS
T
WPDS
T
WHDS
X6474
DATA OUT OLD NEW
T
WODS
T
ILO
T
ILO
Single-Port RAM Dual-Port RAM
X XILINXG
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-80 DS005 (v2.0) March 1, 2013 - Product Specification
Product Obsolete/Under Obsolescence
XC4000XL Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
Output Flip-Flop, Clock to Out
Capacitive Load Factor
Figure 1 shows the relationship between I/O output delay
and load capacitance. It allows a user to adjust the speci-
fied output delay if the load capacitance is different than
50 pF. For example, if the actual load capacitance is
120 pF, add 2.5 ns to the specified delay. If the load capac-
itance is 20 pF, subtract 0.8 ns from the specified output
delay.
Figure 1 is usable over the specified operating conditions of
voltage and temperature and is independent of the output
slew rate control.
Figure 1: Delay Factor at Various Capacitive Loads
Speed Grade All -3 -2 -1 -09 -08 Units
Description Symbol Device Min Max Max Max Max Max
Global Low Skew Clock to Output us-
ing Output Flip Flop
TICKOF XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
1.2
1.3
1.4
1.5
1.6
1.8
2.0
2.1
2.2
2.3
2.5
7.1
7.7
8.2
8.6
9.0
9.4
9.8
10.3
10.7
11.3
12.2
6.1
6.6
7.1
7.4
7.8
8.1
8.5
8.9
9.3
9.7
10.5
5.4
5.8
6.2
6.5
6.8
7.1
7.4
7.8
8.3
8.5
9.5
5.1
5.4
5.8
6.1
6.4
6.7
7.0
7.4
7.9
8.1
9.0
5.6
6.4
7.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
For output SLOW option add TSLOW All Devices 0.5 3.0 2.5 2.0 1.7 1.6 ns
Notes: Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is
measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin
clock-to-out delay for clocked outputs for FAST mode configurations.
Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 1.
X8257
-2
0 20406080
Capacitance (pF)
Delta Delay (ns)
100 120 140
-1
0
1
2
3
XXILINX“
R
DS005 (v2.0) March 1, 2013 - Product Specification 6-81
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Product Obsolete/Under Obsolescence
Output Flip-Flop, Clock to Out, BUFGE #s 1, 2, 5, and 6
Output Flip-Flop, Clock to Out, BUFGE #s 3, 4, 7, and 8
Speed Grade All -3 -2 -1 -09 -08 Units
Description Symbol Device Min Max Max Max Max Max
Global Early Clock to Output using
Output Flip Flop. Values are for
BUFGE #s 1, 2, 5, and 6.
TICKEOF XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
1.0
1.2
1.2
1.3
1.3
1.2
1.2
1.1
1.2
1.2
1.3
6.6
6.9
7.2
7.4
7.6
7.8
8.1
8.5
9.0
9.9
10.8
5.7
6.1
6.2
6.4
6.5
6.7
7.0
7.3
7.8
8.6
9.4
5.1
5.5
5.5
5.6
5.9
5.9
6.1
6.4
6.8
7.5
8.5
4.8
5.2
5.3
5.3
5.6
5.6
5.8
6.0
6.6
7.0
7.9
4.8
5.2
6.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is
measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin
clock-to-out delay for clocked outputs for FAST mode configurations.
Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 1.
Speed Grade All -3 -2 -1 -09 -08 Units
Description Symbol Device Min Max Max Max Max Max
Global Early Clock to Output using
Output Flip Flop. Values are for
BUFGE #s 3, 4, 7, and 8.
TICKEOF XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
1.3
1.5
1.6
1.6
1.7
1.7
1.8
1.9
2.0
2.0
2.2
7.8
8.1
8.5
8.8
9.1
9.4
9.7
10.1
10.5
10.9
11.8
6.8
7.1
7.4
7.6
7.9
8.2
8.5
8.8
9.1
9.5
10.3
5.9
6.5
6.6
6.7
7.2
7.2
7.5
7.8
8.1
8.6
9.3
5.3
6.1
6.3
6.4
6.8
6.9
7.2
7.3
7.9
8.1
8.8
5.7
6.4
7.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is
measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin
clock-to-out delay for clocked outputs for FAST mode configurations.
Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 1.
X XILINXB
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-82 DS005 (v2.0) March 1, 2013 - Product Specification
Product Obsolete/Under Obsolescence
XC4000XL Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted
Global Low Skew Clock, Set-Up and Hold
Speed Grade -3 -2 -1 -09 -08 Units
Description Symbol Device Min Min Min Min Min
Input Setup and Hold Times
No Delay
Global Low Skew Clock and IFF
Global Low Skew Clock and FCL
TPSN/TPHN XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
2.5 / 1.5
1.2 / 2.6
1.2 / 3.0
1.2 / 3.2
1.2 / 3.7
1.2 / 4.4
1.2 / 5.5
1.2 / 5.8
1.2 / 7.1
1.2 / 7.0
1.2 / 9.4
2.2 / 1.3
1.1 / 2.2
1.1 / 2.6
1.1 / 2.8
1.1 / 3.2
1.1 / 3.8
1.1 / 4.8
1.1 / 5.0
1.1 / 6.2
1.1 / 6.1
1.1 / 8.2
1.9 / 1.2
0.9 / 2.0
0.9 / 2.3
0.9 / 2.4
0.9 / 2.8
0.9 / 3.3
0.9 / 4.1
0.9 / 4.4
0.9 / 5.4
0.9 / 5.3
0.9 / 7.1
1.7 / 1.0
0.8 / 1.7
0.8 / 2.0
0.8 / 2.1
0.8 / 2.4
0.8 / 2.9
0.8 / 3.6
0.8 / 3.8
0.8 / 4.7
0.8 / 4.6
0.8 / 6.2
0.8 / 2.1
0.8 / 3.6
0.8 / 4.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Partial Delay
Global Low Skew Clock and IFF
Global Low Skew Clock and FCL
TPSP/TPHP XC4002XL
XC4005XL
XC4010XL
XC4013XL*
XC4020XL
XC4028XL
XC4036XL*
XC4044XL
XC4052XL
XC4062XL*
XC4085XL
8.4 / 0.0
10. 5 / 0.0
11.1 / 0.0
6.1 / 1.0
11.9 / 1.0
12.3 / 1.0
6.4 / 1.0
13.1 / 1.0
11.9 / 1.0
6.7 / 1.2
12.9 / 1.2
7.3 / 0.0
9.1 / 0.0
9.7 / 0.0
5.3 / 1.0
10.3 / 1.0
10.7 / 1.0
5.6 / 1.0
11.4 / 1.0
10.3 / 1.0
5.8 / 1.2
11.2 / 1.2
6.3 / 0.0
7.9 / 0.0
8.4 / 0.0
4.6 / 1.0
9.0 / 1.0
9.3 / 1.0
4.8 / 1.0
9.9 / 1.0
9.0 / 1.0
5.1 / 1.2
9.8 / 1.2
5.5 / 0.0
6.9 / 0.0
7.3 / 0.0
4.0 / 1.0
7.8 / 1.0
8.1 / 1.0
4.2 / 1.0
8.6 / 1.0
7.8 / 1.0
4.4 / 1.2
8.5 / 1.2
3.7 / 0.5
4.0/ 0.8
4.2/ 1.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Full Delay
Global Low Skew Clock and IFF
TPSD/TPHD XC4002XL
XC4005XL
XC4010XL
XC4013XL*
XC4020XL
XC4028XL
XC4036XL*
XC4044XL
XC4052XL
XC4062XL*
XC4085XL
6.8 / 0.0
8.8 / 0.0
9.0 / 0.0
6.4 / 0.0
8.8 / 0.0
9.3 / 0.0
6.6 / 0.0
10.6 / 0.0
11.2 / 0.0
6.8 / 0.0
12.7 / 0.0
6.0 / 0.0
7.6 / 0.0
7.8 / 0.0
6.0 / 0.0
7.6 / 0.0
8.1 / 0.0
6.2 / 0.0
9.2 / 0.0
9.7 / 0.0
6.4 / 0.0
11.0 / 0.0
5.2 / 0.0
6.6 / 0.0
6.8 / 0.0
5.6 / 0.0
6.6 / 0.0
7.0 / 0.0
5.8 / 0.0
8.0 / 0.0
8.4 / 0.0
6.0 / 0.0
9.6 / 0.0
4.5 / 0.0
5.6 / 0.0
5.8 / 0.0
4.8 / 0.0
6.2 / 0.0
6.4 / 0.0
5.3 / 0.0
6.8 / 0.0
7.0 / 0.0
5.5 / 0.0
8.4 / 0.0
4.8 / 0.0
5.3 / 0.0
5.5 / 0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IFF = Input Flip-Flop or Latch
* The XC4013XL, XC4036XL, and 4062XL have significantly faster partial and full delay setup times than other devices.
Notes: Input setup time is measured with the fastest route and the lightest load.
Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification.
XXILINX“
R
DS005 (v2.0) March 1, 2013 - Product Specification 6-83
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Product Obsolete/Under Obsolescence
Global Early Clock BUFGEs 1, 2, 5, and 6 Set-up and Hold for IFF and FCL
Speed Grade -3 -2 -1 -09 -08 Units
Description Symbol Device Min Min Min Min Min
Input Setup and Hold
Times
No Delay
Global Early Clock and IFF
Global Early Clock and
FCL
TPSEN/TPHEN
TPFSEN/TPFHEN
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
2.8 / 1.5
1.2 / 4.1
1.2 / 4.4
1.2 / 4.7
1.2 / 4.6
1.2 / 5.3
1.2 / 6.7
1.2 / 6.5
1.2 / 6.7
1.2 / 8.4
1.2 / 8.7
2.5 / 1.3
1.1 / 3.6
1.1 / 3.8
1.1 / 4.1
1.1 / 4.0
1.1 / 4.6
1.1 / 5.8
1.1 / 5.7
1.1 / 5.8
1.1 / 7.3
1.1 / 7.5
2.2 / 1.2
0.9 / 3.1
0.9 / 3.3
0.9 / 3.6
0.9 / 3.5
0.9 / 4.0
0.9 / 5.1
0.9 / 4.9
0.9 / 5.1
0.9 / 6.3
0.9 / 6.6
1.9 / 1.0
0.8 / 2.7
0.8 / 2.9
0.8 / 3.1
0.8 / 3.0
0.8 / 3.5
0.8 / 4.4
0.8 / 4.3
0.8 / 4.4
0.8 / 5.5
0.8 / 5.7
0.5 / 2.7
0.5 / 3.7
0.5 / 4.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Partial Delay
Global Early Clock and IFF
Global Early Clock and
FCL
TPSEP/TPHEP
TPFSEP/TPFHEP
XC4002XL
XC4005XL
XC4010XL
XC4013XL*
XC4020XL
XC4028XL
XC4036XL*
XC4044XL
XC4052XL
XC4062XL*
XC4085XL
8.1 / 0.9
9.0 / 0.0
11.9 / 0.0
6.4 / 0.0
10.8 / 0.0
14.0 / 0.0
7.0 / 0.0
14.6 / 0.0
16.4 / 0.0
9.0 / 0.8
16.7 / 0.0
7.0 / 0.8
8.5 / 0.0
10.4 / 0.0
5.9 / 0.0
10.3 / 0.0
12.2 / 0.0
6.6 / 0.0
12.7 / 0.0
14.3 / 0.0
8.6 / 0.8
14.5 / 0.0
6.1 / 0.7
8.0 / 0.0
9.0 / 0.0
5.4 / 0.0
9.8 / 0.0
10.6 / 0.0
6.2 / 0.0
11.0 / 0.0
12.4 / 0.0
8.2 / 0.8
12.6 / 0.0
5.3 / 0.6
7.5 / 0.0
8.0 / 0.0
4.9 / 0.0
9.0 / 0.0
9.8 / 0.0
5.2 / 0.0
10.8 / 0.0
11.4 / 0.0
7.0 / 0.8
11.6 / 0.0
4.4 / 0.0
4.7 / 0.0
6.3 / 0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Full Delay
Global Early Clock and IFF TPSED/TPHED
XC4002XL
XC4005XL
XC4010XL
XC4013XL*
XC4020XL
XC4028XL
XC4036XL*
XC4044XL
XC4052XL
XC4062XL*
XC4085XL
6.7 / 0.0
10.8 / 0.0
10.3 / 0.0
10.0 / 0.0
12.0 / 0.0
12.6 / 0.0
12.2 / 0.0
13.8 / 0.0
14.1 / 0.0
13.1 / 0.0
17.9 / 0.0
5.8 / 0.0
9.4 / 0.0
9.0 / 0.0
8.7 / 0.0
10.4 / 0.0
11.0 / 0.0
10.6 / 0.0
12.0 / 0.0
12.3 / 0.0
11.4 / 0.0
15.6 / 0.0
5.1 / 0.0
8.2 / 0.0
7.8 / 0.0
7.6 / 0.0
9.1 / 0.0
9.5 / 0.0
9.2 / 0.0
10.5 / 0.0
10.7 / 0.0
9.9 / 0.0
13.6 / 0.0
4.4 / 0.0
7.1 / 0.0
6.8 / 0.0
6.6 / 0.0
7.9 / 0.0
8.3 / 0.0
8.0 / 0.0
9.1 / 0.0
9.3 / 0.0
8.6 / 0.0
11.8 / 0.0
6.0 / 0.0
7.2 / 0.0
7.8 / 0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
* The XC4013XL, XC4036XL, and 4062XL have significantly faster partial and full delay setup times than other devices.
Notes: Input setup time is measured with the fastest route and the lightest load.
Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification.
X XILINXG
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-84 DS005 (v2.0) March 1, 2013 - Product Specification
Product Obsolete/Under Obsolescence
Global Early Clock BUFGEs 3, 4, 7, and 8 Set-up and Hold for IFF and FCL
Speed Grade -3 -2 -1 -09 -08 Units
Description Symbol Device Min Min Min Min Min
Input Setup & Hold Times
No Delay
Global Early Clock and
IFF
Global Early Clock and
FCL
TPSEN/TPHEN
TPFSEN/TPFHEN
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
3.0 / 2.0
1.2 / 4.1
1.2 / 4.4
1.2 / 4.7
1.2 / 4.6
1.2 / 5.3
1.2 / 6.7
1.2 / 6.5
1.2 / 6.7
1.2 / 8.4
1.2 / 8.7
2.6 / 1.7
1.1 / 3.6
1.1 / 3.8
1.1 / 4.1
1.1 / 4.0
1.1 / 4.6
1.1 / 5.8
1.1 / 5.7
1.1 / 5.8
1.1 / 7.3
1.1 / 7.5
2.3 / 1.5
0.9 / 3.1
0.9 / 3.3
0.9 / 3.6
0.9 / 3.5
0.9 / 4.0
0.9 / 5.1
0.9 / 4.9
0.9 / 5.1
0.9 / 6.3
0.9 / 6.6
2.0 / 1.3
0.8 / 2.7
0.8 / 2.9
0.8 / 3.1
0.8 / 3.0
0.8 / 3.5
0.8 / 4.4
0.8 / 4.3
0.8 / 4.4
0.8 / 5.5
0.8 / 5.7
0.5 / 2.7
0.5 / 3.7
0.5 / 4.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Partial Delay
Global Early Clock and
IFF
Global Early Clock and
FCL
TPSEP/TPHEP
TPFSEP/TPFHEP
XC4002XL
XC4005XL
XC4010XL
XC4013XL*
XC4020XL
XC4028XL
XC4036XL*
XC4044XL
XC4052XL
XC4062XL*
XC4085XL
7.3 / 1.5
8.4 / 0.0
10.3 / 0.0
5.4 / 0.0
9.8 / 0.0
12.7 / 0.0
6.4 / 0.8
13.8 / 0.0
14.5 / 0.0
8.4 / 1.5
14.5 / 0.0
6.4 / 1.3
7.9 / 0.0
9.0 / 0.0
4.9 / 0.0
9.3 / 0.0
11.0 / 0.0
5.9 / 0.8
12.0 / 0.0
12.7 / 0.0
7.9 / 1.5
12.7 / 0.0
5.5 / 1.2
7.4 / 0.0
7.8 / 0.0
4.4 / 0.0
8.8 / 0.0
9.6 / 0.0
5.4 / 0.8
10.4 / 0.0
11.0 / 0.0
7.4 / 1.5
11.0 / 0.0
4.8 / 1.0
7.2 / 0.0
7.4 / 0.0
4.3 / 0.0
8.5 / 0.0
9.3 / 0.0
5.0 / 0.8
10.2 / 0.0
10.7 / 0.0
6.8 / 1.5
10.8 / 0.0
4.0 / 0.0
4.6 / 0.2
6.2 / 0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Full Delay
Global Early Clock and
IFF
TPSED/TPHED
XC4002XL
XC4005XL
XC4010XL
XC4013XL*
XC4020XL
XC4028XL
XC4036XL*
XC4044XL
XC4052XL
XC4062XL*
XC4085XL
5.9 / 0.0
10.8 / 0.0
10.3 / 0.0
10.0 / 0.0
12.0 / 0.0
12.6 / 0.0
12.2 / 0.0
13.8 / 0.0
14.1 / 0.0
13.1 / 0.0
17.9 / 0.0
5.2 / 0.0
9.4 / 0.0
9.0 / 0.0
8.7 / 0.0
10.4 / 0.0
11.0 / 0.0
10.6 / 0.0
12.0 / 0.0
12.3 / 0.0
11.4 / 0.0
15.6 / 0.0
4.5 / 0.0
8.2 / 0.0
7.8 / 0.0
7.6 / 0.0
9.1 / 0.0
9.5 / 0.0
9.2 / 0.0
10.5 / 0.0
10.7 / 0.0
9.9 / 0.0
13.6 / 0.0
3.9 / 0.0
7.1 / 0.0
6.8 / 0.0
6.6 / 0.0
7.9 / 0.0
8.3 / 0.0
8.0 / 0.0
9.1 / 0.0
9.3 / 0.0
8.6 / 0.0
11.8 / 0.0
6.0 / 0.0
7.2 / 0.0
7.8 / 0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* The XC4013XL, XC4036XL, and 4062XL have significantly faster partial and full delay setup times than other devices.
IFF = Input Flip Flop or Latch. FCL = Fast Capture Latch
Notes: Input setup time is measured with the fastest route and the lightest load.
Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification.
XXILINX”
R
DS005 (v2.0) March 1, 2013 - Product Specification 6-85
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Product Obsolete/Under Obsolescence
XC4000XL IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature).
Speed Grade -3 -2 -1 -09 -08 Units
Description Symbol Device Min Min Min Min Min
Clocks
Clock Enable (EC) to Clock (IK) TECIK All devices 0.1 0.1 0.1 0.1 0.1 ns
Delay from FCL enable (OK) active edge to
IFF clock (IK) active edge
TOKIK XC4002XL
XC4013, 36, 62XL
Balance of Family
3.0
2.2
2.2
2.7
1.9
1.9
2.3
1.6
1.6
2.3
1.6
1.6
1.6
ns
ns
ns
Setup Times
Pad to Clock (IK), no delay TPICK XC4002XL
XC4013, 36, 62XL
Balance of Family
2.6
1.7
1.7
2.3
1.5
1.5
2.0
1.3
1.3
2.0
1.3
1.3
1.2
ns
ns
ns
Pad to Clock (IK), via transparent Fast Cap-
ture Latch, no delay
TPICKF XC4002XL
XC4013, 36, 62XL
Balance of Family
3.2
2.3
2.3
2.9
2.0
2.0
2.5
1.8
1.8
2.4
1.7
1.7
1.6
ns
ns
ns
Pad to Fast Capture Latch Enable (OK), no
delay
TPOCK XC4013, 36, 62XL
Balance of Family
1.2
1.2
1.0
1.0
0.9
0.9
0.9
0.9
0.9 ns
ns
Hold Times
All Hold Times All Devices 0 0 0 0 0
Global Set/Reset
Minimum GSR Pulse Width TMRW All devices 19.8 17.3 15.0 14.0 14.0 ns
Global Set/Reset Max Max Max Max Max
Delay from GSR input to any Q TRRI* XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
9.8
11.3
13.9
15.9
18.6
20.5
22.5
25.1
27.2
29.1
34.4
8.5
9.8
12.1
13.8
16.1
17.9
19.6
21.9
23.6
25.3
29.9
7.4
8.5
10.5
12.0
14.0
15.5
17.0
19.0
20.5
22.0
26.0
7.0
8.1
10.0
11.4
13.3
14.3
16.2
18.1
19.5
20.9
24.7
10.9
16.2
20.4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Propagation Delays
Pad to I1, I2 TPID All devices 1.6 1.4 1.2 1.1 1.0 ns
Pad to I1, I2 via transparent input latch,
no delay
TPLI XC4002XL
XC4013, 36, 62XL
Balance of Family
4.7
3.1
3.1
4.2
2.7
2.7
3.6
2.4
2.4
3.5
2.2
2.2
2.1
ns
ns
ns
Pad to I1, I2 via transparent FCL and in-
put latch, no delay
TPFLI X4002XL
XC4013, 36, 62XL
Balance of Family
5.4
3.7
3.7
4.7
3.3
3.3
4.1
2.8
2.8
3.9
2.7
2.7
2.5
ns
ns
ns
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2 (latch enable, active
Low)
FCL Enable (OK) active edge to I1, I2
(via transparent standard input latch)
TIKRI
TIKLI
TOKLI
All devices
All devices
XC4002XL
XC4013, 36, 62XL
Balance of Family
1.7
1.8
5.2
3.6
3.6
1.5
1.6
4.6
3.1
3.1
1.3
1.4
4.0
2.7
2.7
1.2
1.3
3.8
2.6
2.6
1.2
1.3
2.5
ns
ns
ns
ns
ns
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
* Indicates Minimum Amount of Time to Assure Valid Data.
X XILINXB
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-86 DS005 (v2.0) March 1, 2013 - Product Specification
Product Obsolete/Under Obsolescence
XC4000XL IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless
otherwise noted. Values are expressed in nanoseconds unless otherwise noted.
-3 -2 -1 -09 -08
Description Symbol Min Max Min Max Min Max Min Max Min Max
Clocks
Clock High
Clock Low
TCH
TCL
3.0
3.0
2.8
2.8
2.5
2.5
2.3
2.3
2.1
2.1
Propagation Delays
Clock (OK) to Pad
Output (O) to Pad
3-state to Pad hi-Z (slew-rate independent)
3-state to Pad active and valid
Output (O) to Pad via Fast Output MUX
Select (OK) to Pad via Fast MUX
TOKPOF
TOPF
TTSHZ
TTSONF
TOFPF
TOKFPF
5.0
4.1
4.0
4.4
5.5
5.1
4.3
3.6
3.5
3.8
4.8
4.5
3.8
3.1
3.0
3.3
4.2
3.9
3.5
3.0
2.9
3.3
4.0
3.7
3.3
2.8
2.9
3.3
3.7
3.4
Setup and Hold Times
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
Clock Enable (EC) to clock (OK) setup time
Clock Enable (EC) to clock (OK) hold time
TOOK
TOKO
TECOK
TOKEC
0.5
0.0
0.0
0.3
0.4
0.0
0.0
0.2
0.3
0.0
0.0
0.1
0.3
0.0
0.0
0.0
0.3
0.0
0.0
0.0
Global Set/Reset
Minimum GSR pulse width
Delay from GSR input to any Pad
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
TMRW
TRPO*
19.8
14.3
15.9
18.5
20.5
23.2
25.1
27.1
29.7
31.7
33.7
39.0
17.3
12.5
13.8
16.1
17.8
20.1
21.9
23.6
25.9
27.6
29.3
33.9
15.0
10.9
12.0
14.0
15.5
17.5
19.0
20.5
22.5
24.0
25.5
29.5
14.0
10.3
11.4
13.3
14.7
16.6
17.6
19.4
21.4
22.8
24.2
28.0
14.0
14.0
19.3
23.5
Slew Rate Adjustment
For output SLOW option add TSLOW 3.0 2.5 2.0 1.7 1.6
Note: Output timing is measured at ~50% VCC threshold, with 50 pF external capacitive loads.
* Indicates Minimum Amount of Time to Assure Valid Data.
XXILINX“ XCN08011
R
DS005 (v2.0) March 1, 2013 - Product Specification 6-87
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Product Obsolete/Under Obsolescence
Revision Control
Version Nature of Changes
02/01/1999 (1.5) Release included in the 1999 data book, section 6
05/14/1999 (1.6) Replaced Electrical Specification and pinout pages for E, EX, and XL families with separate updates and
added URL link on placeholder page for electrical specifications/pinouts for WebLINX users
09/30/1999 (1.7) Added Power-on specification.
10/18/1999 (1.8) Corrected posted file to include missing page (IOB Output Parameters).
03/01/2013 (2.0) The products listed in this data sheet are obsolete. See XCN08011 for further information.
X XILINX®
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-88 DS005 (v2.0) March 1, 2013 - Product Specification
Product Obsolete/Under Obsolescence

Products related to this Datasheet

IC FPGA 112 I/O 160QFP
Available Quantity: 0
Unit Price: 0
IC FPGA 112 I/O 208QFP
Available Quantity: 0
Unit Price: 0
IC FPGA 112 I/O 144TQFP
Available Quantity: 0
Unit Price: 0
IC FPGA 77 I/O 100VQFP
Available Quantity: 0
Unit Price: 0
IC FPGA 160 I/O 256BGA
Available Quantity: 0
Unit Price: 0
IC FPGA 77 I/O 100QFP
Available Quantity: 0
Unit Price: 0
IC FPGA 160 I/O 208QFP
Available Quantity: 0
Unit Price: 0
IC FPGA 113 I/O 144TQFP
Available Quantity: 0
Unit Price: 0
IC FPGA 145 I/O 176TQFP
Available Quantity: 0
Unit Price: 0
IC FPGA 192 I/O 256BGA
Available Quantity: 0
Unit Price: 0
IC FPGA 129 I/O 160QFP
Available Quantity: 0
Unit Price: 0
IC FPGA 160 I/O 208QFP
Available Quantity: 0
Unit Price: 0
IC FPGA 192 I/O 240QFP
Available Quantity: 0
Unit Price: 0
IC FPGA 192 I/O 256BGA
Available Quantity: 0
Unit Price: 0
IC FPGA 192 I/O 256BGA
Available Quantity: 0
Unit Price: 0
IC FPGA 129 I/O 160QFP
Available Quantity: 0
Unit Price: 0
IC FPGA 129 I/O 160QFP
Available Quantity: 0
Unit Price: 0
IC FPGA 160 I/O 208QFP
Available Quantity: 0
Unit Price: 0
IC FPGA 160 I/O 208QFP
Available Quantity: 0
Unit Price: 0
IC FPGA 192 I/O 240QFP
Available Quantity: 0
Unit Price: 0
IC FPGA 192 I/O 240QFP
Available Quantity: 0
Unit Price: 0
IC FPGA 192 I/O 256BGA
Available Quantity: 0
Unit Price: 0
IC FPGA 192 I/O 256BGA
Available Quantity: 0
Unit Price: 0
IC FPGA 129 I/O 160QFP
Available Quantity: 0
Unit Price: 0
IC FPGA 129 I/O 160QFP
Available Quantity: 0
Unit Price: 0
IC FPGA 256 I/O 352MBGA
Available Quantity: 0
Unit Price: 0
IC FPGA 160 I/O 208QFP
Available Quantity: 0
Unit Price: 0
IC FPGA 193 I/O 240QFP
Available Quantity: 0
Unit Price: 0
IC FPGA 352 I/O 432MBGA
Available Quantity: 0
Unit Price: 0
IC FPGA 384 I/O 560MBGA
Available Quantity: 0
Unit Price: 0