MUN5212DW1, NSBC124EDxx Datasheet by onsemi

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0N Semiconductor® network consisting of iwt) ms stars, a . basercmitter resistor. The BRT eliminates these Individual components by integrating them into n single device. The use Ufa BRT can reduce both system cost and board space. i Features - Simplifies Circuit Design - Reduces Board Space - Reduces Component Count - s and NSV Prefix for Automotive and Other Applications H H H Requiring Unique site and Control Change Requirements; AEC’QIUI Qualified and PPAP Capablc' y 0 I These Devices arc PbrFrcc, Halogen Free/BFR Free and am RuHs LI LI LI Compliant n n n MAXIMUM RATINGS ('rA : 25°C, common for or and 02, untess otherwtse noted) 0 e Rattng Symbol Max UnIt u. in u. CollectoIrBase Voltage Vega 50 Vdc CollectoIrEmItter Voltage vCEO 50 Vdc n Cottector Cunent — Continuous lc too mAdc Q 0 Input Forward Voltage VINM, 40 Vdc ’ u. Input Reverse Voltage vwev, to Vdc Stresses exceeding those tisted in the Maximum Ratings table may damage the oeyice. It any ot these limits are exceeded. oeviee Iuncltonahiy should not be assumed. oamage may occur ano reliability may be atteetect. ORDERING INFORMATION Devlce Package Shlpplng' MUstt zuwm G. SOT—sea moo/Tape & Reel NSVMUNSZIZDWITIG' NSBCIZAEDXVSTI G SOT-563 4,000/Tape & Reel NSBCIZAEDXVSTSG SOT-563 8,000/Tape & Reel NSBCIZAEDPSTSG SOT-963 8,000/Tape & Reel 1For Inlotmaiton on tape amt reeI speeitications, Includtng part orientation ano tape sizes. please reter to our Tape amt Reel Packaging Spectltcations Brochure, BRDsmt/D, e eemreananeraresmaanenunansnee LLC 2m2 7: Puhhcaiion OIdeI Numhet. June, 2017 - Rev. 1 DTC124ED/D
© Semiconductor Components Industries, LLC, 2012
June, 2017 Rev. 1
73 Publication Order Number:
DTC124ED/D
MUN5212DW1,
NSBC124EDXV6,
NSBC124EDP6
Dual NPN Bias Resistor
Transistors
R1 = 22 kW, R2 = 22 kW
NPN Transistors with Monolithic Bias
Resistor Network
This series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a
base-emitter resistor. The BRT eliminates these individual
components by integrating them into a single device. The use of a BRT
can reduce both system cost and board space.
Features
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
S and NSV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements;
AEC-Q101 Qualified and PPAP Capable*
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS
(TA = 25°C, common for Q1 and Q2, unless otherwise noted)
Rating Symbol Max Unit
Collector-Base Voltage VCBO 50 Vdc
Collector-Emitter Voltage VCEO 50 Vdc
Collector Current Continuous IC100 mAdc
Input Forward Voltage VIN(fwd) 40 Vdc
Input Reverse Voltage VIN(rev) 10 Vdc
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
Device Package Shipping
MUN5212DW1T1G,
NSVMUN5212DW1T1G*
SOT363 3,000/Tape & Reel
NSBC124EDXV6T1G SOT563 4,000/Tape & Reel
NSBC124EDXV6T5G SOT563 8,000/Tape & Reel
NSBC124EDP6T5G SOT963 8,000/Tape & Reel
For information on tape and reel specifications, including part orientation and
tape sizes, please refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
www.onsemi.com
MARKING DIAGRAMS
PIN CONNECTIONS
7B/R = Specific Device Code
M = Date Code*
G= Pb-Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
SOT363
CASE 419B02
SOT563
CASE 463A
Q1
Q2
(1)(2)(3)
(6)(5)(4)
R1
R2
R2
R1
SOT963
CASE 527AD
R M
1
7B MG
G
1
6
7B MG
1
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MUN5212DW1, NSBC124EDXV6, NSBC124EDP6
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74
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
MUN5212DW1 (SOT363) ONE JUNCTION HEATED
Total Device Dissipation
TA = 25°C (Note 49)
(Note 50)
Derate above 25°C (Note 49)
(Note 50)
PD187
256
1.5
2.0
mW
mW/°C
Thermal Resistance, (Note 49)
Junction to Ambient (Note 50)
RqJA 670
490
°C/W
MUN5212DW1 (SOT363) BOTH JUNCTION HEATED (Note 51)
Total Device Dissipation
TA = 25°C (Note 49)
(Note 50)
Derate above 25°C (Note 49)
(Note 50)
PD250
385
2.0
3.0
mW
mW/°C
Thermal Resistance,
Junction to Ambient (Note 49)
(Note 50)
RqJA 493
325
°C/W
Thermal Resistance,
Junction to Lead (Note 49)
(Note 50)
RqJL 188
208
°C/W
Junction and Storage Temperature Range TJ, Tstg 55 to +150 °C
NSBC124EDXV6 (SOT563) ONE JUNCTION HEATED
Total Device Dissipation
TA = 25°C (Note 49)
Derate above 25°C (Note 49)
PD357
2.9
mW
mW/°C
Thermal Resistance,
Junction to Ambient (Note 49)
RqJA 350
°C/W
NSBC124EDXV6 (SOT563) BOTH JUNCTION HEATED (Note 51)
Total Device Dissipation
TA = 25°C (Note 49)
Derate above 25°C (Note 49)
PD500
4.0
mW
mW/°C
Thermal Resistance,
Junction to Ambient (Note 49)
RqJA 250
°C/W
Junction and Storage Temperature Range TJ, Tstg 55 to +150 °C
NSBC124EDP6 (SOT963) ONE JUNCTION HEATED
Total Device Dissipation
TA = 25°C (Note 52)
(Note 53)
Derate above 25°C (Note 52)
(Note 53)
PD231
269
1.9
2.2
MW
mW/°C
Thermal Resistance,
Junction to Ambient (Note 52)
(Note 53)
RqJA 540
464
°C/W
NSBC124EDP6 (SOT963) BOTH JUNCTION HEATED (Note 51)
Total Device Dissipation
TA = 25°C (Note 52)
(Note 53)
Derate above 25°C (Note 52)
(Note 53)
PD339
408
2.7
3.3
MW
mW/°C
Thermal Resistance,
Junction to Ambient (Note 52)
(Note 53)
RqJA 369
306
°C/W
Junction and Storage Temperature Range TJ, Tstg 55 to +150 °C
49.FR4 @ Minimum Pad.
50.FR4 @ 1.0 ×1.0 Inch Pad.
51.Both junction heated values assume total power is sum of two equally powered channels.
52.FR4 @ 100 mm2, 1 oz. copper traces, still air.
53.FR4 @ 500 mm2, 1 oz. copper traces, still air.
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MUN5212DW1, NSBC124EDXV6, NSBC124EDP6
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75
ELECTRICAL CHARACTERISTICS (TA=25°C, common for Q1 and Q2, unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Collector-Base Cutoff Current
(VCB =50V, I
E=0)
ICBO
100
nAdc
Collector-Emitter Cutoff Current
(VCE =50V, I
B=0)
ICEO
500
nAdc
Emitter-Base Cutoff Current
(VEB = 6.0 V, IC=0)
IEBO
0.2
mAdc
Collector-Base Breakdown Voltage
(IC=10mA, IE=0)
V(BR)CBO 50 − −
Vdc
Collector-Emitter Breakdown Voltage (Note 54)
(IC= 2.0 mA, IB=0)
V(BR)CEO 50 − −
Vdc
ON CHARACTERISTICS
DC Current Gain (Note 54)
(IC= 5.0 mA, VCE =10V)
hFE 60 100
Collector-Emitter Saturation Voltage (Note 54)
(IC= 10 mA, IB= 0.3 mA)
VCE(sat)
0.25
V
Input Voltage (Off)
(VCE = 5.0 V, IC= 100 mA)
Vi(off)
1.2
Vdc
Input Voltage (On)
(VCE = 0.2 V, IC= 5.0 mA)
Vi(on)
1.9
Vdc
Output Voltage (On)
(VCC = 5.0 V, VB= 2.5 V, RL= 1.0 kW)
VOL
0.2
Vdc
Output Voltage (Off)
(VCC = 5.0 V, VB= 0.5 V, RL= 1.0 kW)
VOH 4.9 − −
Vdc
Input Resistor R1 15.4 22 28.6 kW
Resistor Ratio R1/R20.8 1.0 1.2
54.Pulsed Condition: Pulse Width = 300 ms, Duty Cycle 2%.
Figure 130. Derating Curve
AMBIENT TEMPERATURE (°C)
12510075502502550
0
50
100
150
200
250
300
PD, POWER DISSIPATION (mW)
150
(1) (2)
(1) SOT363; 1.0 ×1.0 Inch Pad
(2) SOT563; Minimum Pad
(3) SOT963; 100 mm2, 1 oz. Copper Trace
350
400
(3)
MUN5212DW1, NSBC124EDXV6, NSBC124EDP6
www.onsemi.com
76
TYPICAL CHARACTERISTICS
MUN5212DW1, NSBC124EDXV6
Figure 131. VCE(sat) vs. ICFigure 132. DC Current Gain
Figure 133. Output Capacitance Figure 134. Output Current vs. Input Voltage
1000
10
IC, COLLECTOR CURRENT (mA)
TA=75°C
25°C
25°C
100
10 1 100
75°C25°C
100
0
Vin, INPUT VOLTAGE (V)
10
1
0.1
0.01
0.001 246810
TA=25°C
0
IC, COLLECTOR CURRENT (mA)
100
TA=25°C
75°C
10
1
0.1
10 20 30 40 50
Figure 135. Input Voltage vs. Output Current
0.001
TA=25°C
75°C
25°C
0.01
0.1
1
40
IC, COLLECTOR CURRENT (mA)
020 50
50
010 203040
1.6
0.8
0
VR, REVERSE VOLTAGE (V)
IC/IB = 10 VCE = 10 V
f = 10 kHz
IE = 0 A
TA = 25°C
VO = 5 V
VO = 0.2 V
0.4
1.2
2.0
2.4
2.8
3.2
Cob, OUTPUT CAPACITANCE (pF)
Vin, INPUT VOLTAGE (V)
25°C
IC, COLLECTOR CURRENT (mA) hFE, DC CURRENT GAIN
VCE(sat), COLLECTOREMITTER VOLTAGE (V)
MUN5212DW1, NSBC124EDXV6, NSBC124EDP6
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77
TYPICAL CHARACTERISTICS
NSBC124EDP6
Figure 136. VCE(sat) vs. IC
1002030
IC, COLLECTOR CURRENT (mA)
100
1
0.1
40 50
Figure 137. DC Current Gain
Figure 138. Output Capacitance
1
0.1
0.01
02040
50
IC, COLLECTOR CURRENT (mA)
1000
100
10.1 10 100
IC, COLLECTOR CURRENT (mA)
Figure 139. Output Current vs. Input Voltage
100
10
1
0.1
0.01 02 64
Vin, INPUT VOLTAGE (V)
816
Figure 140. Input Voltage vs. Output Current
50
010 203040
0.4
1.2
0
VR, REVERSE VOLTAGE (V)
30
VCE(sat), COLLECTOREMITTER VOLTAGE (V)
IC/IB = 10
55°C
25°C
VCE = 10 V
hFE, DC CURRENT GAIN
f = 10 kHz
IE = 0 A
TA = 25°C
0.8
1.6
2.0
2.4
Cob, OUTPUT CAPACITANCE (pF)
VO = 5 V
IC, COLLECTOR CURRENT (mA)
VO = 0.2 V
Vin, INPUT VOLTAGE (V)
10
150°C
55°C
25°C150°C
1
10
10
55°C
25°C
150°C
55°C
25°C
150°C
10 12 14
TES RADlus 0: THE FOOT DlMENsloNlNG AND mLERANcle PER CONTROLUNG DlMENsloN MlLLlMElE DlMENsloNs D AND El Do NOT lNCLu Pnomuslows. 0R GATE EURRS Mo SIGNS. 0R GATE EURRS SHALL NOT DlMENsloNs D AND El AT THE ouT IHE PLAsTlc Dom AND DAmM H DAluMs A AND E ARE DETERMlNED Al DATUM DlMENsloNs e AND c APPLV TO THE FLAT SEC LEAD BETWEEN a as AND D 15 FROM THE HP 7 DlMENsloN e DOES Not INCLUDE DAMBAR Pnomuslow ALLOWABLE DAMEAR PROTRUSlON SHALL EE 0 DB TOTAL lN EXCESS OF DlMENsloN e AT MAleuM MATERlAL CONDlr lloN THE DAMEAR cANNol BE LocAlED ON IHE LOWER MILLIMEYERS IMCMES DIM MIN MOM MAX mu MOM MAX A r r l m m cm: Al and am undo dam A: we um: um n n27 a mi a L139 ms nza a25 nude 0005 cam and ms L122 a an: n nus a any a am a D75 a use and 2m 22a n me n n52 a use b c DE'IAILA D led and 220 E E l H5 lzs la5 n MS n mg a a5: a me asc dam luau ladle a doe asc duos amz ~ 9 055830 / L n25 l n35 l 046 l l L2 0653!: m ms 7 L J m dam dam \ / if me mm 5mm, \/ c add um SIDE VIEW END VIEW RECOMMENDED SOLDERING FOOTPRINT“ 320% D fi '17?le 2.50 0,65 44 PlTCl-l F DIMENSIONS MlLLIMETERS "Fol addmonel mlmellon on em Pb-Free slrelegy and soldering deleils, please download me ON Semiconductor Soldellng and Mounllng Technlques Reference Manuall SOLDERRM/D, www onsemi com 75
MUN5212DW1, NSBC124EDXV6, NSBC124EDP6
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78
PACKAGE DIMENSIONS
SC88/SC706/SOT363
CASE 419B02
ISSUE Y
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-
TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
Cddd M
123
A1
A
c
654
E
b
6X DIM MIN NOM MAX
MILLIMETERS
A−−− −−− 1.10
A1 0.00 −−− 0.10
ddd
b0.15 0.20 0.25
C0.08 0.15 0.22
D1.80 2.00 2.20
−−− −−− 0.043
0.000 −−− 0.004
0.006 0.008 0.010
0.003 0.006 0.009
0.070 0.078 0.086
MIN NOM MAX
INCHES
0.10 0.004
E1 1.15 1.25 1.35
e0.65 BSC
L0.26 0.36 0.46
2.00 2.10 2.20
0.045 0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.078 0.082 0.086
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.65
0.66
6X
DIMENSIONS: MILLIMETERS
0.30
PITCH
2.50
6X
RECOMMENDED
TOP VIEW
SIDE VIEW END VIEW
bbb H
B
SEATING
PLANE
DETAIL A E
A2 0.70 0.90 1.00 0.027 0.035 0.039
L2 0.15 BSC 0.006 BSC
aaa 0.15 0.006
bbb 0.30 0.012
ccc 0.10 0.004
A-B D
aaa C
2X 3 TIPS
D
E1
D
e
A
2X
aaa H D
2X
D
L
PLANE
DETAIL A
H
GAGE
L2
C
ccc C
A2
6X
\ \ 777+ 7 + "+77 \ \ mchez L www.cnsemi.com
MUN5212DW1, NSBC124EDXV6, NSBC124EDP6
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79
PACKAGE DIMENSIONS
HE
DIM MIN NOM MAX
MILLIMETERS
A0.50 0.55 0.60
b0.17 0.22 0.27
C
D1.50 1.60 1.70
E1.10 1.20 1.30
e0.5 BSC
L0.10 0.20 0.30
1.50 1.60 1.70
0.020 0.021 0.023
0.007 0.009 0.011
0.059 0.062 0.066
0.043 0.047 0.051
0.02 BSC
0.004 0.008 0.012
0.059 0.062 0.066
MIN NOM MAX
INCHES
SOT563, 6 LEAD
CASE 463A
ISSUE G
eM
0.08 (0.003) X
b6 5 PL
A
C
X
Y
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE MATERIAL.
D
E
Y
12 3
45
L
6
1.35
0.0531
0.5
0.0197
ǒmm
inchesǓ
SCALE 20:1
0.5
0.0197
1.0
0.0394
0.45
0.0177
0.3
0.0118
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
HE
0.08 0.12 0.18 0.003 0.005 0.007
«DM -‘ ‘e 2223 7 gt? 5 4 “P“ A? *1 % Emmi \ j ’T’ L T %pn l-ll
MUN5212DW1, NSBC124EDXV6, NSBC124EDP6
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80
PACKAGE DIMENSIONS
SOT963
CASE 527AD
ISSUE E
DIM MIN NOM MAX
MILLIMETERS
A0.34 0.37 0.40
b0.10 0.15 0.20
C0.07 0.12 0.17
D0.95 1.00 1.05
E0.75 0.80 0.85
e0.35 BSC
0.95 1.00 1.05
HE
E
D
C
A
HE
123
456
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
X
Y
TOP VIEW
SIDE VIEW
e
b
X0.08
6X
Y
BOTTOM VIEW
6X
0.35
PITCH
1.20
0.20
DIMENSIONS: MILLIMETERS
RECOMMENDED
PACKAGE
OUTLINE
MOUNTING FOOTPRINT*
L0.19 REF
L2 0.05 0.10 0.15
L
6X
L2
6X
6X
0.35
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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