XC7Z030,35,45,100 Datasheet by Xilinx Inc.

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Product Specification 1
© Copyright 2012–2018 Xilinx, Inc. Xilinx, the Xilinx logo, Zynq, Virtex, Artix, Kintex, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. AMBA, AMBA Designer, ARM, Cortex-A9, CoreSight, Cortex, PrimeCell, ARM Powered, and ARM Connected Partner are trademarks
of ARM Ltd. All other trademarks are the property of their respective owners.
Introduction
The Zynq®-7000 SoCs are available in -3, -2, -2LI, -1, and
-1LQ speed grades, with -3 having the highest performance.
The -2LI devices operate at programmable logic (PL)
VCCINT/VCCBRAM = 0.95V and are screened for lower
maximum static power. The speed specification of a -2LI
device is the same as that of a -2 device. The -1LQ devices
operate at the same voltage and speed as the -1Q devices
and are screened for lower power. Zynq-7000 device DC
and AC characteristics are specified in commercial,
extended, industrial, and expanded (Q-temp) temperature
ranges. Except the operating temperature range or unless
otherwise noted, all the DC and AC electrical parameters
are the same for a particular speed grade (that is, the timing
characteristics of a -1 speed grade industrial device are the
same as for a -1 speed grade commercial device). However,
only selected speed grades and/or devices are available in
the commercial, extended, or industrial temperature ranges.
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The
parameters included are common to popular designs and
typical applications.
The available device/package combinations are outlined in:
Zynq-7000 SoC Overview (DS190)
Defense-grade Zynq-7000Q SoC Overview (DS196)
XA Zynq-7000 SoC Overview (DS188)
This Zynq-7000 SoC data sheet, which covers the
specifications for the XC7Z030, XA7Z030, XQ7Z030,
XC7Z035, XC7Z045, XQ7Z045, XC7Z100, and XQ7Z100
complements the Zynq-7000 SoC documentation suite
available on the Xilinx website at www.xilinx.com/zynq.
DC Characteristics
Zynq-7000 SoC
(Z-7030, Z-7035, Z-7045, and Z-7100):
DC and AC Switching Characteristics
DS191 (v1.18.1) July 2, 2018 Product Specification
Table 1: Absolute Maximum Ratings (1)
Symbol Description Min Max Units
Processing System (PS)
VCCPINT PS internal logic supply voltage –0.5 1.1 V
VCCPAUX PS auxiliary supply voltage –0.5 2.0 V
VCCPLL PS PLL supply –0.5 2.0 V
VCCO_DDR PS DDR I/O supply –0.5 2.0 V
VCCO_MIO(2) PS MIO I/O supply –0.5 3.6 V
VPREF PS input reference voltage –0.5 2.0 V
VPIN(2)(3)(4)(5) PS MIO I/O input voltage –0.40 VCCO_MIO +0.55 V
PS DDR I/O input voltage –0.55 VCCO_DDR +0.55 V
Programmable Logic (PL)
VCCINT PL internal supply voltage –0.5 1.1 V
VCCBRAM PL supply voltage for the block RAM memories –0.5 1.1 V
VCCAUX PL auxiliary supply voltage –0.5 2.0 V
VCCO
PL output drivers supply voltage for HR I/O banks –0.5 3.6 V
PL output drivers supply voltage for HP I/O banks –0.5 2.0 V
VCCAUX_IO(4) Auxiliary supply voltage –0.5 2.06 V
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Product Specification 2
VREF Input reference voltage –0.5 2.0 V
VIN(3)(4)(5)
I/O input voltage for HR I/O banks –0.40 VCCO +0.55 V
I/O input voltage for HP I/O banks –0.55 VCCO +0.55 V
I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards
except TMDS_33(6) –0.40 2.625 V
VCCBATT Key memory battery backup supply –0.5 2.0 V
GTX Transceiver
VMGTAVCC Analog supply voltage for the GTX transmitter and receiver circuits –0.5 1.1 V
VMGTAVTT Analog supply voltage for the GTX transmitter and receiver termination circuits –0.5 1.32 V
VMGTVCCAUX Auxiliary analog Quad PLL (QPLL) voltage supply for the GTX transceivers –0.5 1.935 V
VMGTREFCLK GTX transceiver reference clock absolute input voltage –0.5 1.32 V
VMGTAVTTRCAL Analog supply voltage for the resistor calibration circuit of the GTX transceiver
column –0.5 1.32 V
VIN Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage –0.5 1.26 V
IDCIN-FLOAT DC input current for receiver input pins DC coupled RX termination = floating 14 mA
IDCIN-MGTAVTT DC input current for receiver input pins DC coupled RX termination = VMGTAVTT –12mA
IDCIN-GND DC input current for receiver input pins DC coupled RX termination = GND 6.5 mA
IDCOUT-FLOAT DC output current for transmitter pins DC coupled RX termination = floating 14 mA
IDCOUT-MGTAVTT DC output current for transmitter pins DC coupled RX termination = VMGTAVTT –12mA
XADC
VCCADC XADC supply relative to GNDADC –0.5 2.0 V
VREFP XADC reference input relative to GNDADC –0.5 2.0 V
Temperature
TSTG Storage temperature (ambient) –65 150 °C
TSOL
Maximum soldering temperature for Pb/Sn component bodies(7) +220 °C
Maximum soldering temperature for Pb-free component bodies(7) +260 °C
TjMaximum junction temperature(7) +125 °C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
2. Applies to both MIO supply banks VCCO_MIO0 and VCCO_MIO1.
3. The lower absolute voltage specification always applies.
4. For I/O operation, refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471) or the Zynq-7000 SoC Technical Reference Manual
(UG585).
5. The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4 and Table 5.
6. See Table 12 for TMDS_33 specifications.
7. For soldering guidelines and thermal considerations, see the Zynq-7000 SoC Packaging and Pinout Specification (UG865).
Table 1: Absolute Maximum Ratings (1) (Cont’d)
Symbol Description Min Max Units
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Product Specification 3
Table 2: Recommended Operating Conditions (1)(2)
Symbol Description Min Typ Max Units
PS
VCCPINT(3) PS internal logic supply voltage 0.95 1.00 1.05 V
VCCPAUX PS auxiliary supply voltage 1.71 1.80 1.89 V
VCCPLL PS PLL supply voltage 1.71 1.80 1.89 V
VCCO_DDR PS DDR supply voltage 1.14 1.89 V
VCCO_MIO(4) PS supply voltage for MIO banks 1.71 3.465 V
VPIN(5) PS DDR and MIO I/O input voltage –0.20 VCCO_DDR + 0.20
VCCO_MIO +0.20 V
PL
VCCINT(6) PL internal supply voltage 0.97 1.00 1.03 V
PL -2LI (0.95V) internal supply voltage 0.93 0.95 0.97 V
VCCBRAM(6) PL block RAM supply voltage 0.97 1.00 1.03 V
PL -2LI (0.95V) block RAM supply voltage 0.93 0.95 0.97 V
VCCAUX PL auxiliary supply voltage 1.71 1.80 1.89 V
VCCO(7)(8) PL supply voltage for HR I/O banks 1.14 3.465 V
PL supply voltage for HP I/O banks 1.14 1.89 V
VCCAUX_IO(9) PL auxiliary supply voltage when set to 1.8V 1.71 1.80 1.89 V
PL auxiliary supply voltage when set to 2.0V 1.94 2.00 2.06 V
VIN(5)
I/O input voltage –0.20 VCCO +0.20 V
I/O input voltage (when VCCO = 3.3V) for VREF and differential
I/O standards except TMDS_33(10) –0.20 – 2.625 V
IIN(11) Maximum current through any (PS or PL) pin in a powered or
unpowered bank when forward biasing the clamp diode –– 10 mA
VCCBATT(12) Battery voltage 1.0 1.89 V
GTX Transceiver
VMGTAVCC(13)
Analog supply voltage for the GTX transceiver QPLL frequency
range 10.3125 GHz(14)(15) 0.97 1.0 1.08 V
Analog supply voltage for the GTX transceiver QPLL frequency
range > 10.3125 GHz 1.02 1.05 1.08
VMGTAVTT(13) Analog supply voltage for the GTX transmitter and receiver
termination circuits 1.17 1.2 1.23 V
VMGTVCCAUX(13) Auxiliary analog QPLL voltage supply for the transceivers 1.75 1.80 1.85 V
VMGTAVTTRCAL(13) Analog supply voltage for the resistor calibration circuit of the
GTX transceiver column 1.17 1.2 1.23 V
XADC
VCCADC XADC supply relative to GNDADC 1.71 1.80 1.89 V
VREFP Externally supplied reference voltage 1.20 1.25 1.30 V
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Product Specification 4
Temperature
Tj
Junction temperature operating range for commercial (C)
temperature devices 0– 85 °C
Junction temperature operating range for extended (E)
temperature devices 0– 100 °C
Junction temperature operating range for industrial (I)
temperature devices –40 – 100 °C
Junction temperature operating range for expanded (Q)
temperature devices –40 – 125 °C
Notes:
1. All voltages are relative to ground. The PL and PS share a common ground.
2. For the design of the power distribution system consult the Zynq-7000 SoC PCB Design Guide (UG933).
3. When the processor cores operate FCPU_6X4X_621_MAX at 1 GHz (-3E speed grade) or when the DDR interface operates at 1333 Mb/s, the
VCCPINT minimum is 0.97V and the VCCPINT maximum is 1.03V.
4. Applies to both MIO supply banks VCCO_MIO0 and VCCO_MIO1.
5. The lower absolute voltage specification always applies.
6. VCCINT and VCCBRAM should be connected to the same supply.
7. Configuration data is retained even if VCCO drops to 0V.
8. Includes VCCO of 1.2V, 1.35V, 1.5V, 1.8V, 2.5V (HR I/O only), and 3.3V (HR I/O only) at ±5%.
9. For more information, refer to the VCCAUX_IO section of the 7 Series FPGAs SelectIO Resources User Guide (UG471) or the Zynq-7000 SoC
Technical Reference Manual (UG585).
10. See Table 12 for TMDS_33 specifications.
11. A total of 200 mA per PS or PL bank should not be exceeded.
12. VCCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX.
13. Each voltage listed requires the filter circuit described in the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476).
14. For data rates 10.3125 Gb/s, VMGTAVCC should be 1.0V ±3% for lower power consumption.
15. For lower power consumption, VMGTAVCC should be 1.0V ±3% over the entire CPLL frequency range.
Table 2: Recommended Operating Conditions (1)(2) (Cont’d)
Symbol Description Min Typ Max Units
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Product Specification 5
Table 3: DC Characteristics Over Recommended Operating Conditions
Symbol Description Min Typ(1) Max Units
VDRINT Data retention VCCINT voltage (below which configuration data might be lost) 0.75 V
VDRI Data retention VCCAUX voltage (below which configuration data might be lost) 1.5 V
IREF PS_DDR_VREF 0/1, PS_MIO_VREF, and VREF leakage current per pin 15 µA
ILInput or output leakage current per pin (sample-tested) 15 µA
CIN(2) PL die input capacitance at the pad 8 pF
CPIN(2) PS die input capacitance at the pad 8 pF
IRPU
Pad pull-up (when selected) @ VIN =0V, V
CCO =3.3V 90 330 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO =2.5V 68 250 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO =1.8V 34 220 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO =1.5V 23 150 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO =1.2V 12 120 µA
IRPD
Pad pull-down (when selected) @ VIN =3.3V 68 330 µA
Pad pull-down (when selected) @ VIN =1.8V 45 180 µA
ICCADC Analog supply current, analog circuits in powered up state 25 mA
IBATT(3) Battery supply current 150 nA
RIN_TERM(4)
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_40) 28 40 55 Ω
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_50) 35 50 65 Ω
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_60) 44 60 83 Ω
n Temperature diode ideality factor 1.010
r Temperature diode series resistance 2 Ω
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. This measurement represents the die capacitance at the pad, not including the package.
3. Maximum value specified for worst case process at 25°C.
4. Termination resistance to a VCCO/2 level.
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Product Specification 6
Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for PS I/O and PL HR I/O Banks(1)(2)
AC Voltage Overshoot % of UI @–40°C to 125°C AC Voltage Undershoot % of UI @–40°C to 125°C
VCCO + 0.55 100
–0.40 100
–0.45 61.7
–0.50 25.8
–0.55 11.0
VCCO + 0.60 46.6 –0.60 4.77
VCCO + 0.65 21.2 –0.65 2.10
VCCO + 0.70 9.75 –0.70 0.94
VCCO + 0.75 4.55 –0.75 0.43
VCCO + 0.80 2.15 –0.80 0.20
VCCO + 0.85 1.02 –0.85 0.09
VCCO + 0.90 0.49 –0.90 0.04
VCCO + 0.95 0.24 –0.95 0.02
Notes:
1. A total of 200 mA per bank should not be exceeded.
2. The peak voltage of the overshoot or undershoot, and the duration above VCCO + 0.20V or below GND 0.20V, must not exceed the values
in this table.
Table 5: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for PL HP I/O Banks(1)(2)
AC Voltage Overshoot % of UI at –40°C to 125°C AC Voltage Undershoot % of UI at –40°C to 125°C
VCCO + 0.55 100 –0.55 100
VCCO + 0.60 50.0(3) –0.60 50.0(3)
VCCO + 0.65 50.0(3) –0.65 50.0(3)
VCCO + 0.70 47.0 –0.70 50.0(3)
VCCO + 0.75 21.2 –0.75 50.0(3)
VCCO + 0.80 9.71 –0.80 50.0(3)
VCCO + 0.85 4.51 –0.85 28.4
VCCO + 0.90 2.12 –0.90 12.7
VCCO + 0.95 1.01 –0.95 5.79
Notes:
1. A total of 200 mA per bank should not be exceeded.
2. The peak voltage of the overshoot or undershoot, and the duration above VCCO + 0.20V or below GND 0.20V, must not exceed the values
in this table.
3. For UI lasting less than 20 µs.
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Product Specification 7
Table 6: Typical Quiescent Supply Current
Symbol Description Device Speed Grade Units
-3E -2E -2I -2LI -1C -1I -1Q -1LQ
ICCPINTQ PS quiescent VCCPINT supply
current
XC7Z030 122 122 122 79 122 122 N/A N/A mA
XC7Z035 122 122 122 79 122 122 N/A N/A mA
XC7Z045 122 122 122 79 122 122 N/A N/A mA
XC7Z100 N/A N/A 122 79 N/A 122 N/A N/A mA
XA7Z030 N/A N/A N/A N/A N/A 122 122 N/A mA
XQ7Z030 N/A N/A 122 79 N/A 122 122 N/A mA
XQ7Z045 N/A N/A 122 79 N/A 122 122 122 mA
XQ7Z100 N/A N/A 122 79 N/A 122 N/A N/A mA
ICCPAUXQ PS quiescent VCCPAUX supply
current
XC7Z030131313111313N/AN/AmA
XC7Z035131313111313N/AN/AmA
XC7Z045131313111313N/AN/AmA
XC7Z100 N/A N/A 13 11 N/A 13 N/A N/A mA
XA7Z030 N/A N/A N/A N/A N/A 13 13 N/A mA
XQ7Z030 N/A N/A 13 11 N/A 13 13 N/A mA
XQ7Z045 N/A N/A 13 11 N/A 13 13 13 mA
XQ7Z100 N/A N/A 13 11 N/A 13 N/A N/A mA
ICCDDRQ PS quiescent VCCO_DDR supply
current
XC7Z030444444N/AN/AmA
XC7Z035444444N/AN/AmA
XC7Z045444444N/AN/AmA
XC7Z100 N/A N/A 4 4 N/A 4 N/A N/A mA
XA7Z030 N/A N/A N/A N/A N/A 4 4 N/A mA
XQ7Z030 N/A N/A 4 4 N/A 4 4 N/A mA
XQ7Z045 N/A N/A 4 4 N/A 4 4 4 mA
XQ7Z100 N/A N/A 4 4 N/A 4 N/A N/A mA
ICCINTQ PL quiescent VCCINT supply
current
XC7Z030 246 246 246 141 246 246 N/A N/A mA
XC7Z035 611 611 611 351 611 611 N/A N/A mA
XC7Z045 611 611 611 351 611 611 N/A N/A mA
XC7Z100 N/A N/A 795 457 N/A 795 N/A N/A mA
XA7Z030 N/A N/A N/A N/A N/A 246 246 N/A mA
XQ7Z030 N/A N/A 246 141 N/A 246 246 N/A mA
XQ7Z045 N/A N/A 611 351 N/A 611 611 611 mA
XQ7Z100 N/A N/A 795 457 N/A 795 N/A N/A mA
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Product Specification 8
ICCAUXQ PL quiescent VCCAUX supply
current
XC7Z030565656505656N/AN/AmA
XC7Z035 131 131 131 117 131 131 N/A N/A mA
XC7Z045 131 131 131 117 131 131 N/A N/A mA
XC7Z100 N/A N/A 165 148 N/A 165 N/A N/A mA
XA7Z030 N/A N/A N/A N/A N/A 56 56 N/A mA
XQ7Z030 N/A N/A 56 50 N/A 56 56 N/A mA
XQ7Z045 N/A N/A 131 117 N/A 131 131 131 mA
XQ7Z100 N/A N/A 165 148 N/A 165 N/A N/A mA
ICCAUX_IOQ PL quiescent VCCAUX_IO supply
current
XC7Z030222122N/AN/AmA
XC7Z035222122N/AN/AmA
XC7Z045222122N/AN/AmA
XC7Z100 N/A N/A 2 1 N/A 2 N/A N/A mA
XA7Z030 N/A N/A N/A N/A N/A 2 2 N/A mA
XQ7Z030 N/A N/A 2 1 N/A 2 2 N/A mA
XQ7Z045 N/A N/A 2 1 N/A 2 2 2 mA
XQ7Z100 N/A N/A 2 1 N/A 2 N/A N/A mA
ICCOQ PL quiescent VCCO supply
current
XC7Z030444444N/AN/AmA
XC7Z035444444N/AN/AmA
XC7Z045444444N/AN/AmA
XC7Z100 N/A N/A 4 4 N/A 4 N/A N/A mA
XA7Z030 N/A N/A N/A N/A N/A 4 4 N/A mA
XQ7Z030 N/A N/A 4 4 N/A 4 4 N/A mA
XQ7Z045 N/A N/A 4 4 N/A 4 4 4 mA
XQ7Z100 N/A N/A 4 4 N/A 4 N/A N/A mA
ICCBRAMQ PL quiescent VCCBRAM supply
current
XC7Z030111111 6 1111N/AN/AmA
XC7Z035232323132323N/AN/AmA
XC7Z045232323132323N/AN/AmA
XC7Z100 N/A N/A 33 19 N/A 33 N/A N/A mA
XA7Z030 N/A N/A N/A N/A N/A 11 11 N/A mA
XQ7Z030 N/A N/A 11 6 N/A 11 11 N/A mA
XQ7Z045 N/A N/A 23 13 N/A 23 23 23 mA
XQ7Z100 N/A N/A 33 19 N/A 33 N/A N/A mA
Notes:
1. Typical values are specified at nominal voltage, 85°C junction temperatures (Tj) with single-ended SelectIO resources.
2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and
floating.
3. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to estimate static power consumption for
conditions other than those specified.
Table 6: Typical Quiescent Supply Current (Cont’d)
Symbol Description Device Speed Grade Units
-3E -2E -2I -2LI -1C -1I -1Q -1LQ
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Product Specification 9
PS Power-On/Off Power Supply Sequencing
The recommended power-on sequence is VCCPINT, then VCCPAUX and VCCPLL together, then the PS VCCO supplies
(VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-
on. The PS_POR_B input is required to be asserted to GND during the power-on sequence until VCCPINT, VCCPAUX and
VCCO_MIO0 have reached minimum operating levels to ensure PS eFUSE integrity. For additional information about
PS_POR_B timing requirements refer to Resets.
The recommended power-off sequence is the reverse of the power-on sequence. If VCCPAUX, VCCPLL, and the PS VCCO
supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) have the same recommended voltage levels, then they can be powered
by the same supply and ramped simultaneously. Xilinx recommends powering VCCPLL with the same supply as VCCPAUX,
with an optional ferrite bead filter. Before VCCPINT reaches 0.80V at least one of the four following conditions is required
during the power-off stage: the PS_POR_B input is asserted to GND, the reference clock to the PS_CLK input is disabled,
VCCPAUX is lower than 0.70V, or VCCO_MIO0 is lower than 0.90V. The condition must be held until VCCPINT reaches 0.40V to
ensure PS eFUSE integrity.
For VCCO_MIO0 and VCCO_MIO1 voltages of 3.3V:
The voltage difference between VCCO_MIO0 /VCCO_MIO1 and VCCPAUX must not exceed 2.625V for longer than
TVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels.
•The T
VCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.
PL Power-On/Off Power Supply Sequencing
The recommended power-on sequence for the PL is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO to achieve minimum
current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the
power-on sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the
same supply and ramped simultaneously. If VCCAUX, VCCAUX_IO, and VCCO have the same recommended voltage levels
then they can be powered by the same supply and ramped simultaneously.
For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0:
The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each
power-on/off cycle to maintain device reliability levels.
•The T
VCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.
The recommended power-on sequence to achieve minimum current draw for the GTX transceivers is VCCINT, VMGTAVCC,
VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. There is no recommended sequencing for VMGTVCCAUX. Both VMGTAVCC and
VCCINT can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to
achieve minimum current draw.
If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during
power-up and power-down.
When VMGTAVTT is powered before VMGTAVCC and VMGTAVTT –V
MGTAVCC > 150 mV and VMGTAVCC < 0.7V, the
VMGTAVTT current draw can increase by 460 mA per transceiver during VMGTAVCC ramp up. The duration of the current
draw can be up to 0.3 x TMGTAVCC (ramp time from GND to 90% of VMGTAVCC). The reverse is true for power-down.
When VMGTAVTT is powered before VCCINT and VMGTAVTT –V
CCINT > 150 mV and VCCINT <0.7V, the V
MGTAVTT current
draw can increase by 50 mA per transceiver during VCCINT ramp up. The duration of the current draw can be up to
0.3 x TVCCINT (ramp time from GND to 90% of VCCINT). The reverse is true for power-down.
There is no recommended sequence for supplies not shown.
PS—PL Power Sequencing
The PS and PL power supplies are fully independent. PS power supplies (VCCPINT, VCCPAUX, VCCPLL, VCCO_DDR,
VCCO_MIO0, and VCCO_MIO1) can be powered before or after any PL power supplies. The PS and PL power regions are
isolated to prevent damage.
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Product Specification 10
Power Supply Requirements
Table 7 shows the minimum current, in addition to ICCQ, that is required by Zynq-7000 devices for proper power-on and
configuration. If the current minimums shown in Table 6 and Table 7 are met, the device powers on after all five supplies have
passed through their power-on reset threshold voltages. The Zynq-7000 device must not be configured until after VCCINT is
applied. Once initialized and configured, use the Xilinx Power Estimator (XPE) spreadsheet tool (download at
www.xilinx.com/power) to estimate current drain on these supplies.
Table 7: Power-On Current for Zynq-7000 Devices
Device ICCPINTMIN ICCPAUXMIN ICCDDRMIN ICCINTMIN ICCAUXMIN ICCOMIN ICCAUX_IOMIN ICCBRAMMIN Units
XC7Z030 ICCPINTQ +
70 mA
ICCPAUXQ +
40 mA
ICCDDRQ +
130 mA
per bank
ICCINTQ +
900 mA
ICCAUXQ +
60 mA
ICCOQ +
90 mA
per bank
ICCOAUXIOQ +
40 mA
per bank
ICCBRAMQ +
90 mA mA
XC7Z035 ICCPINTQ +
70 mA
ICCPAUXQ +
40 mA
ICCDDRQ +
130 mA
per bank
ICCINTQ +
1400 mA
ICCAUXQ +
60 mA
ICCOQ +
90 mA
per bank
ICCOAUXIOQ +
40 mA
per bank
ICCBRAMQ +
90 mA mA
XC7Z045 ICCPINTQ +
70 mA
ICCPAUXQ +
40 mA
ICCDDRQ +
130 mA
per bank
ICCINTQ +
1400 mA
ICCAUXQ +
60 mA
ICCOQ +
90 mA
per bank
ICCOAUXIOQ +
40 mA
per bank
ICCBRAMQ +
90 mA mA
XC7Z100 ICCPINTQ +
70 mA
ICCPAUXQ +
40 mA
ICCDDRQ +
130 mA
per bank
ICCINTQ +
2200 mA
ICCAUXQ +
60 mA
ICCOQ +
90 mA
per bank
ICCOAUXIOQ +
40 mA
per bank
ICCBRAMQ +
90 mA mA
XA7Z030 ICCPINTQ +
70 mA
ICCPAUXQ +
40 mA
ICCDDRQ +
130 mA
per bank
ICCINTQ +
900 mA
ICCAUXQ +
60 mA
ICCOQ +
90 mA
per bank
ICCOAUXIOQ +
40 mA
per bank
ICCBRAMQ +
90 mA mA
XQ7Z030 ICCPINTQ +
70 mA
ICCPAUXQ +
40 mA
ICCDDRQ +
130 mA
per bank
ICCINTQ +
900 mA
ICCAUXQ +
60 mA
ICCOQ +
90 mA
per bank
ICCOAUXIOQ +
40 mA
per bank
ICCBRAMQ +
90 mA mA
XQ7Z045 ICCPINTQ +
70 mA
ICCPAUXQ +
40 mA
ICCDDRQ +
130 mA
per bank
ICCINTQ +
1400 mA
ICCAUXQ +
60 mA
ICCOQ +
90 mA
per bank
ICCOAUXIOQ +
40 mA
per bank
ICCBRAMQ +
90 mA mA
XQ7Z100 ICCPINTQ +
70 mA
ICCPAUXQ +
40 mA
ICCDDRQ +
130 mA
per bank
ICCINTQ +
2200 mA
ICCAUXQ +
60 mA
ICCOQ +
90 mA
per bank
ICCOAUXIOQ +
40 mA
per bank
ICCBRAMQ +
90 mA mA
Table 8: Power Supply Ramp Time
Symbol Description Conditions Min Max Units
TVCCPINT Ramp time from GND to 90% of VCCPINT 0.2 50 ms
TVCCPAUX Ramp time from GND to 90% of VCCPAUX 0.2 50 ms
TVCCO_DDR Ramp time from GND to 90% of VCCO_DDR 0.2 50 ms
TVCCO_MIO Ramp time from GND to 90% of VCCO_MIO 0.2 50 ms
TVCCINT Ramp time from GND to 90% of VCCINT 0.2 50 ms
TVCCO Ramp time from GND to 90% of VCCO 0.2 50 ms
TVCCAUX Ramp time from GND to 90% of VCCAUX 0.2 50 ms
TVCCAUX_IO Ramp time from GND to 90% of VCCAUX_IO 0.2 50 ms
TVCCBRAM Ramp time from GND to 90% of VCCBRAM 0.2 50 ms
TVCCO2VCCAUX
Allowed time per power cycle for VCCO –V
CCAUX > 2.625V
and VCCO_MIO –V
CCPAUX > 2.625V
TJ = 125°C(1) –300 ms
TJ = 100°C(1) –500 ms
TJ = 85°C(1) –800 ms
TMGTAVCC Ramp time from GND to 90% of VMGTAVCC 0.2 50 ms
TMGTAVTT Ramp time from GND to 90% of VMGTAVTT 0.2 50 ms
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Product Specification 11
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended
operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that
all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and
VOH voltage levels shown. Other standards are sample tested.
PS I/O Levels
TMGTVCCAUX Ramp time from GND to 90% of VMGTVCCAUX 0.2 50 ms
Notes:
1. Based on 240,000 power cycles with nominal VCCO of 3.3V or 36,500 power cycles with a worst case VCCO of 3.465V.
Table 9: PS DC Input and Output Levels(1)
Bank I/O
Standard
VIL VIH VOL VOH IOL IOH
V, Min V, Max V, Min V, Max V, Max V, Min mA mA
MIO LVCMOS18 –0.300 35% VCCO_MIO 65% VCCO_MIO VCCO_MIO + 0.300 0.450 VCCO_MIO – 0.450 8 –8
MIO LVCMOS25 –0.300 0.700 1.700 VCCO_MIO + 0.300 0.400 VCCO_MIO – 0.400 8 –8
MIO LVCMOS33 –0.300 0.800 2.000 3.450 0.400 VCCO_MIO – 0.400 8 –8
MIO HSTL_I_18 –0.300 VPREF – 0.100 VPREF +0.100 V
CCO_MIO + 0.300 0.400 VCCO_MIO – 0.400 8 –8
DDR SSTL18_I –0.300 VPREF – 0.125 VPREF +0.125 V
CCO_DDR +0.300 V
CCO_DDR/2–0.470 V
CCO_DDR/2 + 0.470 8 –8
DDR SSTL15 –0.300 VPREF – 0.100 VPREF +0.100 V
CCO_DDR +0.300 V
CCO_DDR/2–0.175 V
CCO_DDR/2 + 0.175 13.0 –13.0
DDR SSTL135 –0.300 VPREF – 0.090 VPREF +0.090 V
CCO_DDR +0.300 V
CCO_DDR/2–0.150 V
CCO_DDR/2 + 0.150 13.0 –13.0
DDR HSUL_12 –0.300 VPREF – 0.130 VPREF +0.130 V
CCO_DDR + 0.300 20% VCCO_DDR 80% VCCO_DDR 0.1 –0.1
Notes:
1. Tested according to relevant specifications.
Table 10: PS Complementary Differential DC Input and Output Levels
Bank I/O Standard VICM(1) VID(2) VOL(3) VOH(4) IOL IOH
V, Min V,Typ V, Max V,Min V, Max V, Max V, Min mA, Max mA, Min
DDR DIFF_HSUL_12 0.300 0.600 0.850 0.100 20% VCCO 80% VCCO 0.100 –0.100
DDR DIFF_SSTL135 0.300 0.675 1.000 0.100 (VCCO_DDR/2) – 0.150 (VCCO_DDR/2) + 0.150 13.0 –13.0
DDR DIFF_SSTL15 0.300 0.750 1.125 0.100 (VCCO_DDR/2) – 0.175 (VCCO_DDR/2) + 0.175 13.0 –13.0
DDR DIFF_SSTL18_I 0.300 0.900 1.425 0.100 (VCCO_DDR/2) – 0.470 (VCCO_DDR/2) + 0.470 8.00 –8.00
Notes:
1. VICM is the input common mode voltage.
2. VID is the input differential voltage (Q–Q).
3. VOL is the single-ended low-output voltage.
4. VOH is the single-ended high-output voltage.
Table 8: Power Supply Ramp Time (Cont’d)
Symbol Description Conditions Min Max Units
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Product Specification 12
PL I/O Levels
Table 11: SelectIO DC Input and Output Levels(1)(2)
I/O Standard VIL VIH VOL VOH IOL IOH
V, Min V, Max V, Min V, Max V, Max V, Min mA mA
HSTL_I –0.300 VREF –0.100 V
REF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 8 –8
HSTL_I_12 –0.300 VREF –0.080 V
REF + 0.080 VCCO + 0.300 25% VCCO 75% VCCO 6.3 –6.3
HSTL_I_18 –0.300 VREF –0.100 V
REF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 8 –8
HSTL_II –0.300 VREF –0.100 V
REF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 16 –16
HSTL_II_18 –0.300 VREF –0.100 V
REF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 16 –16
HSUL_12 –0.300 VREF –0.130 V
REF + 0.130 VCCO + 0.300 20% VCCO 80% VCCO 0.1 –0.1
LVCMOS12 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.400 VCCO – 0.400 Note 3 Note 3
LVCMOS15,
LVDCI_15
–0.300 35% VCCO 65% VCCO VCCO + 0.300 25% VCCO 75% VCCO Note 4 Note 4
LVCMOS18,
LVDCI_18
–0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO – 0.450 Note 5 Note 5
LVCMOS25 –0.300 0.700 1.700 VCCO + 0.300 0.400 VCCO – 0.400 Note 6 Note 6
LVCMOS33 –0.300 0.800 2.000 3.450 0.400 VCCO – 0.400 Note 6 Note 6
LVTTL –0.300 0.800 2.000 3.450 0.400 2.400 Note 7 Note 7
MOBILE_DDR –0.300 20% VCCO 80% VCCO VCCO + 0.300 10% VCCO 90% VCCO 0.1 –0.1
PCI33_3 –0.400 30% VCCO 50% VCCO VCCO + 0.500 10% VCCO 90% VCCO 1.5 –0.5
SSTL12 –0.300 VREF –0.100 V
REF + 0.100 VCCO + 0.300 VCCO/2–0.150 V
CCO/2 + 0.150 14.25 –14.25
SSTL135 –0.300 VREF –0.090 V
REF + 0.090 VCCO + 0.300 VCCO/2–0.150 V
CCO/2 + 0.150 13.0 –13.0
SSTL135_R –0.300 VREF –0.090 V
REF + 0.090 VCCO + 0.300 VCCO/2–0.150 V
CCO/2 + 0.150 8.9 –8.9
SSTL15 –0.300 VREF –0.100 V
REF + 0.100 VCCO + 0.300 VCCO/2–0.175 V
CCO/2 + 0.175 13.0 –13.0
SSTL15_R –0.300 VREF –0.100 V
REF + 0.100 VCCO + 0.300 VCCO/2–0.175 V
CCO/2 + 0.175 8.9 –8.9
SSTL18_I –0.300 VREF –0.125 V
REF + 0.125 VCCO + 0.300 VCCO/2–0.470 V
CCO/2 + 0.470 8 –8
SSTL18_II –0.300 VREF –0.125 V
REF + 0.125 VCCO + 0.300 VCCO/2–0.600 V
CCO/2 + 0.600 13.4 –13.4
Notes:
1. Tested according to relevant specifications.
2. 3.3V and 2.5V standards are only supported in HR I/O banks.
3. Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks and 4, 8, or 12 mA in HR I/O banks.
4. Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, or 16 mA in HR I/O banks.
5. Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, 16, or 24 mA in HR I/O banks.
6. Supported drive strengths of 4, 8, 12, or 16 mA
7. Supported drive strengths of 4, 8, 12, 16, or 24 mA
8. For detailed interface specific DC voltage levels, see the 7 Series FPGAs SelectIO Resources User Guide (UG471).
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Product Specification 13
Table 12: Differential SelectIO DC Input and Output Levels
I/O Standard VICM(1) VID(2) VOCM(3) VOD(4)
V, Min V, Typ V, Max V, Min V, Typ V, Max V, Min V, Typ V, Max V, Min V, Typ V, Max
BLVDS_25 0.300 1.200 1.425 0.100 1.250 Note 5
MINI_LVDS_25 0.300 1.200 VCCAUX 0.200 0.400 0.600 1.000 1.200 1.400 0.300 0.450 0.600
PPDS_25 0.200 0.900 VCCAUX 0.100 0.250 0.400 0.500 0.950 1.400 0.100 0.250 0.400
RSDS_25 0.300 0.900 1.500 0.100 0.350 0.600 1.000 1.200 1.400 0.100 0.350 0.600
TMDS_33 2.700 2.965 3.230 0.150 0.675 1.200 VCCO–0.405 VCCO–0.300 VCCO–0.190 0.400 0.600 0.800
Notes:
1. VICM is the input common mode voltage.
2. VID is the input differential voltage (Q – Q).
3. VOCM is the output common mode voltage.
4. VOD is the output differential voltage (Q – Q).
5. VOD for BLVDS will vary significantly depending on topology and loading.
6. LVDS_25 is specified in Table 14.
7. LVDS is specified in Table 15.
Table 13: Complementary Differential SelectIO DC Input and Output Levels
I/O Standard
VICM(1) VID(2) VOL(3) VOH(4) IOL IOH
V, Min V, Typ V, Max V,
Min V, Max V, Max V, Min mA, Max mA, Min
DIFF_HSTL_I 0.300 0.750 1.125 0.100 0.400 VCCO–0.400 8.00 –8.00
DIFF_HSTL_I_18 0.300 0.900 1.425 0.100 0.400 VCCO–0.400 8.00 –8.00
DIFF_HSTL_II 0.300 0.750 1.125 0.100 0.400 VCCO–0.400 16.00 –16.00
DIFF_HSTL_II_18 0.300 0.900 1.425 0.100 0.400 VCCO–0.400 16.00 –16.00
DIFF_HSUL_12 0.300 0.600 0.850 0.100 20% VCCO 80% VCCO 0.100 –0.100
DIFF_MOBILE_DDR 0.300 0.900 1.425 0.100 10% VCCO 90% VCCO 0.100 –0.100
DIFF_SSTL12 0.300 0.600 0.850 0.100 (VCCO/2) – 0.150 (VCCO/2) + 0.150 14.25 –14.25
DIFF_SSTL135 0.300 0.675 1.000 0.100 (VCCO/2) – 0.150 (VCCO/2) + 0.150 13.0 –13.0
DIFF_SSTL135_R 0.300 0.675 1.000 0.100 (VCCO/2) – 0.150 (VCCO/2) + 0.150 8.9 8.9
DIFF_SSTL15 0.300 0.750 1.125 0.100 (VCCO/2) – 0.175 (VCCO/2) + 0.175 13.0 –13.0
DIFF_SSTL15_R 0.300 0.750 1.125 0.100 (VCCO/2) – 0.175 (VCCO/2) + 0.175 8.9 8.9
DIFF_SSTL18_I 0.300 0.900 1.425 0.100 (VCCO/2) – 0.470 (VCCO/2) + 0.470 8.00 –8.00
DIFF_SSTL18_II 0.300 0.900 1.425 0.100 (VCCO/2) – 0.600 (VCCO/2) + 0.600 13.4 –13.4
Notes:
1. VICM is the input common mode voltage.
2. VID is the input differential voltage (Q – Q).
3. VOL is the single-ended low-output voltage.
4. VOH is the single-ended high-output voltage.
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Product Specification 14
LVDS DC Specifications (LVDS_25)
The LVDS_25 standard is available in the HR I/O banks.
LVDS DC Specifications (LVDS)
The LVDS standard is available in the HP I/O banks.
Table 14: LVDS_25 DC Specifications(1)
Symbol DC Parameter Conditions Min Typ Max Units
VCCO Supply Voltage 2.375 2.500 2.625 V
VOH Output High Voltage for Q and Q RT = 100 Ω across Q and Q signals 1.675 V
VOL Output Low Voltage for Q and Q RT = 100 Ω across Q and Q signals 0.700 V
VODIFF
Differential Output Voltage
(Q – Q), Q = High
(Q –Q), Q=High
RT = 100 Ω across Q and Q signals
247 350 600 mV
VOCM Output Common-Mode Voltage RT = 100 Ω across Q and Q signals 1.000 1.250 1.425 V
VIDIFF
Differential Input Voltage
(Q – Q), Q = High
(Q –Q), Q=High
100 350 600 mV
VICM Input Common-Mode Voltage 0.300 1.200 1.500 V
Notes:
1. Differential inputs for LVDS_25 can be placed in banks with VCCO levels that are different from the required level for outputs. Consult the
7 Series FPGAs SelectIO Resources User Guide (UG471) for more information.
Table 15: LVDS DC Specifications(1)
Symbol DC Parameter Conditions Min Typ Max Units
VCCO Supply Voltage 1.710 1.800 1.890 V
VOH Output High Voltage for Q and Q RT = 100 Ω across Q and Q signals 1.675 V
VOL Output Low Voltage for Q and Q RT = 100 Ω across Q and Q signals 0.825 V
VODIFF
Differential Output Voltage
(Q – Q), Q = High
(Q –Q), Q=High
RT = 100 Ω across Q and Q signals 247 350 600 mV
VOCM Output Common-Mode Voltage RT = 100 Ω across Q and Q signals 1.000 1.250 1.425 V
VIDIFF
Differential Input Voltage
(Q – Q), Q = High
(Q –Q), Q=High
Common-mode input voltage = 1.25V 100 350 600 mV
VICM Input Common-Mode Voltage Differential input voltage = ±350 mV 0.300 1.200 1.425 V
Notes:
1. Differential inputs for LVDS can be placed in banks with VCCO levels that are different from the required level for outputs. Consult the 7Series
FPGAs SelectIO Resources User Guide (UG471) for more information.
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Product Specification 15
AC Switching Characteristics
All values represented in this data sheet are based on the speed specifications in the ISE® Design Suite 14.7 and
Vivado® Design Suite 2015.4 as outlined in Table 16.
Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or
Production. Each designation is defined as follows:
Advance Product Specification
These specifications are based on simulations only and are typically available soon after device design specifications are
frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-
reporting might still occur.
Preliminary Product Specification
These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades
with this designation are intended to give a better indication of the expected performance of production silicon. The
probability of under-reporting delays is greatly reduced as compared to Advance data.
Production Product Specification
These specifications are released once enough production silicon of a particular device family member has been
characterized to provide full correlation between specifications and devices over numerous production lots. There is no
under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest
speed grades transition to Production before faster speed grades.
Testing of AC Switching Characteristics
Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are
representative of worst-case supply voltage and junction temperature conditions.
For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and
back-annotate to the simulation net list. Unless otherwise noted, values apply to all Zynq-7000 devices.
Speed Grade Designations
Since individual family members are produced at different times, the migration from one category to another depends
completely on the status of the fabrication process for each device. Table 17 correlates the current status of each Zynq-7000
device on a per speed grade basis.
Table 16: Zynq-7000 SoC Speed Specification Version By Device
ISE 14.7 Vivado 2015.4 Device
1.08 1.11 XC7Z030 and XC7Z045
N/A 1.11 XC7Z035 and XC7Z100
N/A 1.09 XA7Z030
1.06 1.10 XQ7Z030 and XQ7Z045
N/A 1.10 XQ7Z100
Table 17: Zynq-7000 Device Speed Grade Designations
Device Speed Grade Designations
Advance Preliminary Production
XC7Z030 -3, -2, -2LI, -1
XC7Z035 -3, -2, -2LI, -1
XC7Z045 -3, -2, -2LI, -1
XC7Z100 -2, -2LI, -1
XA7Z030 -1I, -1Q
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Product Specification 16
Production Silicon and Software Status
In some cases, a particular family member (and speed grade) is released to production before a speed specification is
released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent
speed specification releases.
Table 18 lists the production released Zynq-7000 device, speed grade, and the minimum corresponding supported speed
specification version and software revisions. The software and speed specifications listed are the minimum releases
required for production. All subsequent releases of software and speed specifications are valid.
Selecting the Correct Speed Grade and Voltage in the Vivado Tools
It is important to select the correct device speed grade and voltage in the Vivado tools for the device that you are selecting.
To select the -3, -2, or -1 (PL 1.0V) speed specifications in the Vivado tools, select the Zynq-7000, XA Zynq-7000, or
Defense Grade Zynq-7000 sub-family, and then select the part name that is the device name followed by the package name
followed by the speed grade. For example, select the xc7z030fbg676-3 part name for the XC7Z030 device in the FBG676
package and -3 speed grade.
To select the -2LI (PL 0.95V) speed specifications in the Vivado tools, select the Zynq-7000 sub-family and then select the
part name that is the device name followed by an i followed by the package name followed by the speed grade. For example,
select the xc7z030ifbg676-2L part name for the XC7Z030 device in the FBG676 package and -2LI (PL 0.95V) speed grade.
The -2LI (PL 0.95V) speed specifications are not supported in the ISE tools.
A similar part naming convention applies to the speed specifications selection in the ISE tools for supported devices. See
Table 18 for the subset of Zynq-7000 devices supported in the ISE tools.
XQ7Z030 -2I, -2LI, -1I, -1Q
XQ7Z045 -2I, -2LI, -1I, -1Q, -1LQ
XQ7Z100 -2I, -2LI, -1I
Table 18: Zynq-7000 Device Production Software and Speed Specification Release
Device Speed Grade Designations
-3E -2E -2I -2LI -1C -1I -1Q -1LQ
XC7Z030 ISE tools 14.5 v1.06 and
Vivado tools 2013.1 v1.06
Vivado tools
2014.4 v1.11
ISE tools 14.5 v1.06 and
Vivado tools 2013.1 v1.06
N/A N/A
XC7Z035 Vivado tools 2014.4 v1.11 N/A N/A
XC7Z045 ISE tools 14.5 v1.06 and
Vivado tools 2013.1 v1.06
Vivado tools
2014.4 v1.11
ISE tools 14.5 v1.06 and
Vivado tools 2013.1 v1.06
N/A N/A
XC7Z100 N/A N/A Vivado tools 2013.2 v1.07 Vivado tools
2014.4 v1.11
N/A Vivado tools
2013.2 v1.07
N/A N/A
XA7Z030 N/A N/A N/A N/A N/A Vivado tools 2014.2 v1.08 N/A
XQ7Z030 N/A N/A ISE tools 14.7 v1.06 and
Vivado tools 2013.3 v1.06
Vivado tools
2015.4 v1.10
N/A ISE tools 14.7 v1.06 and Vivado
tools 2013.3 v1.06
N/A
XQ7Z045 N/A N/A N/A Vivado tools
2015.2 v1.09
XQ7Z100 N/A N/A Vivado tools 2015.4 v1.10 N/A Vivado tools
2015.2 v1.09
N/A N/A
Table 17: Zynq-7000 Device Speed Grade Designations (Cont’d)
Device Speed Grade Designations
Advance Preliminary Production
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Product Specification 17
PS Performance Characteristics
For further design requirement details, refer to the Zynq-7000 SoC Technical Reference Manual (UG585).
Table 19: CPU Clock Domains Performance
Symbol Clock
Ratio Description Speed Grade Units
-3E -2E/-2I/-2LI -1C/-1I -1Q/-1LQ
FCPU_6X4X_621_MAX(1)(2)
6:2:1
Maximum CPU clock frequency 1000 800 667 667 MHz
FCPU_3X2X_621_MAX Maximum CPU_3X clock frequency 500 400 333 333 MHz
FCPU_2X_621_MAX Maximum CPU_2X clock frequency 333 266 222 222 MHz
FCPU_1X_621_MAX Maximum CPU_1X clock frequency 167 133 111 111 MHz
FCPU_6X4X_421_MAX(1)
4:2:1
Maximum CPU clock frequency 710 600 533 533 MHz
FCPU_3X2X_421_MAX Maximum CPU_3X clock frequency 355 300 267 267 MHz
FCPU_2X_421_MAX Maximum CPU_2X clock frequency 355 300 267 267 MHz
FCPU_1X_421_MAX Maximum CPU_1X clock frequency 178 150 133 133 MHz
Notes:
1. The maximum frequency during BootROM execution is 500 MHz across all speed specifications.
2. When the processor cores operate FCPU_6X4X_621_MAX at 1 GHz (-3E speed grade), the VCCPINT minimum is 0.97V and the VCCPINT
maximum is 1.03V.
Table 20: PS DDR Clock Domains Performance(1)
Symbol Description Speed Grade Units
-3E -2E/-2I/-2LI -1C/-1I -1Q/-1LQ
FDDR3_MAX Maximum DDR3 interface performance 1333(2) 1066 1066 1066 Mb/s
FDDR3L_MAX Maximum DDR3L interface performance 1066 1066 1066 1066 Mb/s
FDDR2_MAX Maximum DDR2 interface performance 800 800 800 800 Mb/s
FLPDDR2_MAX Maximum LPDDR2 interface performance 800 800 800 800 Mb/s
FDDRCLK_2XMAX Maximum DDR_2X clock frequency 444 408 355 355 MHz
Notes:
1. All performance numbers apply to both internal and external VREF configurations.
2. When a DDR interface operates at 1333 Mb/s, the VCCPINT minimum is 0.97V and the VCCPINT maximum is 1.03V.
Table 21: PS-PL Interface Performance
Symbol Description Min Max Units
FEMIOGEMCLK EMIO gigabit Ethernet controller maximum frequency 125 MHz
FEMIOSDCLK EMIO SD controller maximum frequency 25 MHz
FEMIOSPICLK EMIO SPI controller maximum frequency 25 MHz
FEMIOJTAGCLK EMIO JTAG controller maximum frequency 20 MHz
FEMIOTRACECLK EMIO trace controller maximum frequency 125 MHz
FFTMCLK Fabric trace monitor maximum frequency 125 MHz
FEMIODMACLK DMA maximum frequency 100 MHz
FAXI_MAX Maximum AXI interface performance 250 MHz
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Product Specification 18
PS Switching Characteristics
Clocks
Resets
The PS_POR_B deassertion must meet the following requirements to avoid coinciding with the secure lockdown window.
Figure 1 shows the timing relationship between PS_POR_B and the last power supply ramp (VCCINT, VCCBRAM, VCCAUX, or
VCCO in bank 0). TSLW minimum and maximum parameters define the beginning and end, respectively, of the secure
lockdown window relative to the last PL power supply reaching 250 mV. The PS_POR_B must not be deasserted within the
secure lockdown window.
Table 22: System Reference Clock Input Requirements
Symbol Description Min Typ Max Units
TJTPSCLK PS_CLK RMS clock jitter tolerance ±0.5 %
TDCPSCLK PS_CLK duty cycle 40 60 %
TRFPSCLK PS_CLK rise and fall time 6 ns
FPSCLK PS_CLK frequency 30 60 MHz
Table 23: PS PLL Switching Characteristics
Symbol Description Speed Grade Units
-3E -2E/-2I/-2LI -1C/-1I -1Q/-1LQ
TLOCK_PSPLL PLL maximum lock time 60 60 60 60 µs
FPSPLL_MAX PLL maximum output frequency 2000 1800 1600 1600 MHz
FPSPLL_MIN PLL minimum output frequency 780 780 780 780 MHz
Table 24: PS Reset Assertion Timing Requirements
Symbol Description Min Typ Max Units
TPSPOR Required PS_POR_B assertion time(1) 100 – µs
TPSRST Required PS_SRST_B assertion time 3 PS_CLK Clock Cycles
Notes:
1. PS_POR_B needs to be asserted low until PS supply voltages reach minimum levels.
X-Ref Target - Figure 1
Figure 1: PS_POR_B and Power Supply Ramp Timing Requirements
PS_POR_B
Last Ramping PL Supply
Secure Lockdown Window
Do not deassert PS_POR_B
T
SLW(min)
T
SLW(max)
250 mV
DS191_21_022015
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Product Specification 19
PS Configuration
DDR Memory Interfaces
Table 25: PS Reset/Power Supply Timing Requirements
Symbol Description PS_CLK Frequency
(MHz) Min Max Units
TSLW(1) 128 KB CRC eFUSE disabled and PLL enabled.
Default configuration
30 12 39 ms
33.33 12 40 ms
60 13 40 ms
128 KB CRC eFUSE disabled and PLL in bypass. 30 –32 13 ms
33.33 –27 13 ms
60 –9 25 ms
128 KB CRC eFUSE enabled and PLL enabled.(2) 30 –19 9 ms
33.33 –16 12 ms
60 –3 25 ms
128 KB CRC eFUSE enabled and PLL in bypass.(2) 30 –830 –788 ms
33.33 –746 –705 ms
60 –408 –374 ms
Notes:
1. Valid for power supply ramp times of less than 6 ms. For ramp times longer than 6 ms, see the BootROM Performance section of the
Zynq-7000 SoC Technical Reference Manual (UG585).
2. If any PS and PL power supplies are tied together, observe the PS_POR_B assertion time requirement (TPSPOR) in Table 24 and its
accompanying note.
Table 26: Processor Configuration Access Port Switching Characteristics
Symbol Description Min Typ Max Units
FPCAPCK Maximum processor configuration access port (PCAP) frequency 100 MHz
Table 27: DDR3 Interface Switching Characteristics (1333 Mb/s)(1)
Symbol Description Min Max Units
TDQVALID(2) Input data valid window 450 ps
TDQDS(3) Output DQ to DQS skew 95 ps
TDQDH(4) Output DQS to DQ skew 222 ps
TDQSS Output clock to DQS skew –0.11 0.08 TCK
TCACK(5) Command/address output setup time with respect to CLK 465 ps
TCKCA(6) Command/address output hold time with respect to CLK 528 ps
Notes:
1. Recommended VCCO_DDR =1.55%.
2. Measurement is taken from VREF to VREF.
3. Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses
VIL(AC) to VREF of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
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Product Specification 20
Table 28: DDR3 Interface Switching Characteristics (1066 Mb/s)(1)
Symbol Description Min Max Units
TDQVALID(2) Input data valid window 450 ps
TDQDS(3) Output DQ to DQS skew 100 ps
TDQDH(4) Output DQS to DQ skew 350 ps
TDQSS Output clock to DQS skew –0.10 0.10 TCK
TCACK(5) Command/address output setup time with respect to CLK 560 ps
TCKCA(6) Command/address output hold time with respect to CLK 658 ps
Notes:
1. Recommended VCCO_DDR =1.55%.
2. Measurement is taken from VREF to VREF.
3. Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses
VIL(AC) to VREF of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
Table 29: DDR3L Interface Switching Characteristics (1066 Mb/s)(1)
Symbol Description Min Max Units
TDQVALID(2) Input data valid window 450 ps
TDQDS(3) Output DQ to DQS skew 189 ps
TDQDH(4) Output DQS to DQ skew 267 ps
TDQSS Output clock to DQS skew –0.13 0.04 TCK
TCACK(5) Command/address output setup time with respect to CLK 410 ps
TCKCA(6) Command/address output hold time with respect to CLK 629 ps
Notes:
1. Recommended VCCO_DDR = 1.35V ±5%.
2. Measurement is taken from VREF to VREF.
3. Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses
VIL(AC) to VREF of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
Table 30: DDR3L Interface Switching Characteristics (800 Mb/s)(1)
Symbol Description Min Max Units
TDQVALID(2) Input data valid window 500 ps
TDQDS(3) Output DQ to DQS skew 321 ps
TDQDH(4) Output DQS to DQ skew 380 ps
TDQSS Output clock to DQS skew –0.12 0.04 TCK
TCACK(5) Command/address output setup time with respect to CLK 636 ps
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Product Specification 21
TCKCA(6) Command/address output hold time with respect to CLK 853 ps
Notes:
1. Recommended VCCO_DDR = 1.35V ±5%.
2. Measurement is taken from VREF to VREF.
3. Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses
VIL(AC) to VREF of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
Table 31: LPDDR2 Interface Switching Characteristics (800 Mb/s)(1)
Symbol Description Min Max Units
TDQVALID(2) Input data valid window 500 ps
TDQDS(3) Output DQ to DQS skew 111 ps
TDQDH(4) Output DQS to DQ skew 318 ps
TDQSS Output clock to DQS skew 0.91 1.10 TCK
TCACK(5) Command/address output setup time with respect to CLK 132 ps
TCKCA(6) Command/address output hold time with respect to CLK 363 ps
Notes:
1. Recommended VCCO_DDR =1.25%.
2. Measurement is taken from VREF to VREF.
3. Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses VIL(AC)
to VREF of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
Table 32: LPDDR2 Interface Switching Characteristics (400 Mb/s)(1)
Symbol Description Min Max Units
TDQVALID(2) Input data valid window 500 ps
TDQDS(3) Output DQ to DQS skew 561 ps
TDQDH(4) Output DQS to DQ skew 852 ps
TDQSS Output clock to DQS skew 0.91 1.08 TCK
TCACK(5) Command/address output setup time with respect to CLK 617 ps
TCKCA(6) Command/address output hold time with respect to CLK 918 ps
Notes:
1. Recommended VCCO_DDR =1.25%.
2. Measurement is taken from VREF to VREF.
3. Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses VIL(AC)
to VREF of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
Table 30: DDR3L Interface Switching Characteristics (800 Mb/s)(1) (Cont’d)
Symbol Description Min Max Units
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Product Specification 22
Table 33: DDR2 Interface Switching Characteristics (800 Mb/s)(1)
Symbol Description Min Max Units
TDQVALID(2) Input data valid window 500 ps
TDQDS(3) Output DQ to DQS skew 147 ps
TDQDH(4) Output DQS to DQ skew 376 ps
TDQSS Output clock to DQS skew –0.07 0.08 TCK
TCACK(5) Command/address output setup time with respect to CLK 732 ps
TCKCA(6) Command/address output hold time with respect to CLK 938 ps
Notes:
1. Recommended VCCO_DDR =1.85%.
2. Measurement is taken from VREF to VREF.
3. Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses
VIL(AC) to VREF of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
Table 34: DDR2 Interface Switching Characteristics (400 Mb/s)(1)
Symbol Description Min Max Units
TDQVALID(2) Input data valid window 500 ps
TDQDS(3) Output DQ to DQS skew 385 ps
TDQDH(4) Output DQS to DQ skew 662 ps
TDQSS Output clock to DQS skew –0.11 0.06 TCK
TCACK(5) Command/address output setup time with respect to CLK 1760 ps
TCKCA(6) Command/address output hold time with respect to CLK 1739 ps
Notes:
1. Recommended VCCO_DDR =1.85%.
2. Measurement is taken from VREF to VREF.
3. Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses
VIL(AC) to VREF of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
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Product Specification 23
X-Ref Target - Figure 2
Figure 2: DDR Output Timing Diagram
X-Ref Target - Figure 3
Figure 3: DDR Input Timing Diagram
Write NOP NOP NOP NOP
Bank, Col n
D0 D1 D3
TDQDH
TDQDS
TDQDH
TDQDS
TDQSS
TCKCA
TCACK
TCKCA
TCACK
DS191_01_052714
CLK
CLK
Command
Address
DQS
DQS
DQ D2
D0 D1 D2 D3
T
DQVALID
CLK
CLK
DQS
DQS
DQ
DS191_02_052714
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Product Specification 24
Static Memory Controller
Table 35: SMC Interface Delay Characteristics(1)(2)
Symbol Description Min Max Units
TNANDDOUT NAND_IO output delay from last register to pad 4.12 6.45 ns
TNANDALE NAND_ALE output delay from last register to pad 5.08 6.33 ns
TNANDCLE NAND_CLE output delay from last register to pad 4.87 6.40 ns
TNANDWE NAND_WE_B output delay from last register to pad 4.69 5.89 ns
TNANDRE NAND_RE_B output delay from last register to pad 5.12 6.44 ns
TNANDCE NAND_CE_B output delay from last register to pad 4.68 5.89 ns
TNANDDIN NAND_IO setup time and input delay from pad to first register 1.48 3.09 ns
TNANDBUSY NAND_BUSY setup time and input delay from pad to first register 2.48 3.33 ns
TSRAMA SRAM_A output delay from last register to pad 3.94 5.73 ns
TSRAMDOUT SRAM_DQ output delay from last register to pad 4.66 6.45 ns
TSRAMCE SRAM_CE output delay from last register to pad 4.57 5.95 ns
TSRAMOE SRAM_OE_B output delay from last register to pad 4.79 6.13 ns
TSRAMBLS SRAM_BLS_B output delay from last register to pad 5.25 6.74 ns
TSRAMWE SRAM_WE_B output delay from last register to pad 5.12 6.48 ns
TSRAMDIN SRAM_DQ setup time and input delay from pad to first register 1.93 3.05 ns
TSRAMWAIT SRAM_WAIT setup time and input delay from pad to first register 2.26 3.15 ns
FSMC_REF_CLK SMC reference clock frequency 100 MHz
Notes:
1. All parameters do not include the package flight time and register controlled delays.
2. Refer to the ARM® PrimeCell® Static Memory Controller (PL350 series) Technical Reference Manual for more SMC timing details.
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Product Specification 25
Quad-SPI Interfaces
Table 36: Quad-SPI Interface Switching Characteristics
Symbol Description Load
Conditions Min Max Units
Feedback Clock Enabled
TDCQSPICLK1 Quad-SPI clock duty cycle All(1)(2) 44 56 %
TQSPICKO1 Data and slave select output delay 15 pF(1) –0.10(3) 2.30 ns
30 pF(2) –1.00 3.80
TQSPIDCK1 Input data setup time 15 pF(1) 2.00 – ns
30 pF(2) 3.30 –
TQSPICKD1 Input data hold time 15 pF(1) 1.30 – ns
30 pF(2) 1.50 –
TQSPISSCLK1 Slave select asserted to next clock edge All(1)(2) 1–F
QSPI_REF_CLK cycle
TQSPICLKSS1 Clock edge to slave select deasserted All(1)(2) 1–F
QSPI_REF_CLK cycle
FQSPICLK1 Quad-SPI device clock frequency 15 pF(1) – 100(4) MHz
30 pF(2) –70
(4)
Feedback Clock Disabled
TDCQSPICLK2 Quad-SPI clock duty cycle All(1)(2) 44 56 %
TQSPICKO2 Data and slave select output delay 15 pF(1) –0.10 3.80 ns
30 pF(2) –1.00 3.80 ns
TQSPIDCK2 Input data setup time All(1)(2) 6–ns
TQSPICKD2 Input data hold time All(1)(2) 12.5 – ns
TQSPISSCLK2 Slave select asserted to next clock edge All(1)(2) 1–F
QSPI_REF_CLK cycle
TQSPICLKSS2 Clock edge to slave select deasserted All(1)(2) 1–F
QSPI_REF_CLK cycle
FQSPICLK2 Quad-SPI device clock frequency All(1)(2) –40MHz
Feedback Clock Enabled or Disabled
FQSPI_REF_CLK Quad-SPI reference clock frequency All(1)(2) –200MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads, feedback clock pin has no load. Quad-SPI single slave select
4-bit I/O mode.
2. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 30 pF loads in 4-bit stacked I/O configuration, feedback clock pin has no
load. Quad-SPI single slave select 4-bit I/O mode.
3. The TQSPICKO1 is an effective value. Use it to compute the available memory device input setup and hold timing budgets based on the given
device clock-out duty-cycle limits.
4. Requires appropriate component selection/board design.
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Product Specification 26
X-Ref Target - Figure 4
Figure 4: Quad-SPI Interface (Feedback Clock Enabled) Timing Diagram
X-Ref Target - Figure 5
Figure 5: Quad-SPI Interface (Feedback Clock Disabled) Timing Diagram
QSPI{1,0}_SS_B
QSPI_SCLK_OUT
CPOL = 0
QSPI{1,0}_IO_[3,0]
QSPI_SCLK_OUT
CPOL = 1
DS191_03_110615
TQSPICKO1
TQSPISSCLK1
TQSPISSCLK1
TQSPICLKSS1
TQSPICLKSS1
TQSPIDCK1
TQSPICKD1
OUT1OUT0 INn-2 INn-1 INn
OUT0 OUT1 INn-1
QSPI{1,0}_SS_B
QSPI_SCLK_OUT
(CPOL = 0)
QSPI_SCLK_OUT
(CPOL = 1)
QSPI{0,1}_IO_[3:0]
T
QSPICKD2
T
QSPIDCK2
T
QSPICKO2
T
QSPICLKSS2
T
QSPISSCLK2
T
QSPICLKSS2
T
QSPISSCLK2
INn
DS191_04_110615
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Product Specification 27
ULPI Interfaces
Table 37: ULPI Interface Clock Receiving Mode Switching Characteristics(1)(2)
Symbol Description Min Typ Max Units
TULPIDCK Input setup to ULPI clock, all inputs 3.00 ns
TULPICKD Input hold to ULPI clock, all inputs 1.00 ns
TULPICKO ULPI clock to output valid, all outputs 1.70 8.86 ns
FULPICLK ULPI device clock frequency 60 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads, 60 MHz device clock frequency.
2. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
X-Ref Target - Figure 6
Figure 6: ULPI Interface Timing Diagram
TULPICKO
TULPICKO
TULPICKD
TULPIDCK
TULPICKD
TULPIDCK
USB{0,1}_ULPI_CLK
USB{0,1}_ULPI_DATA[7:0] (Input)
USB{0,1}_ULPI_DIR,
USB{0,1}_ULPI_NXT
USB{0,1}_ULPI_STP
USB{0,1}_ULPI_DATA[7:0] (Output)
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Product Specification 28
RGMII and MDIO Interfaces
Table 38: RGMII and MDIO Interface Switching Characteristics(1)(2)(3)
Symbol Description Min Typ Max Units
TDCGETXCLK Transmit clock duty cycle 45 55 %
TGEMTXCKO RGMII_TX_D[3:0], RGMII_TX_CTL output clock to out time –0.50 0.50 ns
TGEMRXDCK RGMII_RX_D[3:0], RGMII_RX_CTL input setup time 0.80 ns
TGEMRXCKD RGMII_RX_D[3:0], RGMII_RX_CTL input hold time 0.80 ns
TMDIOCLK MDC output clock period 400 ns
TMDIOCKH MDC clock High time 160 ns
TMDIOCKL MDC clock Low time 160 ns
TMDIODCK MDIO input data setup time 80 ns
TMDIOCKD MDIO input data hold time 0 ns
TMDIOCKO MDIO data output delay –20 170 ns
FGETXCLK RGMII_TX_CLK transmit clock frequency 125 MHz
FGERXCLK RGMII_RX_CLK receive clock frequency 125 MHz
FENET_REF_CLK Ethernet reference clock frequency 125 MHz
Notes:
1. Test conditions: LVCMOS25, fast slew rate, 8 mA drive strength, 15 pF loads. Values in this table are specified during 1000 Mb/s operation.
2. LVCMOS25 slow slew rate and LVCMOS33 are not supported.
3. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
X-Ref Target - Figure 7
Figure 7: RGMII Interface Timing Diagram
RGMII_TX_CLK
MDIO_CLK
RGMII_RX_CLK
TGEMTXCKO
TMDIOCKH TMDIOCLK TMDIOCKL
TGEMRXCKD
RGMII_TX_D[3:0]
RGMII_TX_CTL
RGMII_RX_D[3:0]
RGMII_RX_CTL
TGEMRXDCK
TMDIOCKD
MDIO_IO (Input)
TMDIODCK
DS191_06_022013
MDIO_IO (Output)
TMDIOCKO
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Product Specification 29
SD/SDIO Interfaces
Table 39: SD/SDIO Interface High Speed Mode Switching Characteristics(1)
Symbol Description Min Typ Max Units
TDCSDHSCLK SD device clock duty cycle 50 %
TSDHSCKO Clock to output delay, all outputs 2.00 12.00 ns
TSDHSDCK Input setup time, all inputs 3.00 ns
TSDHSCKD Input hold time, all inputs 1.05 ns
FSD_REF_CLK SD reference clock frequency 125 MHz
FSDHSCLK High speed mode SD device clock frequency 0 50 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
X-Ref Target - Figure 8
Figure 8: SD/SDIO Interface High Speed Mode Timing Diagram
Table 40: SD/SDIO Interface Switching Characteristics(1)
Symbol Description Min Typ Max Units
TDCSDSCLK SD device clock duty cycle 50 %
TSDSCKO Clock to output delay, all outputs 2.00 12.00 ns
TSDSDCK Input setup time, all inputs 4.00 ns
TSDSCKD Input hold time, all inputs 3.00 ns
FSD_REF_CLK SD reference clock frequency 125 MHz
FSDIDCLK Clock frequency in identification mode 400 KHz
FSDSCLK Standard mode SD device clock frequency 0 25 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
X-Ref Target - Figure 9
Figure 9: SD/SDIO Interface Standard Mode Timing Diagram
TSDHSCKO
TSDHSCKD
TSDHSDCK
SD{0,1}_CLK
SD{0,1}_DATA[3:0],
SD{0,1}_CMD (input)
SD{0,1}_DATA[3:0],
SD{0,1}_CMD (output)
DS191_07_022013
DS191_108_030113
TSDSCKO
TSDSCKD
TSDSDCK
SD{0,1}_CLK
SD{0,1}_DATA[3:0],
SD{0,1}_CMD (input)
SD{0,1}_DATA[3:0],
SD{0,1}_CMD (output)
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Product Specification 30
I2C Interfaces
Table 41: I2C Fast Mode Interface Switching Characteristics(1)
Symbol Description Min Typ Max Units
TDCI2CFCLK I2C{0,1}SCL duty cycle 50 %
TI2CFCKO I2C{0,1}SDAO clock to out delay 900 ns
TI2CFDCK I2C{0,1}SDAI setup time 100 ns
FI2CFCLK I2C{0,1}SCL clock frequency 400 KHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
X-Ref Target - Figure 10
Figure 10: I2C Fast Mode Interface Timing Diagram
Table 42: I2C Standard Mode Interface Switching Characteristics(1)
Symbol Description Min Typ Max Units
TDCI2CSCLK I2C{0,1}SCL duty cycle 50 %
TI2CSCKO I2C{0,1}SDAO clock to out delay 3450 ns
TI2CSDCK I2C{0,1}SDAI setup time 250 ns
FI2CSCLK I2C{0,1}SCL clock frequency 100 KHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
X-Ref Target - Figure 11
Figure 11: I2C Standard Mode Interface Timing Diagram
TI2CFCKO
TI2CFDCK
DS191_08_022013
I2C{0,1}SCL
I2C{0,1}SDAI
I2C{0,1}SDAO
TI2CSCKO
TI2CSDCK
DS191_09_022013
I2C{0,1}SCL
I2C{0,1}SDAI
I2C{0,1}SDAO
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Product Specification 31
SPI Interfaces
Table 43: SPI Master Mode Interface Switching Characteristics(1)
Symbol Description Min Typ Max Units
TDCMSPICLK SPI master mode clock duty cycle 50 %
TMSPIDCK Input setup time for SPI{0,1}_MISO 2.00 – ns
TMSPICKD Input hold time for SPI{0,1}_MISO 8.20 – ns
TMSPICKO Output delay for SPI{0,1}_MOSI and SPI{0,1}_SS –3.10 – 3.90 ns
TMSPISSCLK Slave select asserted to first active clock edge 1 FSPI_REF_CLK cycles
TMSPICLKSS Last active clock edge to slave select deasserted 0.5 FSPI_REF_CLK cycles
FMSPICLK SPI master mode device clock frequency 50.00 MHz
FSPI_REF_CLK SPI reference clock frequency 200.00 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
X-Ref Target - Figure 12
Figure 12: SPI Master (CPHA = 0) Interface Timing Diagram
X-Ref Target - Figure 13
Figure 13: SPI Master (CPHA = 1) Interface Timing Diagram
Dn Dn–1 Dn–2 Dn–3D0
Dn Dn–1 Dn–2
T
MSPICKD
T
MSPIDCK
T
MSPICKO
T
MSPICLKSS
T
MSPISSCLK
SPI{0,1}_SS
SPI{0,1}_CLK (CPOL=0)
SPI{0,1}_CLK (CPOL=1)
SPI{0,1}_MOSI
SPI{0,1}_MISO
DS191_10_022013
Dn Dn–1 Dn–2 Dn–3D0
Dn Dn–1 Dn–2 Dn–3D0
TMSPICKD
TMSPIDCK
TMSPICKO
TMSPICLKSS
TMSPISSCLK
SPI{0,1}_SS
SPI{0,1}_CLK (CPOL=0)
SPI{0,1}_CLK (CPOL=1)
SPI{0,1}_MOSI
SPI{0,1}_MISO
DS191_11_022013
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Product Specification 32
Table 44: SPI Slave Mode Interface Switching Characteristics(1)(2)
Symbol Description Min Max Units
TSSPIDCK Input setup time for SPI{0,1}_MOSI and SPI{0,1}_SS 1 – FSPI_REF_CLK cycles
TSSPICKD Input hold time for SPI{0,1}_MOSI and SPI{0,1}_SS 1 – FSPI_REF_CLK cycles
TSSPICKO Output delay for SPI{0,1}_MISO 0 2.6 FSPI_REF_CLK cycles
TSSPISSCLK Slave select asserted to first active clock edge 1 FSPI_REF_CLK cycles
TSSPICLKSS Last active clock edge to slave select deasserted 1 FSPI_REF_CLK cycles
FSSPICLK SPI slave mode device clock frequency 25 MHz
FSPI_REF_CLK SPI reference clock frequency 200 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
2. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
X-Ref Target - Figure 14
Figure 14: SPI Slave (CPHA = 0) Interface Timing Diagram
X-Ref Target - Figure 15
Figure 15: SPI Slave (CPHA = 1) Interface Timing Diagram
Dn Dn–1 Dn–2 Dn–3D0
Dn Dn–1 Dn–2 Dn–3D0
T
SSPICKO
T
SSPICKD
T
SSPIDCK
T
SSPICLKSS
T
SSPISSCLK
SPI{0,1}_SS
SPI{0,1}_CLK (CPOL=0)
SPI{0,1}_CLK (CPOL=1)
SPI{0,1}_MOSI
SPI{0,1}_MISO
DS191_12_022013
Dn Dn–1 Dn–2 Dn–3D0
Dn Dn–1 Dn–2 Dn–3D0
TSSPICKO
TSSPICKD
TSSPIDCK
TSSPICLKSS
TSSPISSCLK
SPI{0,1}_SS
SPI{0,1}_CLK (CPOL=0)
SPI{0,1}_CLK (CPOL=1)
SPI{0,1}_MOSI
SPI{0,1}_MISO
DS191_13_021013
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Product Specification 33
CAN Interfaces
PJTAG Interfaces
UART Interfaces
Table 45: CAN Interface Switching Characteristics(1)
Symbol Description Min Max Units
TPWCANRX Minimum receive pulse width 1 µs
TPWCANTX Minimum transmit pulse width 1 µs
FCAN_REF_CLK
Internally sourced CAN reference clock frequency 100 MHz
Externally sourced CAN reference clock frequency 40 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
Table 46: PJTAG Interface(1)(2)
Symbol Description Min Max Units
TPJTAGDCK PJTAG input setup time 2.4 ns
TPJTAGCKD PJTAG input hold time 2.0 ns
TPJTAGCKO PJTAG clock to out delay 12.5 ns
TPJTAGCLK PJTAG clock frequency 20 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
2. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
X-Ref Target - Figure 16
Figure 16: PJTAG Interface Timing Diagram
Table 47: UART Interface Switching Characteristics(1)
Symbol Description Min Max Units
BAUDTXMAX Maximum transmit baud rate 1 Mb/s
BAUDRXMAX Maximum receive baud rate 1 Mb/s
FUART_REF_CLK UART reference clock frequency 100 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
PJTAGCLK
PJTAGTMS, PJTAGTDI
PJTAGTDO
TPJTAGDCK TPJTAGCKD
TPJTAGCKO
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Product Specification 34
GPIO Interfaces
Trace Interface
Triple Timer Counter Interface
Watchdog Timer
Table 48: GPIO Banks Switching Characteristics(1)
Symbol Description Min Max Units
TPWGPIOH Input high pulse width 10 x 1/cpu1x µs
TPWGPIOL Input low pulse width 10 x 1/cpu1x µs
Notes:
1. Pulse width requirement for interrupt.
X-Ref Target - Figure 17
Figure 17: GPIO Interface Timing Diagram
Table 49: Trace Interface Switching Characteristics(1)
Symbol Description Min Max Units
TTCECKO Trace clock to output delay, all outputs –1.4 1.5 ns
TDCTCECLK Trace clock duty cycle 40 60 %
FTCECLK Trace clock frequency 80 MHz
Notes:
1. Test conditions: LVCMOS25, fast slew rate, 8 mA drive strength, 15 pF loads.
Table 50: Triple Timer Counter interface Switching Characteristics(1)
Symbol Description Min Max Units
TPWTTCOCLK Triple timer counter output clock pulse width 2 x 1/cpu1x ns
FTTCOCLK Triple timer counter output clock frequency cpu1x/4 MHz
TTTCICLKH Triple timer counter input clock high pulse width 1.5 x 1/cpu1x ns
TTTCICLKL Triple timer counter input clock low pulse width 1.5 x 1/cpu1x ns
FTTCICLK Triple timer counter input clock frequency cpu1x/3 MHz
Notes:
1. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
Table 51: Watchdog Timer Switching Characteristics
Symbol Description Min Max Units
FWDTCLK(1) Watchdog timer input clock frequency 10 MHz
Notes:
1. Applies to external input clock through MIO pin only.
T
PWGPIOL
T
PWGPIOH
GPIO
DS191_15_022013
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Product Specification 35
PL Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in the PL. The
numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same
guidelines as the AC Switching Characteristics, page 15. In each table, the I/O bank type is either High Performance (HP)
or High Range (HR).
Table 53 provides the maximum data rates for applicable memory standards using the Zynq-7000 SoC memory PHY. The
final performance of the memory interface is determined through a complete design implemented in the Vivado or ISE
Design Suite, following guidelines in the Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions User Guide
(UG586).
Table 52: PL Networking Applications Interface Performances
Description I/O Bank
Type
Speed Grade Units
-3E -2E/-2I/-2LI -1C/-1I -1Q/-1LQ
SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8) HR 710 710 625 625 Mb/s
HP 710 710 625 625 Mb/s
DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14) HR 1250 1250 950 950 Mb/s
HP 1600 1400 1250 1250 Mb/s
SDR LVDS receiver (SFI-4.1)(1) HR 710 710 625 625 Mb/s
HP 710 710 625 625 Mb/s
DDR LVDS receiver (SPI-4.2)(1) HR 1250 1250 950 950 Mb/s
HP 1600 1400 1250 1250 Mb/s
Notes:
1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate
deterministic performance.
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Product Specification 36
Table 53: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface
Generator (FF and RF Packages)(1)(2)
Memory
Standard I/O Bank Type VCCAUX_IO
Speed Grade Units
-3E -2E/-2I -2LI -1C/-1I -1Q/-1LQ
4:1 Memory Controllers
DDR3
HP 2.0V 1866(3) 1866(3) 1600 1600 1066 Mb/s
HP 1.8V 1600 1333 1333 1066 800 Mb/s
HR N/A 1066 1066 1066 800 800 Mb/s
DDR3L
HP 2.0V 1600 1600 1600 1333 1066 Mb/s
HP 1.8V 1333 1066 1066 800 800 Mb/s
HR N/A 800 800 800 667 N/A Mb/s
DDR2
HP 2.0V 800 800 800 800 667 Mb/s
HP 1.8V 800 800 800 800 667 Mb/s
HR N/A 800 800 800 800 533 Mb/s
RLDRAM III
HP 2.0V 800 667 667 667 550 MHz
HP 1.8V 550 500 500 450 400 MHz
HR N/A N/A
2:1 Memory Controllers
DDR3
HP 2.0V
1066 1066 1066 800 667
Mb/s
HP 1.8V Mb/s
HR N/A Mb/s
DDR3L
HP 2.0V 1066 1066 1066 800 667 Mb/s
HP 1.8V Mb/s
HR N/A 800 800 800 667 N/A Mb/s
DDR2
HP 2.0V
800 800 800 800
667
Mb/sHP 1.8V 667
HR N/A 533
QDR II+(4)
HP 2.0V 550 500 500 450 300 MHz
HP 1.8V
HR N/A 500 450 450 400 300 MHz
RLDRAM II
HP 2.0V
533 500 500 450 400 MHzHP 1.8V
HR N/A
LPDDR2
HP 2.0V
667 667 667 667 533
Mb/s
HP 1.8V Mb/s
HR N/A Mb/s
Notes:
1. VREF tracking is required. For more information, see the Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions User
Guide (UG586).
2. When using the internal VREF, the maximum data rate is 800 Mb/s (400 MHz).
3. For designs using 1866 Mb/s components, contact Xilinx Technical Support.
4. The maximum QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations. Burst length 2 (BL = 2) implementations
are limited to 333 MHz for all speed grades and I/O bank types.
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Product Specification 37
Table 54: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface
Generator (FB, RB, and SB Packages)(1)(2)
Memory
Standard I/O Bank Type VCCAUX_IO(3) Speed Grade Units
-3E -2E/-2I/-2LI -1C/-1I -1Q
4:1 Memory Controllers
DDR3 HP N/A 1333 1066 800 800 Mb/s
HR N/A 1066 800 800 800 Mb/s
DDR3L HP N/A 1066 800 667 667 Mb/s
HR N/A 800 800 667 N/A Mb/s
DDR2 HP N/A 800 800 800 667 Mb/s
HR N/A 800 667 667 533 Mb/s
RLDRAM III HP N/A 550 500 450 350 MHz
HR N/A N/A
2:1 Memory Controllers
DDR3 HP N/A 1066 1066 800 667 Mb/s
HR N/A 1066 800 800 667 Mb/s
DDR3L HP N/A 1066 800 667 667 Mb/s
HR N/A 800 800 667 N/A Mb/s
DDR2 HP N/A 800 800 800 667 Mb/s
HR N/A 800 667 667 533 Mb/s
QDR II+(4) HP N/A 550 500 450 300 MHz
HR N/A 450 400 350 300 MHz
RLDRAM II HP N/A 533 500 450 400 MHz
HR N/A
LPDDR2 HP N/A 667 667 667 400 Mb/s
HR N/A 667 667 533 400 Mb/s
Notes:
1. VREF tracking is required. For more information, see the Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions User
Guide (UG586).
2. When using the internal VREF, the maximum data rate is 800 Mb/s (400 MHz).
3. FB, RB, and SB packages do not have separate VCCAUX_IO supply pins to adjust the pre-driver voltage of the HP I/O banks.
4. The maximum QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations. Burst length 2 (BL = 2) implementations
are limited to 333 MHz for all speed grades and I/O bank types.
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Product Specification 38
PL Switching Characteristics
IOB Pad Input/Output/3-State
Table 55 (high-range IOB (HR)) and Table 56 (high-performance IOB (HP)) summarizes the values of standard-specific data
input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays.
•T
IOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies
depending on the capability of the SelectIO input buffer.
•T
IOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies
depending on the capability of the SelectIO output buffer.
•T
IOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO capability of the output buffer. In HP I/O banks, the internal DCI
termination turn-on time is always faster than TIOTP when the DCITERMDISABLE pin is used. In HR I/O banks, the
IN_TERM termination turn-on time is always faster than TIOTP when the INTERMDISABLE pin is used.
Table 55: IOB High Range (HR) Switching Characteristics
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
-3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ -3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ -3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ
LVTTL_S4 1.31 1.42 1.64 1.64 3.77 3.90 4.00 4.00 3.52 3.67 3.86 3.86 ns
LVTTL_S8 1.31 1.42 1.64 1.64 3.50 3.64 3.73 3.73 3.26 3.40 3.60 3.60 ns
LVTTL_S12 1.31 1.42 1.64 1.64 3.49 3.62 3.72 3.72 3.24 3.39 3.58 3.58 ns
LVTTL_S16 1.31 1.42 1.64 1.64 3.03 3.17 3.26 3.26 2.79 2.93 3.13 3.13 ns
LVTTL_S24 1.31 1.42 1.64 1.64 3.25 3.39 3.48 3.48 3.01 3.15 3.35 3.35 ns
LVTTL_F4 1.31 1.42 1.64 1.64 3.22 3.36 3.45 3.45 2.98 3.12 3.32 3.32 ns
LVTTL_F8 1.31 1.42 1.64 1.64 2.71 2.84 2.93 2.93 2.46 2.61 2.80 2.80 ns
LVTTL_F12 1.31 1.42 1.64 1.64 2.69 2.82 2.92 2.92 2.44 2.59 2.79 2.79 ns
LVTTL_F16 1.31 1.42 1.64 1.64 2.57 2.85 3.15 3.15 2.33 2.61 3.02 3.02 ns
LVTTL_F24 1.31 1.42 1.64 1.64 2.41 2.64 2.89 3.04 2.16 2.41 2.76 2.91 ns
LVDS_25 0.64 0.68 0.80 0.87 1.36 1.47 1.55 1.55 1.11 1.24 1.41 1.41 ns
MINI_LVDS_25 0.68 0.70 0.79 0.87 1.36 1.47 1.55 1.55 1.11 1.24 1.41 1.41 ns
BLVDS_25 0.65 0.69 0.80 0.85 1.83 2.02 2.20 2.57 1.59 1.79 2.07 2.44 ns
RSDS_25 0.63 0.68 0.79 0.87 1.36 1.48 1.55 1.55 1.11 1.24 1.41 1.41 ns
PPDS_25 0.65 0.69 0.80 0.87 1.36 1.49 1.58 1.58 1.11 1.25 1.45 1.45 ns
TMDS_33 0.72 0.76 0.86 0.90 1.43 1.54 1.60 1.60 1.18 1.31 1.47 1.47 ns
PCI33_3 1.28 1.41 1.65 1.65 2.71 3.08 3.52 3.52 2.46 2.84 3.39 3.39 ns
HSUL_12_S 0.63 0.64 0.71 0.85 1.77 1.90 2.00 2.00 1.52 1.67 1.86 1.86 ns
HSUL_12_F 0.63 0.64 0.71 0.85 1.26 1.40 1.50 1.50 1.01 1.16 1.37 1.37 ns
DIFF_HSUL_12_S 0.58 0.61 0.70 0.84 1.55 1.68 1.78 1.78 1.30 1.45 1.65 1.65 ns
DIFF_HSUL_12_F 0.58 0.61 0.70 0.84 1.16 1.28 1.35 1.35 0.92 1.04 1.21 1.21 ns
MOBILE_DDR_S 0.64 0.66 0.74 0.74 2.58 2.91 3.31 3.31 2.33 2.68 3.17 3.17 ns
MOBILE_DDR_F 0.64 0.66 0.74 0.74 1.91 2.13 2.36 2.36 1.66 1.89 2.23 2.23 ns
DIFF_MOBILE_DDR_S 0.63 0.66 0.75 0.75 2.51 2.84 3.24 3.24 2.26 2.61 3.10 3.10 ns
DIFF_MOBILE_DDR_F 0.63 0.66 0.75 0.75 1.89 2.11 2.34 2.34 1.64 1.88 2.21 2.21 ns
HSTL_I_S 0.61 0.64 0.73 0.84 1.55 1.69 1.80 1.80 1.30 1.46 1.67 1.67 ns
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Product Specification 39
HSTL_II_S 0.61 0.64 0.73 0.84 1.21 1.34 1.43 1.61 0.96 1.11 1.30 1.47 ns
HSTL_I_18_S 0.64 0.67 0.76 0.85 1.28 1.39 1.45 1.45 1.04 1.16 1.31 1.32 ns
HSTL_II_18_S 0.64 0.67 0.76 0.85 1.18 1.31 1.40 1.57 0.93 1.08 1.27 1.44 ns
DIFF_HSTL_I_S 0.63 0.67 0.77 0.84 1.42 1.54 1.61 1.78 1.17 1.31 1.48 1.65 ns
DIFF_HSTL_II_S 0.63 0.67 0.77 0.84 1.15 1.24 1.27 1.61 0.91 1.01 1.14 1.47 ns
DIFF_HSTL_I_18_S 0.65 0.69 0.78 0.84 1.27 1.38 1.43 1.45 1.03 1.14 1.30 1.32 ns
DIFF_HSTL_II_18_S 0.65 0.69 0.78 0.85 1.14 1.23 1.26 1.57 0.90 1.00 1.13 1.44 ns
HSTL_I_F 0.61 0.64 0.73 0.84 1.10 1.19 1.23 1.31 0.85 0.96 1.10 1.18 ns
HSTL_II_F 0.61 0.64 0.73 0.84 1.05 1.18 1.28 1.31 0.80 0.95 1.15 1.18 ns
HSTL_I_18_F 0.64 0.67 0.76 0.85 1.05 1.18 1.28 1.36 0.80 0.95 1.15 1.22 ns
HSTL_II_18_F 0.64 0.67 0.76 0.85 1.03 1.14 1.23 1.32 0.78 0.90 1.10 1.19 ns
DIFF_HSTL_I_F 0.63 0.67 0.77 0.84 1.09 1.18 1.22 1.31 0.84 0.95 1.09 1.18 ns
DIFF_HSTL_II_F 0.63 0.67 0.77 0.84 1.02 1.11 1.14 1.31 0.77 0.88 1.01 1.18 ns
DIFF_HSTL_I_18_F 0.65 0.69 0.78 0.84 1.08 1.17 1.21 1.36 0.83 0.94 1.07 1.22 ns
DIFF_HSTL_II_18_F 0.65 0.69 0.78 0.85 1.01 1.10 1.13 1.32 0.76 0.87 1.00 1.19 ns
LVCMOS33_S4 1.31 1.40 1.60 1.60 3.77 3.90 4.00 4.00 3.52 3.67 3.86 3.86 ns
LVCMOS33_S8 1.31 1.40 1.60 1.60 3.49 3.62 3.72 3.72 3.24 3.39 3.58 3.58 ns
LVCMOS33_S12 1.31 1.40 1.60 1.60 3.05 3.18 3.28 3.28 2.80 2.95 3.15 3.15 ns
LVCMOS33_S16 1.31 1.40 1.60 1.60 3.06 3.43 3.88 3.88 2.81 3.20 3.75 3.75 ns
LVCMOS33_F4 1.31 1.40 1.60 1.60 3.22 3.36 3.45 3.45 2.98 3.12 3.32 3.32 ns
LVCMOS33_F8 1.31 1.40 1.60 1.60 2.71 2.84 2.93 2.93 2.46 2.61 2.80 2.80 ns
LVCMOS33_F12 1.31 1.40 1.60 1.60 2.57 2.85 3.15 3.15 2.33 2.61 3.02 3.02 ns
LVCMOS33_F16 1.31 1.40 1.60 1.60 2.44 2.69 2.96 2.96 2.19 2.45 2.82 2.82 ns
LVCMOS25_S4 1.08 1.16 1.32 1.35 3.08 3.22 3.31 3.31 2.84 2.98 3.18 3.18 ns
LVCMOS25_S8 1.08 1.16 1.32 1.35 2.85 2.98 3.07 3.08 2.60 2.75 2.94 2.94 ns
LVCMOS25_S12 1.08 1.16 1.32 1.35 2.44 2.57 2.67 2.67 2.19 2.34 2.54 2.54 ns
LVCMOS25_S16 1.08 1.16 1.32 1.35 2.79 2.92 3.01 3.01 2.54 2.68 2.88 2.88 ns
LVCMOS25_F4 1.08 1.16 1.32 1.35 2.71 2.84 2.93 2.93 2.46 2.61 2.80 2.80 ns
LVCMOS25_F8 1.08 1.16 1.32 1.35 2.14 2.28 2.37 2.37 1.90 2.04 2.24 2.24 ns
LVCMOS25_F12 1.08 1.16 1.32 1.35 2.15 2.29 2.52 2.52 1.91 2.05 2.38 2.38 ns
LVCMOS25_F16 1.08 1.16 1.32 1.35 1.92 2.17 2.45 2.45 1.67 1.94 2.32 2.32 ns
LVCMOS18_S4 0.64 0.66 0.74 0.95 1.55 1.68 1.78 1.78 1.30 1.45 1.65 1.65 ns
LVCMOS18_S8 0.64 0.66 0.74 0.95 2.14 2.28 2.37 2.37 1.90 2.04 2.24 2.24 ns
LVCMOS18_S12 0.64 0.66 0.74 0.95 2.14 2.28 2.37 2.37 1.90 2.04 2.24 2.24 ns
LVCMOS18_S16 0.64 0.66 0.74 0.95 1.49 1.62 1.72 1.72 1.24 1.39 1.58 1.58 ns
LVCMOS18_S24 0.64 0.66 0.74 0.95 1.74 1.92 2.08 2.22 1.50 1.69 1.95 2.08 ns
Table 55: IOB High Range (HR) Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
-3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ -3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ -3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ
(I XILINXe W Send Feed back
Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics
DS191 (v1.18.1) July 2, 2018 www.xilinx.com
Product Specification 40
LVCMOS18_F4 0.64 0.66 0.74 0.95 1.38 1.51 1.61 1.64 1.13 1.28 1.47 1.50 ns
LVCMOS18_F8 0.64 0.66 0.74 0.95 1.64 1.78 1.87 1.87 1.40 1.54 1.74 1.74 ns
LVCMOS18_F12 0.64 0.66 0.74 0.95 1.64 1.78 1.87 1.87 1.40 1.54 1.74 1.74 ns
LVCMOS18_F16 0.64 0.66 0.74 0.95 1.52 1.68 1.81 1.81 1.28 1.45 1.68 1.68 ns
LVCMOS18_F24 0.64 0.66 0.74 0.95 1.34 1.46 1.55 2.09 1.09 1.23 1.42 1.96 ns
LVCMOS15_S4 0.66 0.69 0.81 0.93 1.86 2.00 2.09 2.09 1.62 1.76 1.96 1.96 ns
LVCMOS15_S8 0.66 0.69 0.81 0.93 2.05 2.18 2.28 2.28 1.80 1.95 2.14 2.15 ns
LVCMOS15_S12 0.66 0.69 0.81 0.93 1.83 2.03 2.23 2.23 1.59 1.80 2.10 2.10 ns
LVCMOS15_S16 0.66 0.69 0.81 0.93 1.76 1.95 2.13 2.13 1.52 1.72 1.99 1.99 ns
LVCMOS15_F4 0.66 0.69 0.81 0.93 1.63 1.76 1.86 1.86 1.38 1.53 1.72 1.72 ns
LVCMOS15_F8 0.66 0.69 0.81 0.93 1.79 1.99 2.18 2.18 1.55 1.76 2.05 2.05 ns
LVCMOS15_F12 0.66 0.69 0.81 0.93 1.40 1.54 1.65 1.65 1.15 1.31 1.52 1.52 ns
LVCMOS15_F16 0.66 0.69 0.81 0.93 1.37 1.51 1.61 1.89 1.13 1.27 1.48 1.75 ns
LVCMOS12_S4 0.88 0.91 1.00 1.17 2.53 2.67 2.76 2.76 2.29 2.43 2.63 2.63 ns
LVCMOS12_S8 0.88 0.91 1.00 1.17 2.05 2.18 2.28 2.28 1.80 1.95 2.14 2.15 ns
LVCMOS12_S12 0.88 0.91 1.00 1.17 1.75 1.89 1.98 1.98 1.51 1.65 1.85 1.85 ns
LVCMOS12_F4 0.88 0.91 1.00 1.17 1.94 2.07 2.17 2.17 1.69 1.84 2.04 2.04 ns
LVCMOS12_F8 0.88 0.91 1.00 1.17 1.50 1.64 1.73 1.73 1.26 1.40 1.60 1.60 ns
LVCMOS12_F12 0.88 0.91 1.00 1.17 1.54 1.71 1.87 1.87 1.29 1.48 1.74 1.74 ns
SSTL135_S 0.61 0.64 0.73 0.85 1.27 1.40 1.50 1.53 1.02 1.17 1.36 1.40 ns
SSTL15_S 0.61 0.64 0.73 0.73 1.24 1.37 1.47 1.53 0.99 1.14 1.33 1.40 ns
SSTL18_I_S 0.64 0.67 0.76 0.84 1.59 1.74 1.85 1.85 1.34 1.50 1.72 1.72 ns
SSTL18_II_S 0.64 0.67 0.76 0.85 1.27 1.40 1.50 1.50 1.02 1.17 1.36 1.36 ns
DIFF_SSTL135_S 0.59 0.61 0.73 0.85 1.27 1.40 1.50 1.53 1.02 1.17 1.36 1.40 ns
DIFF_SSTL15_S 0.63 0.67 0.77 0.85 1.24 1.37 1.47 1.53 0.99 1.14 1.33 1.40 ns
DIFF_SSTL18_I_S 0.65 0.69 0.78 0.85 1.50 1.63 1.72 1.82 1.26 1.40 1.59 1.69 ns
DIFF_SSTL18_II_S 0.65 0.69 0.78 0.85 1.13 1.22 1.25 1.50 0.88 0.99 1.12 1.36 ns
SSTL135_F 0.61 0.64 0.73 0.85 1.04 1.17 1.26 1.31 0.79 0.93 1.13 1.18 ns
SSTL15_F 0.61 0.64 0.73 0.73 1.04 1.17 1.26 1.26 0.79 0.93 1.13 1.13 ns
SSTL18_I_F 0.64 0.67 0.76 0.84 1.12 1.22 1.26 1.34 0.88 0.99 1.13 1.21 ns
SSTL18_II_F 0.64 0.67 0.76 0.85 1.05 1.18 1.28 1.32 0.80 0.95 1.15 1.19 ns
DIFF_SSTL135_F 0.59 0.61 0.73 0.85 1.04 1.17 1.26 1.31 0.79 0.93 1.13 1.18 ns
DIFF_SSTL15_F 0.63 0.67 0.77 0.85 1.04 1.17 1.26 1.26 0.79 0.93 1.13 1.13 ns
DIFF_SSTL18_I_F 0.65 0.69 0.78 0.85 1.10 1.19 1.23 1.34 0.85 0.96 1.10 1.21 ns
DIFF_SSTL18_II_F 0.65 0.69 0.78 0.85 1.02 1.10 1.14 1.32 0.77 0.87 1.00 1.19 ns
Table 55: IOB High Range (HR) Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
-3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ -3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ -3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ
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Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics
DS191 (v1.18.1) July 2, 2018 www.xilinx.com
Product Specification 41
Table 56: IOB High Performance (HP) Switching Characteristics
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
-3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ -3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ -3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ
LVDS 0.75 0.79 0.92 0.96 1.05 1.17 1.24 1.26 0.88 1.01 1.08 1.10 ns
HSUL_12_S 0.69 0.72 0.82 0.98 1.65 1.84 2.05 2.05 1.48 1.68 1.89 1.89 ns
HSUL_12_F 0.69 0.72 0.82 0.98 1.39 1.54 1.68 1.68 1.22 1.38 1.52 1.52 ns
DIFF_HSUL_12_S 0.69 0.72 0.82 0.98 1.65 1.84 2.05 2.05 1.48 1.68 1.89 1.89 ns
DIFF_HSUL_12_F 0.69 0.72 0.82 0.98 1.39 1.54 1.68 1.68 1.22 1.38 1.52 1.52 ns
DIFF_HSUL_12_DCI_S 0.69 0.72 0.82 0.82 1.78 1.91 2.05 2.05 1.61 1.76 1.89 1.89 ns
DIFF_HSUL_12_DCI_F 0.69 0.72 0.82 0.82 1.56 1.67 1.76 1.76 1.39 1.51 1.60 1.60 ns
HSTL_I_S 0.68 0.72 0.82 0.90 1.15 1.28 1.38 1.38 0.98 1.12 1.22 1.22 ns
HSTL_II_S 0.68 0.72 0.82 0.90 1.05 1.17 1.26 1.27 0.88 1.01 1.10 1.11 ns
HSTL_I_18_S 0.70 0.72 0.82 0.95 1.12 1.24 1.34 1.34 0.95 1.08 1.18 1.18 ns
HSTL_II_18_S 0.70 0.72 0.82 0.90 1.06 1.18 1.26 1.27 0.89 1.02 1.10 1.11 ns
HSTL_I_12_S 0.68 0.72 0.82 0.96 1.14 1.27 1.37 1.37 0.97 1.11 1.21 1.21 ns
HSTL_I_DCI_S 0.68 0.72 0.82 0.90 1.11 1.23 1.33 1.33 0.94 1.07 1.17 1.17 ns
HSTL_II_DCI_S 0.68 0.72 0.82 0.85 1.05 1.17 1.26 1.26 0.88 1.01 1.10 1.10 ns
HSTL_II_T_DCI_S 0.70 0.72 0.82 0.82 1.15 1.28 1.38 1.38 0.98 1.12 1.22 1.22 ns
HSTL_I_DCI_18_S 0.70 0.72 0.82 0.90 1.11 1.23 1.33 1.33 0.94 1.07 1.17 1.17 ns
HSTL_II_DCI_18_S 0.70 0.72 0.82 0.82 1.05 1.16 1.24 1.24 0.88 1.00 1.08 1.08 ns
HSTL_II _T_DCI_18_S 0.70 0.72 0.82 0.84 1.11 1.23 1.33 1.34 0.94 1.07 1.17 1.18 ns
DIFF_HSTL_I_S 0.75 0.79 0.92 1.02 1.15 1.28 1.38 1.38 0.98 1.12 1.22 1.22 ns
DIFF_HSTL_II_S 0.75 0.79 0.92 1.02 1.05 1.17 1.26 1.32 0.88 1.01 1.10 1.16 ns
DIFF_HSTL_I_DCI_S 0.75 0.79 0.92 0.92 1.15 1.28 1.38 1.38 0.98 1.12 1.22 1.22 ns
DIFF_HSTL_II_DCI_S 0.75 0.79 0.92 0.92 1.05 1.17 1.26 1.26 0.88 1.01 1.10 1.10 ns
DIFF_HSTL_I_18_S 0.75 0.79 0.92 0.98 1.12 1.24 1.34 1.34 0.95 1.08 1.18 1.18 ns
DIFF_HSTL_II_18_S 0.75 0.79 0.92 0.99 1.06 1.18 1.26 1.32 0.89 1.02 1.10 1.16 ns
DIFF_HSTL_I_DCI_18_S 0.75 0.79 0.92 0.92 1.11 1.23 1.33 1.33 0.94 1.07 1.17 1.17 ns
DIFF_HSTL_II_DCI_18_S 0.75 0.79 0.92 0.93 1.05 1.16 1.24 1.26 0.88 1.00 1.08 1.10 ns
DIFF_HSTL_II _T_DCI_18_S 0.75 0.79 0.92 0.92 1.11 1.23 1.33 1.33 0.94 1.07 1.17 1.17 ns
HSTL_I_F 0.68 0.72 0.82 0.90 1.02 1.14 1.22 1.22 0.85 0.98 1.06 1.06 ns
HSTL_II_F 0.68 0.72 0.82 0.90 0.97 1.08 1.15 1.15 0.80 0.92 0.99 0.99 ns
HSTL_I_18_F 0.70 0.72 0.82 0.95 1.04 1.16 1.24 1.24 0.87 1.00 1.08 1.08 ns
HSTL_II_18_F 0.70 0.72 0.82 0.90 0.98 1.09 1.16 1.20 0.81 0.94 1.00 1.03 ns
HSTL_I_12_F 0.68 0.72 0.82 0.96 1.02 1.13 1.21 1.21 0.85 0.97 1.05 1.05 ns
HSTL_I_DCI_F 0.68 0.72 0.82 0.90 1.04 1.16 1.24 1.24 0.87 1.00 1.08 1.08 ns
HSTL_II_DCI_F 0.68 0.72 0.82 0.85 0.97 1.08 1.15 1.15 0.80 0.92 0.99 0.99 ns
HSTL_II_T_DCI_F 0.70 0.72 0.82 0.82 1.02 1.14 1.22 1.22 0.85 0.98 1.06 1.06 ns
HSTL_I_DCI_18_F 0.70 0.72 0.82 0.90 1.04 1.16 1.24 1.24 0.87 1.00 1.08 1.08 ns
HSTL_II_DCI_18_F 0.70 0.72 0.82 0.82 0.98 1.09 1.16 1.16 0.81 0.93 1.00 1.00 ns
HSTL_II _T_DCI_18_F 0.70 0.72 0.82 0.84 1.04 1.16 1.24 1.24 0.87 1.00 1.08 1.08 ns
(I XILINXe W Send Feed back
Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics
DS191 (v1.18.1) July 2, 2018 www.xilinx.com
Product Specification 42
DIFF_HSTL_I_F 0.75 0.79 0.92 1.02 1.02 1.14 1.22 1.22 0.85 0.98 1.06 1.06 ns
DIFF_HSTL_II_F 0.75 0.79 0.92 1.02 0.97 1.08 1.15 1.20 0.80 0.92 0.99 1.03 ns
DIFF_HSTL_I_DCI_F 0.75 0.79 0.92 0.92 1.02 1.14 1.22 1.22 0.85 0.98 1.06 1.06 ns
DIFF_HSTL_II_DCI_F 0.75 0.79 0.92 0.92 0.97 1.08 1.15 1.15 0.80 0.92 0.99 0.99 ns
DIFF_HSTL_I_18_F 0.75 0.79 0.92 0.98 1.04 1.16 1.24 1.24 0.87 1.00 1.08 1.08 ns
DIFF_HSTL_II_18_F 0.75 0.79 0.92 0.99 0.98 1.09 1.16 1.24 0.81 0.94 1.00 1.08 ns
DIFF_HSTL_I_DCI_18_F 0.75 0.79 0.92 0.92 1.04 1.16 1.24 1.24 0.87 1.00 1.08 1.08 ns
DIFF_HSTL_II_DCI_18_F 0.75 0.79 0.92 0.93 0.98 1.09 1.16 1.18 0.81 0.93 1.00 1.02 ns
DIFF_HSTL_II _T_DCI_18_F 0.75 0.79 0.92 0.92 1.04 1.16 1.24 1.24 0.87 1.00 1.08 1.08 ns
LVCMOS18_S2 0.47 0.50 0.60 0.90 3.95 4.28 4.85 4.85 3.78 4.13 4.69 4.69 ns
LVCMOS18_S4 0.47 0.50 0.60 0.90 2.67 2.98 3.43 3.43 2.50 2.82 3.27 3.27 ns
LVCMOS18_S6 0.47 0.50 0.60 0.90 2.14 2.38 2.72 2.72 1.97 2.22 2.56 2.56 ns
LVCMOS18_S8 0.47 0.50 0.60 0.90 1.98 2.21 2.52 2.52 1.81 2.05 2.36 2.36 ns
LVCMOS18_S12 0.47 0.50 0.60 0.90 1.70 1.91 2.17 2.17 1.53 1.75 2.01 2.01 ns
LVCMOS18_S16 0.47 0.50 0.60 0.90 1.57 1.75 1.97 1.97 1.40 1.59 1.81 1.81 ns
LVCMOS18_F2 0.47 0.50 0.60 0.90 3.50 3.87 4.48 4.48 3.33 3.71 4.32 4.32 ns
LVCMOS18_F4 0.47 0.50 0.60 0.90 2.23 2.50 2.87 2.87 2.06 2.34 2.71 2.71 ns
LVCMOS18_F6 0.47 0.50 0.60 0.90 1.80 2.00 2.26 2.26 1.63 1.84 2.09 2.09 ns
LVCMOS18_F8 0.47 0.50 0.60 0.90 1.46 1.72 2.04 2.04 1.29 1.56 1.88 1.88 ns
LVCMOS18_F12 0.47 0.50 0.60 0.90 1.26 1.40 1.53 1.53 1.09 1.24 1.37 1.37 ns
LVCMOS18_F16 0.47 0.50 0.60 0.90 1.19 1.33 1.44 1.66 1.02 1.17 1.28 1.50 ns
LVCMOS15_S2 0.59 0.62 0.73 0.88 3.55 3.89 4.45 4.45 3.38 3.73 4.29 4.29 ns
LVCMOS15_S4 0.59 0.62 0.73 0.88 2.45 2.70 3.06 3.06 2.28 2.54 2.90 2.90 ns
LVCMOS15_S6 0.59 0.62 0.73 0.88 2.24 2.51 2.88 2.88 2.07 2.35 2.72 2.72 ns
LVCMOS15_S8 0.59 0.62 0.73 0.88 1.91 2.16 2.49 2.49 1.74 2.00 2.32 2.32 ns
LVCMOS15_S12 0.59 0.62 0.73 0.88 1.77 1.98 2.23 2.23 1.60 1.82 2.07 2.07 ns
LVCMOS15_S16 0.59 0.62 0.73 0.88 1.62 1.81 2.02 2.02 1.45 1.65 1.86 1.86 ns
LVCMOS15_F2 0.59 0.62 0.73 0.88 3.38 3.69 4.18 4.18 3.21 3.53 4.02 4.02 ns
LVCMOS15_F4 0.59 0.62 0.73 0.88 2.04 2.21 2.44 2.44 1.87 2.06 2.27 2.27 ns
LVCMOS15_F6 0.59 0.62 0.73 0.88 1.47 1.74 2.09 2.09 1.30 1.58 1.93 1.93 ns
LVCMOS15_F8 0.59 0.62 0.73 0.88 1.31 1.46 1.61 1.61 1.14 1.30 1.45 1.45 ns
LVCMOS15_F12 0.59 0.62 0.73 0.88 1.21 1.34 1.45 1.45 1.04 1.18 1.29 1.29 ns
LVCMOS15_F16 0.59 0.62 0.73 0.88 1.18 1.31 1.41 1.68 1.01 1.15 1.25 1.52 ns
LVCMOS12_S2 0.64 0.67 0.78 1.04 3.38 3.80 4.48 4.48 3.21 3.64 4.31 4.31 ns
LVCMOS12_S4 0.64 0.67 0.78 1.04 2.62 2.94 3.43 3.43 2.45 2.78 3.27 3.27 ns
LVCMOS12_S6 0.64 0.67 0.78 1.04 2.05 2.33 2.72 2.72 1.88 2.17 2.56 2.56 ns
LVCMOS12_S8 0.64 0.67 0.78 1.04 1.94 2.18 2.51 2.51 1.77 2.02 2.34 2.34 ns
Table 56: IOB High Performance (HP) Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
-3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ -3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ -3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ
(I XILINXe W Send Feed back
Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics
DS191 (v1.18.1) July 2, 2018 www.xilinx.com
Product Specification 43
LVCMOS12_F2 0.64 0.67 0.78 1.04 2.84 3.15 3.62 3.62 2.67 2.99 3.46 3.46 ns
LVCMOS12_F4 0.64 0.67 0.78 1.04 1.97 2.18 2.44 2.44 1.80 2.02 2.28 2.28 ns
LVCMOS12_F6 0.64 0.67 0.78 1.04 1.33 1.51 1.70 1.70 1.16 1.35 1.54 1.54 ns
LVCMOS12_F8 0.64 0.67 0.78 1.04 1.27 1.42 1.55 1.55 1.10 1.26 1.39 1.39 ns
LVDCI_18 0.47 0.50 0.60 0.87 1.99 2.15 2.35 2.35 1.82 1.99 2.19 2.19 ns
LVDCI_15 0.59 0.62 0.73 0.92 1.98 2.23 2.58 2.58 1.81 2.07 2.41 2.41 ns
LVDCI_DV2_18 0.47 0.50 0.60 0.88 1.99 2.15 2.34 2.34 1.82 1.99 2.18 2.18 ns
LVDCI_DV2_15 0.59 0.62 0.73 0.88 1.98 2.23 2.58 2.58 1.81 2.07 2.41 2.41 ns
HSLVDCI_18 0.68 0.72 0.82 0.90 1.99 2.15 2.35 2.35 1.82 1.99 2.19 2.19 ns
HSLVDCI_15 0.68 0.72 0.82 0.93 1.98 2.23 2.58 2.58 1.81 2.07 2.41 2.41 ns
SSTL18_I_S 0.68 0.72 0.82 0.95 1.02 1.15 1.24 1.24 0.85 0.99 1.08 1.08 ns
SSTL18_II_S 0.68 0.72 0.82 1.01 1.17 1.29 1.37 1.38 1.00 1.13 1.21 1.22 ns
SSTL18_I_DCI_S 0.68 0.72 0.82 0.87 0.92 1.06 1.17 1.18 0.75 0.90 1.01 1.02 ns
SSTL18_II_DCI_S 0.68 0.72 0.82 0.82 0.88 0.98 1.08 1.12 0.71 0.83 0.92 0.96 ns
SSTL18_II_T_DCI_S 0.68 0.72 0.82 0.98 0.92 1.06 1.17 1.18 0.75 0.90 1.01 1.02 ns
SSTL15_S 0.68 0.72 0.82 0.82 0.94 1.06 1.15 1.16 0.77 0.91 0.99 1.00 ns
SSTL15_DCI_S 0.68 0.72 0.82 0.90 0.94 1.06 1.15 1.16 0.77 0.90 0.99 1.00 ns
SSTL15_T_DCI_S 0.68 0.72 0.82 0.87 0.94 1.06 1.15 1.15 0.77 0.90 0.99 0.99 ns
SSTL135_S 0.69 0.72 0.82 0.93 0.97 1.10 1.19 1.20 0.80 0.94 1.03 1.03 ns
SSTL135_DCI_S 0.69 0.72 0.82 0.85 0.97 1.09 1.19 1.20 0.80 0.93 1.03 1.03 ns
SSTL135_T_DCI_S 0.69 0.72 0.82 0.93 0.97 1.09 1.19 1.20 0.80 0.93 1.03 1.03 ns
SSTL12_S 0.69 0.72 0.82 1.02 0.96 1.09 1.18 1.18 0.79 0.93 1.02 1.02 ns
SSTL12_DCI_S 0.69 0.72 0.82 0.90 1.03 1.17 1.27 1.27 0.86 1.01 1.11 1.11 ns
SSTL12_T_DCI_S 0.69 0.72 0.82 0.88 1.03 1.17 1.27 1.27 0.86 1.01 1.11 1.11 ns
DIFF_SSTL18_I_S 0.75 0.79 0.92 0.99 1.02 1.15 1.24 1.29 0.85 0.99 1.08 1.13 ns
DIFF_SSTL18_II_S 0.75 0.79 0.92 0.93 1.17 1.29 1.37 1.40 1.00 1.13 1.21 1.24 ns
DIFF_SSTL18_I_DCI_S 0.75 0.79 0.92 0.92 0.92 1.06 1.17 1.24 0.75 0.90 1.01 1.08 ns
DIFF_SSTL18_II_DCI_S 0.75 0.79 0.92 0.96 0.88 0.98 1.08 1.18 0.71 0.83 0.92 1.02 ns
DIFF_SSTL18_II_T_DCI_S 0.75 0.79 0.92 0.92 0.92 1.06 1.17 1.24 0.75 0.90 1.01 1.08 ns
DIFF_SSTL15_S 0.68 0.72 0.82 0.99 0.94 1.06 1.15 1.16 0.77 0.91 0.99 1.00 ns
DIFF_SSTL15_DCI_S 0.68 0.72 0.82 0.96 0.94 1.06 1.15 1.16 0.77 0.90 0.99 1.00 ns
DIFF_SSTL15_T_DCI_S 0.68 0.72 0.82 0.88 0.94 1.06 1.15 1.23 0.77 0.90 0.99 1.07 ns
DIFF_SSTL135_S 0.69 0.72 0.82 1.09 0.97 1.10 1.19 1.20 0.80 0.94 1.03 1.03 ns
DIFF_SSTL135_DCI_S 0.69 0.72 0.82 0.90 0.97 1.09 1.19 1.20 0.80 0.93 1.03 1.03 ns
DIFF_SSTL135_T_DCI_S 0.69 0.72 0.82 0.84 0.97 1.09 1.19 1.27 0.80 0.93 1.03 1.11 ns
DIFF_SSTL12_S 0.69 0.72 0.82 0.96 0.96 1.09 1.18 1.18 0.79 0.93 1.02 1.02 ns
DIFF_SSTL12_DCI_S 0.69 0.72 0.82 0.87 1.03 1.17 1.27 1.27 0.86 1.01 1.11 1.11 ns
DIFF_SSTL12_T_DCI_S 0.69 0.72 0.82 0.96 1.03 1.17 1.27 1.27 0.86 1.01 1.11 1.11 ns
Table 56: IOB High Performance (HP) Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
-3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ -3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ -3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ
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SSTL18_I_F 0.68 0.72 0.82 0.95 0.94 1.06 1.15 1.15 0.77 0.91 0.99 0.99 ns
SSTL18_II_F 0.68 0.72 0.82 1.01 0.97 1.09 1.16 1.21 0.80 0.93 1.00 1.05 ns
SSTL18_I_DCI_F 0.68 0.72 0.82 0.87 0.89 1.02 1.10 1.15 0.72 0.86 0.94 0.99 ns
SSTL18_II_DCI_F 0.68 0.72 0.82 0.82 0.89 1.02 1.10 1.10 0.72 0.86 0.94 0.94 ns
SSTL18_II_T_DCI_F 0.68 0.72 0.82 0.98 0.89 1.02 1.10 1.15 0.72 0.86 0.94 0.99 ns
SSTL15_F 0.68 0.72 0.82 0.82 0.89 1.01 1.09 1.09 0.72 0.85 0.93 0.93 ns
SSTL15_DCI_F 0.68 0.72 0.82 0.90 0.89 1.01 1.09 1.12 0.72 0.85 0.93 0.96 ns
SSTL15_T_DCI_F 0.68 0.72 0.82 0.87 0.89 1.01 1.09 1.12 0.72 0.85 0.93 0.96 ns
SSTL135_F 0.69 0.72 0.82 0.93 0.88 1.00 1.08 1.12 0.71 0.85 0.92 0.96 ns
SSTL135_DCI_F 0.69 0.72 0.82 0.85 0.89 1.00 1.08 1.12 0.72 0.85 0.92 0.96 ns
SSTL135_T_DCI_F 0.69 0.72 0.82 0.93 0.89 1.00 1.08 1.12 0.72 0.85 0.92 0.96 ns
SSTL12_F 0.69 0.72 0.82 1.02 0.88 1.00 1.08 1.12 0.71 0.84 0.92 0.96 ns
SSTL12_DCI_F 0.69 0.72 0.82 0.90 0.91 1.03 1.11 1.11 0.74 0.88 0.95 0.95 ns
SSTL12_T_DCI_F 0.69 0.72 0.82 0.88 0.91 1.03 1.11 1.12 0.74 0.88 0.95 0.96 ns
DIFF_SSTL18_I_F 0.75 0.79 0.92 0.99 0.94 1.06 1.15 1.23 0.77 0.91 0.99 1.07 ns
DIFF_SSTL18_II_F 0.75 0.79 0.92 0.93 0.97 1.09 1.16 1.24 0.80 0.93 1.00 1.08 ns
DIFF_SSTL18_I_DCI_F 0.75 0.79 0.92 0.92 0.89 1.02 1.10 1.23 0.72 0.86 0.94 1.07 ns
DIFF_SSTL18_II_DCI_F 0.75 0.79 0.92 0.96 0.89 1.02 1.10 1.16 0.72 0.86 0.94 1.00 ns
DIFF_SSTL18_II_T_DCI_F 0.75 0.79 0.92 0.92 0.89 1.02 1.10 1.24 0.72 0.86 0.94 1.08 ns
DIFF_SSTL15_F 0.68 0.72 0.82 0.99 0.89 1.01 1.09 1.09 0.72 0.85 0.93 0.93 ns
DIFF_SSTL15_DCI_F 0.68 0.72 0.82 0.96 0.89 1.01 1.09 1.12 0.72 0.85 0.93 0.96 ns
DIFF_SSTL15_T_DCI_F 0.68 0.72 0.82 0.88 0.89 1.01 1.09 1.20 0.72 0.85 0.93 1.03 ns
DIFF_SSTL135_F 0.69 0.72 0.82 1.09 0.88 1.00 1.08 1.12 0.71 0.85 0.92 0.96 ns
DIFF_SSTL135_DCI_F 0.69 0.72 0.82 0.90 0.89 1.00 1.08 1.12 0.72 0.85 0.92 0.96 ns
DIFF_SSTL135_T_DCI_F 0.69 0.72 0.82 0.84 0.89 1.00 1.08 1.20 0.72 0.85 0.92 1.03 ns
DIFF_SSTL12_F 0.69 0.72 0.82 0.96 0.88 1.00 1.08 1.12 0.71 0.84 0.92 0.96 ns
DIFF_SSTL12_DCI_F 0.69 0.72 0.82 0.87 0.91 1.03 1.11 1.11 0.74 0.88 0.95 0.95 ns
DIFF_SSTL12_T_DCI_F 0.69 0.72 0.82 0.96 0.91 1.03 1.11 1.18 0.74 0.88 0.95 1.02 ns
Table 56: IOB High Performance (HP) Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
-3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ -3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ -3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ
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Product Specification 45
Table 57 specifies the values of TIOTPHZ and TIOIBUFDISABLE. TIOTPHZ is described as the delay from the T pin to the IOB pad
through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). TIOIBUFDISABLE is described
as the IOB delay from IBUFDISABLE to O output. In HP I/O banks, the internal DCI termination turn-off time is always faster
than TIOTPHZ when the DCITERMDISABLE pin is used. In HR I/O banks, the internal IN_TERM termination turn-off time is
always faster than TIOTPHZ when the INTERMDISABLE pin is used.
Table 57: IOB 3-state Output Switching Characteristics
Symbol Description Speed Grade Units
-3E -2E/-2I/-2LI -1C/-1I -1Q/-1LQ
TIOTPHZ T input to pad high-impedance 0.76 0.86 0.99 0.99 ns
TIOIBUFDISABLE_HR IBUF turn-on time from IBUFDISABLE to O output for HR
I/O banks
1.72 1.89 2.14 2.14 ns
TIOIBUFDISABLE_HP IBUF turn-on time from IBUFDISABLE to O output for HP
I/O banks
1.31 1.46 1.76 1.76 ns
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Product Specification 46
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 58 shows the test setup parameters used for measuring input delay.
Table 58: Input Delay Measurement Methodology
Description I/O Standard Attribute VL(1)(2) VH(1)(2) VMEAS
(1)(4)(6)
VREF
(1)(3)(5)
LVCMOS, 1.2V LVCMOS12 0.1 1.1 0.6
LVCMOS, 1.5V LVCMOS15 0.1 1.4 0.75
LVCMOS, 1.8V LVCMOS18 0.1 1.7 0.9
LVCMOS, 2.5V LVCMOS25 0.1 2.4 1.25
LVCMOS, 3.3V LVCMOS33 0.1 3.2 1.65
LVTTL, 3.3V LVTTL 0.1 3.2 1.65
MOBILE_DDR, 1.8V MOBILE_DDR 0.1 1.7 0.9
PCI33, 3.3V PCI33_3 0.1 3.2 1.65
HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12 VREF –0.5 V
REF +0.5 V
REF 0.60
HSTL, Class I & II, 1.5V HSTL_I, HSTL_II VREF –0.65 V
REF +0.65 V
REF 0.75
HSTL, Class I & II, 1.8V HSTL_I_18, HSTL_II_18 VREF –0.8 V
REF +0.8 V
REF 0.90
HSUL (High-Speed Unterminated Logic), 1.2V HSUL_12 VREF –0.5 V
REF +0.5 V
REF 0.60
SSTL (Stub Terminated Transceiver Logic), 1.2V SSTL12 VREF –0.5 V
REF +0.5 V
REF 0.60
SSTL, 1.35V SSTL135, SSTL135_R VREF – 0.575 VREF + 0.575 VREF 0.675
SSTL, 1.5V SSTL15, SSTL15_R VREF –0.65 V
REF +0.65 V
REF 0.75
SSTL, Class I & II, 1.8V SSTL18_I, SSTL18_II VREF –0.8 V
REF +0.8 V
REF 0.90
DIFF_MOBILE_DDR, 1.8V DIFF_MOBILE_DDR 0.9 – 0.125 0.9 + 0.125 0(6)
DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 0.6 – 0.125 0.6 + 0.125 0(6)
DIFF_HSTL, Class I & II,1.5V DIFF_HSTL_I,
DIFF_HSTL_II
0.75 – 0.125 0.75 + 0.125 0(6)
DIFF_HSTL, Class I & II, 1.8V DIFF_HSTL_I_18,
DIFF_HSTL_II_18
0.9 – 0.125 0.9 + 0.125 0(6)
DIFF_HSUL, 1.2V DIFF_HSUL_12 0.6 – 0.125 0.6 + 0.125 0(6)
DIFF_SSTL, 1.2V DIFF_SSTL12 0.6 – 0.125 0.6 + 0.125 0(6)
DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135,
DIFF_SSTL135_R
0.675 – 0.125 0.675 + 0.125 0(6)
DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL15,
DIFF_SSTL15_R
0.75 – 0.125 0.75 + 0.125 0(6)
DIFF_SSTL18_I/DIFF_SSTL18_II, 1.8V DIFF_SSTL18_I,
DIFF_SSTL18_II
0.9 – 0.125 0.9 + 0.125 0(6)
LVDS (Low-Voltage Differential Signaling), 1.8V LVDS 0.9 – 0.125 0.9 + 0.125 0(6)
LVDS_25, 2.5V LVDS_25 1.2 – 0.125 1.2 + 0.125 0(6)
BLVDS_25, 2.5V BLVDS_25 1.25 – 0.125 1.25 + 0.125 0(6)
MINI_LVDS_25, 2.5V MINI_LVDS_25 1.25 – 0.125 1.25 + 0.125 0(6)
PPDS_25 PPDS_25 1.25 – 0.125 1.25 + 0.125 0(6)
RSDS_25 RSDS_25 1.25 – 0.125 1.25 + 0.125 0(6)
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Product Specification 47
Output Delay Measurements
Output delays are measured with short output traces. Standard termination was used for all testing. The propagation delay
of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the
generalized test setups shown in Figure 18 and Figure 19.
Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate
prediction of propagation delay in any given application can be obtained through IBIS simulation, using this method:
1. Simulate the output driver of choice into the generalized test setup using values from Table 59.
2. Record the time to VMEAS.
3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance
value to represent the load.
4. Record the time to VMEAS.
TMDS_33 TMDS_33 3 – 0.125 3 + 0.125 0(6)
Notes:
1. The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay
measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other
DCI standards are the same for the corresponding non-DCI standards.
2. Input waveform switches between VLand VH.
3. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF
values listed are typical.
4. Input voltage level from which measurement starts.
5. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 18.
6. The value given is the differential input voltage.
X-Ref Target - Figure 18
Figure 18: Single-Ended Test Setup
X-Ref Target - Figure 19
Figure 19: Differential Test Setup
Table 58: Input Delay Measurement Methodology (Cont’d)
Description I/O Standard Attribute VL(1)(2) VH(1)(2) VMEAS
(1)(4)(6)
VREF
(1)(3)(5)
VREF
RREF
VMEAS
(Voltage Level When Taking
Delay Measurement)
CREF
(Probe Capacitance)
Output
DS191_19_060415
RREF VMEAS
+
CREF
Output
DS191_20_060415
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Product Specification 48
5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation delay of the
PCB trace.
Table 59: Output Delay Measurement Methodology
Description I/O Standard Attribute RREF
(Ω)
CREF(1)
(pF)
VMEAS
(V)
VREF
(V)
LVCMOS, 1.2V LVCMOS12 1M 0 0.6 0
LVCMOS/LVDCI/HSLVDCI, 1.5V LVCMOS15, LVDCI_15, HSLVDCI_15 1M 0 0.75 0
LVCMOS/LVDCI/HSLVDCI, 1.8V LVCMOS18, LVDCI_15, HSLVDCI_18 1M 0 0.9 0
LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0
LVCMOS, 3.3V LVCMOS33 1M 0 1.65 0
LVTTL, 3.3V LVTTL 1M 0 1.65 0
PCI33, 3.3V PCI33_3 25 10 1.65 0
HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12 50 0 VREF 0.6
HSTL, Class I, 1.5V HSTL_I 50 0 VREF 0.75
HSTL, Class II, 1.5V HSTL_II 25 0 VREF 0.75
HSTL, Class I, 1.8V HSTL_I_18 50 0 VREF 0.9
HSTL, Class II, 1.8V HSTL_II_18 25 0 VREF 0.9
HSUL (High-Speed Unterminated Logic), 1.2V HSUL_12 50 0 VREF 0.6
SSTL12, 1.2V SSTL12 50 0 VREF 0.6
SSTL135/SSTL135_R, 1.35V SSTL135, SSTL135_R 50 0 VREF 0.675
SSTL15/SSTL15_R, 1.5V SSTL15, SSTL15_R 50 0 VREF 0.75
SSTL (Stub Series Terminated Logic),
Class I & Class II, 1.8V
SSTL18_I, SSTL18_II 50 0 VREF 0.9
DIFF_MOBILE_DDR, 1.8V DIFF_MOBILE_DDR 50 0 VREF 0.9
DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 50 0 VREF 0.6
DIFF_HSTL, Class I & II, 1.5V DIFF_HSTL_I, DIFF_HSTL_II 50 0 VREF 0.75
DIFF_HSTL, Class I & II, 1.8V DIFF_HSTL_I_18, DIFF_HSTL_II_18 50 0 VREF 0.9
DIFF_HSUL_12, 1.2V DIFF_HSUL_12 50 0 VREF 0.6
DIFF_SSTL12, 1.2V DIFF_SSTL12 50 0 VREF 0.6
DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135, DIFF_SSTL135_R 50 0 VREF 0.675
DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL15, DIFF_SSTL15_R 50 0 VREF 0.75
DIFF_SSTL18, Class I & II, 1.8V DIFF_SSTL18_I, DIFF_SSTL18_II 50 0 VREF 0.9
LVDS (Low-Voltage Differential Signaling), 1.8V LVDS 100 0 0(2) 0
LVDS, 2.5V LVDS_25 100 0 0(2) 0
BLVDS (Bus LVDS), 2.5V BLVDS_25 100 0 0(2) 0
Mini LVDS, 2.5V MINI_LVDS_25 100 0 0(2) 0
PPDS_25 PPDS_25 100 0 0(2) 0
RSDS_25 RSDS_25 100 0 0(2) 0
TMDS_33 TMDS_33 50 0 0(2) 3.3
Notes:
1. CREF is the capacitance of the probe, nominally 0 pF.
2. The value given is the differential output voltage.
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Product Specification 49
Input/Output Logic Switching Characteristics
Table 60: ILOGIC Switching Characteristics
Symbol Description
Speed Grade
Units
-3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ
Setup/Hold
TICE1CK/TICKCE1 CE1 pin setup/hold with respect to CLK 0.42/0.00 0.48/0.00 0.67/0.00 0.67/0.00 ns
TISRCK/TICKSR SR pin setup/hold with respect to CLK 0.53/0.01 0.61/0.01 0.99/0.01 0.99/0.01 ns
TIDOCKE2/TIOCKDE2 D pin setup/hold with respect to CLK without delay
(HP I/O banks only)
0.01/0.27 0.01/0.29 0.01/0.34 0.01/0.34 ns
TIDOCKDE2/TIOCKDDE2 DDLY pin setup/hold with respect to CLK (using IDELAY)
(HP I/O banks only)
0.01/0.27 0.02/0.29 0.02/0.34 0.02/0.34 ns
TIDOCKE3/TIOCKDE3 D pin setup/hold with respect to CLK without delay
(HR I/O banks only)
0.01/0.27 0.01/0.29 0.01/0.34 0.01/0.34 ns
TIDOCKDE3/TIOCKDDE3 DDLY pin setup/hold with respect to CLK (using IDELAY)
(HR I/O banks only)
0.01/0.27 0.02/0.29 0.02/0.34 0.02/0.34 ns
Combinatorial
TIDIE2 D pin to O pin propagation delay, no delay
(HP I/O banks only)
0.09 0.10 0.12 0.12 ns
TIDIDE2 DDLY pin to O pin propagation delay (using IDELAY)
(HP I/O banks only)
0.10 0.11 0.13 0.13 ns
TIDIE3 D pin to O pin propagation delay, no delay
(HR I/O banks only)
0.09 0.10 0.12 0.12 ns
TIDIDE3 DDLY pin to O pin propagation delay (using IDELAY)
(HR I/O banks only)
0.10 0.11 0.13 0.13 ns
Sequential Delays
TIDLOE2 D pin to Q1 pin using flip-flop as a latch without delay
(HP I/O banks only)
0.36 0.39 0.45 0.45 ns
TIDLODE2 DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY)
(HP I/O banks only)
0.36 0.39 0.45 0.45 ns
TIDLOE3 D pin to Q1 pin using flip-flop as a latch without delay
(HR I/O banks only)
0.36 0.39 0.45 0.45 ns
TIDLODE3 DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY)
(HR I/O banks only)
0.36 0.39 0.45 0.45 ns
TICKQ CLK to Q outputs 0.47 0.50 0.58 0.58 ns
TRQ_ILOGICE2 SR pin to OQ/TQ out (HP I/O banks only) 0.84 0.94 1.16 1.16 ns
TGSRQ_ILOGICE2 Global set/reset to Q outputs (HP I/O banks only) 7.60 7.60 10.51 10.51 ns
TRQ_ILOGICE3 SR pin to OQ/TQ out (HR I/O banks only) 0.84 0.94 1.16 1.16 ns
TGSRQ_ILOGICE3 Global set/reset to Q outputs (HR I/O banks only) 7.60 7.60 10.51 10.51 ns
Set/Reset
TRPW_ILOGICE2 Minimum pulse width, SR inputs (HP I/O banks only) 0.54 0.63 0.63 0.63 ns, Min
TRPW_ILOGICE3 Minimum pulse width, SR inputs (HR I/O banks only) 0.54 0.63 0.63 0.63 ns, Min
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Product Specification 50
Table 61: OLOGIC Switching Characteristics
Symbol Description
Speed Grade
Units
-3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ
Setup/Hold
TODCK/TOCKD D1/D2 pins setup/hold with respect to CLK 0.45/–0.13 0.50/–0.13 0.58/–0.13 0.58/–0.13 ns
TOOCECK/TOCKOCE OCE pin setup/hold with respect to CLK 0.28/0.03 0.29/0.03 0.45/0.03 0.45/0.03 ns
TOSRCK/TOCKSR SR pin setup/hold with respect to CLK 0.32/0.18 0.38/0.18 0.70/0.18 0.70/0.18 ns
TOTCK/TOCKT T1/T2 pins setup/hold with respect to CLK 0.49/–0.16 0.56/–0.16 0.68/–0.16 0.68/–0.13 ns
TOTCECK/TOCKTCE TCE pin setup/hold with respect to CLK 0.28/0.01 0.30/0.01 0.45/0.01 0.45/0.06 ns
Combinatorial
TODQ D1 to OQ out or T1 to TQ out 0.73 0.81 0.97 0.97 ns
Sequential Delays
TOCKQ CLK to OQ/TQ out 0.41 0.43 0.49 0.49 ns
TRQ_OLOGICE2 SR pin to OQ/TQ out (HP I/O banks only) 0.63 0.70 0.83 0.83 ns
TGSRQ_OLOGICE2 Global set/reset to Q outputs (HP I/O banks only) 7.60 7.60 10.51 10.51 ns
TRQ_OLOGICE3 SR pin to OQ/TQ out (HR I/O banks only) 0.63 0.70 0.83 0.83 ns
TGSRQ_OLOGICE3 Global set/reset to Q outputs (HR I/O banks only) 7.60 7.60 10.51 10.51 ns
Set/Reset
TRPW_OLOGICE2 Minimum pulse width, SR inputs (HP I/O banks only) 0.54 0.54 0.63 0.63 ns, Min
TRPW_OLOGICE3 Minimum pulse width, SR inputs (HR I/O banks only) 0.54 0.54 0.63 0.63 ns, Min
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Product Specification 51
Input Serializer/Deserializer Switching Characteristics
Output Serializer/Deserializer Switching Characteristics
Table 62: ISERDES Switching Characteristics
Symbol Description
Speed Grade
Units
-3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ
Setup/Hold for Control Lines
TISCCK_BITSLIP/ TISCKC_BITSLIP BITSLIP pin setup/hold with respect to CLKDIV 0.01/0.12 0.02/0.13 0.02/0.15 0.02/0.15 ns
TISCCK_CE / TISCKC_CE(2) CE pin setup/hold with respect to CLK (for CE1) 0.39/–0.02 0.44/–0.02 0.63/–0.02 0.63/–0.02 ns
TISCCK_CE2 / TISCKC_CE2(2) CE pin setup/hold with respect to CLKDIV (for
CE2)
–0.12/0.29 –0.12/0.31 –0.12/0.35 –0.12/0.35 ns
Setup/Hold for Data Lines
TISDCK_D /TISCKD_D D pin setup/hold with respect to CLK 0.02/0.11 –0.02/0.12 –0.02/0.15 –0.02/0.15 ns
TISDCK_DDLY /TISCKD_DDLY DDLY pin setup/hold with respect to CLK (using
IDELAY)(1)
–0.02/0.11 –0.02/0.12 –0.02/0.15 –0.02/0.15 ns
TISDCK_D_DDR /TISCKD_D_DDR D pin setup/hold with respect to CLK at DDR
mode
–0.02/0.11 –0.02/0.12 –0.02/0.15 –0.02/0.15 ns
TISDCK_DDLY_DDR/
TISCKD_DDLY_DDR
D pin setup/hold with respect to CLK at DDR
mode (using IDELAY)(1)
0.11/0.11 0.12/0.12 0.15/0.15 0.15/0.15 ns
Sequential Delays
TISCKO_Q CLKDIV to out at Q pin 0.46 0.47 0.58 0.58 ns
Propagation Delays
TISDO_DO D input to DO output pin 0.09 0.10 0.12 0.12 ns
Notes:
1. Recorded at 0 tap value.
2. TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in the timing report.
Table 63: OSERDES Switching Characteristics
Symbol Description
Speed Grade
Units
-3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ
Setup/Hold
TOSDCK_D/TOSCKD_D D input setup/hold with respect to CLKDIV 0.37/0.02 0.40/0.02 0.55/0.02 0.55/0.02 ns
TOSDCK_T/TOSCKD_T(1) T input setup/hold with respect to CLK 0.49/–0.15 0.56/–0.15 0.68/–0.15 0.68/–0.15 ns
TOSDCK_T2/TOSCKD_T2(1) T input setup/hold with respect to CLKDIV 0.27/–0.15 0.30/–0.15 0.34/–0.15 0.34/–0.15 ns
TOSCCK_OCE/TOSCKC_OCE OCE input setup/hold with respect to CLK 0.28/0.03 0.29/0.03 0.45/0.03 0.45/0.03 ns
TOSCCK_S SR (reset) input setup with respect to CLKDIV 0.41 0.46 0.75 0.75 ns
TOSCCK_TCE/TOSCKC_TCE TCE input setup/hold with respect to CLK 0.28/0.01 0.30/0.01 0.45/0.01 0.45/0.01 ns
Sequential Delays
TOSCKO_OQ Clock to out from CLK to OQ 0.35 0.37 0.42 0.42 ns
TOSCKO_TQ Clock to out from CLK to TQ 0.41 0.43 0.49 0.49 ns
Combinatorial
TOSDO_TTQ T input to TQ out 0.73 0.81 0.97 0.97 ns
Notes:
1. TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in the timing report.
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Product Specification 52
Input/Output Delay Switching Characteristics
Table 64: Input/Output Delay Switching Characteristics
Symbol Description
Speed Grade
Units
-3E -2E/-2I/
-2LI -1C/-1I -1Q/
-1LQ
IDELAYCTRL
TDLYCCO_RDY Reset to ready for IDELAYCTRL 3.22 3.22 3.22 3.22 µs
FIDELAYCTRL_REF Attribute REFCLK frequency = 200.0(1) 200 200 200 200 MHz
Attribute REFCLK frequency = 300.0(1) 300 300 N/A N/A MHz
Attribute REFCLK frequency = 400.0(1) 400 400 N/A N/A MHz
IDELAYCTRL_REF_PRECI
SION REFCLK precision ±10 ±10 ±10 ±10 MHz
TIDELAYCTRL_RPW Minimum reset pulse width 52.00 52.00 52.00 52.00 ns
IDELAY/ODELAY
TIDELAYRESOLUTION IDELAY/ODELAY chain delay resolution 1/(32 x 2 x FREFs
TIDELAYPAT_JIT and
TODELAYPAT_JIT
Pattern dependent period jitter in delay chain for
clock pattern.(2) 0000ps
per tap
Pattern dependent period jitter in delay chain for
random data pattern (PRBS 23)(3)
±5 ±5 ±5 ±5 ps
per tap
Pattern dependent period jitter in delay chain for
random data pattern (PRBS 23)(4)
±9 ±9 ±9 ±9 ps
per tap
TIDELAY_CLK_MAX/
TODELAY_CLK_MAX
Maximum frequency of CLK input to
IDELAY/ODELAY
800 800 710 710 MHz
TIDCCK_CE / TIDCKC_CE CE pin setup/hold with respect to C for IDELAY 0.11/0.10 0.14/0.12 0.18/0.14 0.18/0.14 ns
TODCCK_CE / TODCKC_CE CE pin setup/hold with respect to C for ODELAY 0.14/0.03 0.16/0.04 0.19/0.05 0.19/0.05 ns
TIDCCK_INC/ TIDCKC_INC INC pin setup/hold with respect to C for IDELAY 0.10/0.14 0.12/0.16 0.14/0.20 0.14/0.20 ns
TODCCK_INC/ TODCKC_INC INC pin setup/hold with respect to C for ODELAY 0.10/0.07 0.12/0.08 0.13/0.09 0.13/0.09 ns
TIDCCK_RST/ TIDCKC_RST RST pin setup/hold with respect to C for IDELAY 0.13/0.08 0.14/0.10 0.16/0.12 0.16/0.12 ns
TODCCK_RST/ TODCKC_RST RST pin setup/hold with respect to C for ODELAY 0.16/0.04 0.19/0.06 0.24/0.08 0.24/0.08 ns
TIDDO_IDATAIN Propagation delay through IDELAY Note 5 Note 5 Note 5 Note 5 ps
TODDO_ODATAIN Propagation delay through ODELAY Note 5 Note 5 Note 5 Note 5 ps
Notes:
1. Average tap delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps.
2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE.
3. When HIGH_PERFORMANCE mode is set to TRUE.
4. When HIGH_PERFORMANCE mode is set to FALSE.
5. Delay depends on IDELAY/ODELAY tap setting. See the timing report for actual values.
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Table 65: IO_FIFO Switching Characteristics
Symbol Description Speed Grade Units
-3E -2E/-2I/-2LI -1C/-1I -1Q/-1LQ
IO_FIFO Clock to Out Delays
TOFFCKO_DO RDCLK to Q outputs 0.51 0.56 0.63 0.63 ns
TCKO_FLAGS Clock to IO_FIFO flags 0.59 0.62 0.81 0.81 ns
Setup/Hold
TCCK_D/TCKC_D D inputs to WRCLK 0.43/–0.01 0.47/–0.01 0.53/–0.01 0.53/0.09 ns
TIFFCCK_WREN /TIFFCKC_WREN WREN to WRCLK 0.39/–0.01 0.43/–0.01 0.50/–0.01 0.50/–0.01 ns
TOFFCCK_RDEN/TOFFCKC_RDEN RDEN to RDCLK 0.49/0.01 0.53/0.02 0.61/0.02 0.61/0.02 ns
Minimum Pulse Width
TPWH_IO_FIFO RESET, RDCLK, WRCLK 0.81 0.92 1.08 1.08 ns
TPWL_IO_FIFO RESET, RDCLK, WRCLK 0.81 0.92 1.08 1.08 ns
Maximum Frequency
FMAX RDCLK and WRCLK 533.05 470.37 400.00 400.00 MHz
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Product Specification 54
CLB Switching Characteristics
Table 66: CLB Switching Characteristics
Symbol Description Speed Grade Units
-3E -2E/-2I/-2LI -1C/-1I -1Q/-1LQ
Combinatorial Delays
TILO An – Dn LUT address to A 0.05 0.05 0.06 0.06 ns, Max
TILO_2 An – Dn LUT address to AMUX/CMUX 0.15 0.16 0.19 0.19 ns, Max
TILO_3 An – Dn LUT address to BMUX_A 0.24 0.25 0.30 0.30 ns, Max
TITO An – Dn inputs to A – D Q outputs 0.58 0.61 0.74 0.74 ns, Max
TAXA AX inputs to AMUX output 0.38 0.40 0.49 0.49 ns, Max
TAXB AX inputs to BMUX output 0.40 0.42 0.52 0.52 ns, Max
TAXC AX inputs to CMUX output 0.39 0.41 0.50 0.50 ns, Max
TAXD AX inputs to DMUX output 0.43 0.44 0.52 0.52 ns, Max
TBXB BX inputs to BMUX output 0.31 0.33 0.40 0.40 ns, Max
TBXD BX inputs to DMUX output 0.38 0.39 0.47 0.47 ns, Max
TCXC CX inputs to CMUX output 0.27 0.28 0.34 0.34 ns, Max
TCXD CX inputs to DMUX output 0.33 0.34 0.41 0.41 ns, Max
TDXD DX inputs to DMUX output 0.32 0.33 0.40 0.40 ns, Max
Sequential Delays
TCKO Clock to AQ – DQ outputs 0.26 0.27 0.32 0.32 ns, Max
TSHCKO Clock to AMUX – DMUX outputs 0.32 0.32 0.39 0.39 ns, Max
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
TAS/TAH AN–D
N input to CLK on A – D flip-flops 0.01/0.12 0.02/0.13 0.03/0.18 0.03/0.24 ns, Min
TDICK/TCKDI AX–D
X input to CLK on A – D flip-flops 0.04/0.14 0.04/0.14 0.05/0.20 0.05/0.26 ns, Min
AX–D
X input through MUXs and/or carry logic to
CLK on A – D flip-flops
0.36/0.10 0.37/0.11 0.46/0.16 0.46/0.22 ns, Min
TCECK_CLB/TCKCE_CLB CE input to CLK on A – D flip-flops 0.19/0.05 0.20/0.05 0.25/0.05 0.25/0.11 ns, Min
TSRCK/TCKSR SR input to CLK on A – D flip-flops 0.30/0.05 0.31/0.07 0.37/0.09 0.37/0.22 ns, Min
Set/Reset
TSRMIN SR input minimum pulse width 0.52 0.78 1.04 1.04 ns, Min
TRQ Delay from SR input to AQ – DQ flip-flops 0.38 0.38 0.46 0.46 ns, Max
TCEO Delay from CE input to AQ – DQ flip-flops 0.34 0.35 0.43 0.43 ns, Max
FTOG Toggle frequency (for export control) 1818 1818 1818 1818 MHz
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Product Specification 55
CLB Distributed RAM Switching Characteristics (SLICEM Only)
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 67: CLB Distributed RAM Switching Characteristics
Symbol Description Speed Grade Units
-3E -2E/-2I/-2LI -1C/-1I -1Q/-1LQ
Sequential Delays
TSHCKO(1) Clock to A – B outputs 0.68 0.70 0.85 0.85 ns, Max
TSHCKO_1 Clock to AMUX – BMUX outputs 0.91 0.95 1.15 1.15 ns, Max
Setup and Hold Times Before/After Clock CLK
TDS_LRAM/TDH_LRAM A – D inputs to CLK 0.45/0.23 0.45/0.24 0.54/0.27 0.54/0.28 ns, Min
TAS_LRAM/TAH_LRAM Address An inputs to clock 0.13/0.50 0.14/0.50 0.17/0.58 0.17/0.61 ns, Min
Address An inputs through MUXs and/or carry
logic to clock
0.40/0.16 0.42/0.17 0.52/0.23 0.52/0.29 ns, Min
TWS_LRAM/TWH_LRAM WE input to clock 0.29/0.09 0.30/0.09 0.36/0.09 0.36/0.11 ns, Min
TCECK_LRAM/TCKCE_LRAM CE input to CLK 0.29/0.09 0.30/0.09 0.37/0.09 0.37/0.11 ns, Min
Clock CLK
TMPW_LRAM Minimum pulse width 0.68 0.77 0.91 0.91 ns, Min
TMCP Minimum clock period 1.35 1.54 1.82 1.82 ns, Min
Notes:
1. TSHCKO also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path.
Table 68: CLB Shift Register Switching Characteristics
Symbol Description Speed Grade Units
-3E -2E/-2I/-2LI -1C/-1I -1Q/-1LQ
Sequential Delays
TREG Clock to A – D outputs 0.96 0.98 1.20 1.20 ns, Max
TREG_MUX Clock to AMUX – DMUX output 1.19 1.23 1.50 1.50 ns, Max
TREG_M31 Clock to DMUX output via M31 output 0.89 0.91 1.10 1.10 ns, Max
Setup and Hold Times Before/After Clock CLK
TWS_SHFREG/TWH_SHFREG WE input 0.26/0.09 0.27/0.09 0.33/0.09 0.33/0.11 ns, Min
TCECK_SHFREG/TCKCE_SHFREG CE input to CLK 0.27/0.09 0.28/0.09 0.33/0.09 0.33/0.11 ns, Min
TDS_SHFREG/TDH_SHFREG A – D inputs to CLK 0.28/0.26 0.28/0.26 0.33/0.30 0.33/0.36 ns, Min
Clock CLK
TMPW_SHFREG Minimum pulse width 0.55 0.65 0.78 0.78 ns, Min
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Product Specification 56
Block RAM and FIFO Switching Characteristics
Table 69: Block RAM and FIFO Switching Characteristics
Symbol Description Speed Grade Units
-3E -2E/-2I/-2LI -1C/-1I -1Q/-1LQ
Block RAM and FIFO Clock-to-Out Delays
TRCKO_DO and
TRCKO_DO_REG(1)
Clock CLK to DOUT output (without output
register)(2)(3)
1.57 1.80 2.08 2.08 ns, Max
Clock CLK to DOUT output (with output
register)(4)(5)
0.54 0.63 0.75 0.75 ns, Max
TRCKO_DO_ECC and
TRCKO_DO_ECC_REG
Clock CLK to DOUT output with ECC
(without output register)(2)(3) 2.35 2.58 3.26 3.26 ns, Max
Clock CLK to DOUT output with ECC (with
output register)(4)(5)
0.62 0.69 0.80 0.80 ns, Max
TRCKO_DO_CASCOUT and
TRCKO_DO_CASCOUT_REG
Clock CLK to DOUT output with Cascade
(without output register)(2)
2.21 2.45 2.80 2.80 ns, Max
Clock CLK to DOUT output with Cascade
(with output register)(4) 0.98 1.08 1.24 1.24 ns, Max
TRCKO_FLAGS Clock CLK to FIFO flags outputs(6) 0.65 0.74 0.89 0.89 ns, Max
TRCKO_POINTERS Clock CLK to FIFO pointers outputs(7) 0.79 0.87 0.98 0.98 ns, Max
TRCKO_PARITY_ECC Clock CLK to ECCPARITY in ECC encode
only mode
0.66 0.72 0.80 0.80 ns, Max
TRCKO_SDBIT_ECC and
TRCKO_SDBIT_ECC_REG
Clock CLK to BITERR (without output
register)
2.17 2.38 3.01 3.01 ns, Max
Clock CLK to BITERR (with output register) 0.57 0.65 0.76 0.76 ns, Max
TRCKO_RDADDR_ECC and
TRCKO_RDADDR_ECC_REG
Clock CLK to RDADDR output with ECC
(without output register)
0.64 0.74 0.90 0.90 ns, Max
Clock CLK to RDADDR output with ECC
(with output register)
0.71 0.79 0.92 0.92 ns, Max
Setup and Hold Times Before/After Clock CLK
TRCCK_ADDRA/TRCKC_ADDRA ADDR inputs(8) 0.38/0.27 0.42/0.28 0.48/0.31 0.48/0.38 ns, Min
TRDCK_DI_WF_NC/
TRCKD_DI_WF_NC
Data input setup/hold time when block RAM
is configured in WRITE_FIRST or
NO_CHANGE mode(9)
0.49/0.51 0.55/0.53 0.63/0.57 0.63/0.57 ns, Min
TRDCK_DI_RF/TRCKD_DI_RF Data input setup/hold time when block RAM
is configured in READ_FIRST mode(9) 0.17/0.25 0.19/0.29 0.21/0.35 0.21/0.35 ns, Min
TRDCK_DI_ECC/TRCKD_DI_ECC DIN inputs with block RAM ECC in standard
mode(9)
0.42/0.37 0.47/0.39 0.53/0.43 0.53/0.58 ns, Min
TRDCK_DI_ECCW/
TRCKD_DI_ECCW
DIN inputs with block RAM ECC encode
only(9)
0.79/0.37 0.87/0.39 0.99/0.43 0.99/0.58 ns, Min
TRDCK_DI_ECC_FIFO/
TRCKD_DI_ECC_FIFO
DIN inputs with FIFO ECC in standard
mode(9) 0.89/0.47 0.98/0.50 1.12/0.54 1.12/0.69 ns, Min
TRCCK_INJECTBITERR/
TRCKC_INJECTBITERR
Inject single/double bit error in ECC mode 0.49/0.30 0.55/0.31 0.63/0.34 0.63/0.43 ns, Min
TRCCK_EN/TRCKC_EN Block RAM Enable (EN) input 0.30/0.17 0.33/0.18 0.38/0.20 0.38/0.32 ns, Min
TRCCK_REGCE/TRCKC_REGCE CE input of output register 0.21/0.13 0.25/0.13 0.31/0.14 0.31/0.19 ns, Min
TRCCK_RSTREG/TRCKC_RSTREG Synchronous RSTREG input 0.25/0.06 0.27/0.06 0.29/0.06 0.29/0.14 ns, Min
TRCCK_RSTRAM/TRCKC_RSTRAM Synchronous RSTRAM input 0.27/0.35 0.29/0.37 0.31/0.39 0.31/0.39 ns, Min
TRCCK_WEA/TRCKC_WEA Write Enable (WE) input (Block RAM only) 0.38/0.15 0.41/0.16 0.46/0.17 0.46/0.29 ns, Min
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TRCCK_WREN/TRCKC_WREN WREN FIFO inputs 0.39/0.25 0.39/0.30 0.40/0.37 0.40/0.49 ns, Min
TRCCK_RDEN/TRCKC_RDEN RDEN FIFO inputs 0.36/0.26 0.36/0.30 0.37/0.37 0.37/0.49 ns, Min
Reset Delays
TRCO_FLAGS Reset RST to FIFO flags/pointers(10) 0.76 0.83 0.93 0.93 ns, Max
TRREC_RST/TRREM_RST FIFO reset recovery and removal timing(11) 1.59/–0.68 1.76/–0.68 2.01/–0.68 2.01/–0.68 ns, Max
Maximum Frequency
FMAX_BRAM_WF_NC Block RAM (Write first and No change
modes)
When not in SDP RF mode
601.32 543.77 458.09 458.09 MHz
FMAX_BRAM_RF_PERFORMANCE Block RAM (Read first, Performance mode)
When in SDP RF mode but no address
overlap between port A and port B
601.32 543.77 458.09 458.09 MHz
FMAX_BRAM_RF_DELAYED_WRITE Block RAM (Read first, Delayed_write mode)
When in SDP RF mode and there is
possibility of overlap between port A and port
B addresses
528.26 477.33 400.80 400.80 MHz
FMAX_CAS_WF_NC Block RAM Cascade (Write first, No change
mode)
When cascade but not in RF mode
551.27 493.93 408.00 408.00 MHz
FMAX_CAS_RF_PERFORMANCE Block RAM Cascade (Read first,
Performance mode)
When in cascade with RF mode and no
possibility of address overlap/one port is
disabled
551.27 493.93 408.00 408.00 MHz
FMAX_CAS_RF_DELAYED_WRITE When in cascade RF mode and there is a
possibility of address overlap between port A
and port B
478.24 427.35 350.88 350.88 MHz
FMAX_FIFO FIFO in all modes without ECC 601.32 543.77 458.09 458.09 MHz
FMAX_ECC Block RAM and FIFO in ECC configuration 484.26 430.85 351.12 351.12 MHz
Notes:
1. The timing report shows all of these parameters as TRCKO_DO.
2. TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters.
3. These parameters also apply to synchronous FIFO with DO_REG = 0.
4. TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters.
5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
6. TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR.
7. TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT.
8. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is
possible.
9. These parameters include both A and B inputs as well as the parity inputs of A and B.
10. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
11. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the
slowest clock (WRCLK or RDCLK).
Table 69: Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol Description Speed Grade Units
-3E -2E/-2I/-2LI -1C/-1I -1Q/-1LQ
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Product Specification 58
DSP48E1 Switching Characteristics
Table 70: DSP48E1 Switching Characteristics
Symbol Description Speed Grade Units
-3E -2E/-2I/-2LI -1C/-1I -1Q/-1LQ
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_A_AREG/ TDSPCKD_A_AREG A input to A register CLK 0.24/0.12 0.27/0.14 0.31/0.16 0.33/0.18 ns
TDSPDCK_B_BREG/TDSPCKD_B_BREG B input to B register CLK 0.28/0.13 0.32/0.14 0.39/0.15 0.41/0.18 ns
TDSPDCK_C_CREG/TDSPCKD_C_CREG C input to C register CLK 0.15/0.15 0.17/0.17 0.20/0.20 0.20/0.22 ns
TDSPDCK_D_DREG/TDSPCKD_D_DREG D input to D register CLK 0.21/0.19 0.27/0.22 0.35/0.26 0.35/0.27 ns
TDSPDCK_ACIN_AREG/TDSPCKD_ACIN_AREG ACIN input to A register CLK 0.21/0.12 0.24/0.14 0.27/0.16 0.30/0.16 ns
TDSPDCK_BCIN_BREG/TDSPCKD_BCIN_BREG BCIN input to B register CLK 0.22/0.13 0.25/0.14 0.30/0.15 0.32/0.15 ns
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{A, B}_MREG_MULT/
TDSPCKD_{A, B}_MREG_MULT
{A, B} input to M register CLK
using multiplier
2.04/–0.01 2.34/–0.01 2.79/–0.01 2.79/–0.01 ns
TDSPDCK_{A, D}_ADREG/
TDSPCKD_{A, D}_ADREG
{A, D} input to AD register CLK 1.09/–0.02 1.25/–0.02 1.49/–0.02 1.49/–0.02 ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{A, B}_PREG_MULT/
TDSPCKD_{A, B}_PREG_MULT
{A, B} input to P register CLK
using multiplier
3.41/–0.24 3.90/–0.24 4.64/–0.24 4.64/–0.24 ns
TDSPDCK_D_PREG_MULT/
TDSPCKD_D_PREG_MULT
D input to P register CLK using
multiplier
3.33/–0.62 3.81/–0.62 4.53/–0.62 4.53/–0.62 ns
TDSPDCK_{A, B}_PREG/
TDSPCKD_{A, B}_PREG
A or B input to P register CLK
not using multiplier
1.47/–0.24 1.68/–0.24 2.00/–0.24 2.00/–0.24 ns
TDSPDCK_C_PREG/ TDSPCKD_C_PREG C input to P register CLK not
using multiplier
1.30/–0.22 1.49/–0.22 1.78/–0.22 1.78/–0.22 ns
TDSPDCK_PCIN_PREG/ TDSPCKD_PCIN_PREG PCIN input to P register CLK 1.12/–0.13 1.28/–0.13 1.52/–0.13 1.52/–0.13 ns
Setup and Hold Times of the CE Pins
TDSPDCK_{CEA, CEB}_{AREG, BREG}/
TDSPCKD_{CEA, CEB}_{AREG, BREG}
{CEA; CEB} input to {A; B}
register CLK
0.30/0.05 0.36/0.06 0.44/0.09 0.44/0.09 ns
TDSPDCK_CEC_CREG/ TDSPCKD_CEC_CREG CEC input to C register CLK 0.24/0.08 0.29/0.09 0.36/0.11 0.36/0.11 ns
TDSPDCK_CED_DREG/ TDSPCKD_CED_DREG CED input to D register CLK 0.31/–0.02 0.36/–0.02 0.44/–0.02 0.44/0.02 ns
TDSPDCK_CEM_MREG/ TDSPCKD_CEM_MREG CEM input to M register CLK 0.26/0.15 0.29/0.17 0.33/0.20 0.33/0.20 ns
TDSPDCK_CEP_PREG/ TDSPCKD_CEP_PREG CEP input to P register CLK 0.31/0.01 0.36/0.01 0.45/0.01 0.45/0.01 ns
Setup and Hold Times of the RST Pins
TDSPDCK_{RSTA, RSTB}_{AREG, BREG}/
TDSPCKD_{RSTA, RSTB}_{AREG, BREG}
{RSTA, RSTB} input to {A, B}
register CLK
0.34/0.10 0.39/0.11 0.47/0.13 0.47/0.14 ns
TDSPDCK_RSTC_CREG/ TDSPCKD_RSTC_CREG RSTC input to C register CLK 0.06/0.22 0.07/0.24 0.08/0.26 0.08/0.26 ns
TDSPDCK_RSTD_DREG/ TDSPCKD_RSTD_DREG RSTD input to D register CLK 0.37/0.06 0.42/0.06 0.50/0.07 0.50/0.07 ns
TDSPDCK_RSTM_MREG/ TDSPCKD_RSTM_MREG RSTM input to M register CLK 0.18/0.18 0.20/0.21 0.23/0.24 0.23/0.24 ns
TDSPDCK_RSTP_PREG/ TDSPCKD_RSTP_PREG RSTP input to P register CLK 0.24/0.01 0.26/0.01 0.30/0.01 0.30/0.11 ns
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_A_CARRYOUT_MULT A input to CARRYOUT output
using multiplier
3.21 3.69 4.39 4.39 ns
TDSPDO_D_P_MULT D input to P output using
multiplier
3.15 3.61 4.30 4.30 ns
(I XILINXe W Send Feed back
Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics
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Product Specification 59
TDSPDO_A_P A input to P output not using
multiplier
1.30 1.48 1.76 1.76 ns
TDSPDO_C_P C input to P output 1.13 1.30 1.55 1.55 ns
Combinatorial Delays from Input Pins to Cascading Output Pins
TDSPDO_{A; B}_{ACOUT; BCOUT} {A, B} input to {ACOUT,
BCOUT} output
0.47 0.53 0.63 0.63 ns
TDSPDO_{A, B}_CARRYCASCOUT_MULT {A, B} input to
CARRYCASCOUT output using
multiplier
3.44 3.94 4.69 4.69 ns
TDSPDO_D_CARRYCASCOUT_MULT D input to CARRYCASCOUT
output using multiplier
3.36 3.85 4.58 4.58 ns
TDSPDO_{A, B}_CARRYCASCOUT {A, B} input to
CARRYCASCOUT output not
using multiplier
1.50 1.72 2.04 2.04 ns
TDSPDO_C_CARRYCASCOUT C input to CARRYCASCOUT
output
1.34 1.53 1.83 1.83 ns
Combinatorial Delays from Cascading Input Pins to All Output Pins
TDSPDO_ACIN_P_MULT ACIN input to P output using
multiplier
3.09 3.55 4.24 4.24 ns
TDSPDO_ACIN_P ACIN input to P output not using
multiplier
1.16 1.33 1.59 1.59 ns
TDSPDO_ACIN_ACOUT ACIN input to ACOUT output 0.32 0.37 0.45 0.45 ns
TDSPDO_ACIN_CARRYCASCOUT_MULT ACIN input to
CARRYCASCOUT output using
multiplier
3.30 3.79 4.52 4.52 ns
TDSPDO_ACIN_CARRYCASCOUT ACIN input to
CARRYCASCOUT output not
using multiplier
1.37 1.57 1.87 1.87 ns
TDSPDO_PCIN_P PCIN input to P output 0.94 1.08 1.29 1.29 ns
TDSPDO_PCIN_CARRYCASCOUT PCIN input to
CARRYCASCOUT output
1.15 1.32 1.57 1.57 ns
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_P_PREG CLK PREG to P output 0.33 0.35 0.39 0.39 ns
TDSPCKO_CARRYCASCOUT_PREG CLK PREG to
CARRYCASCOUT output
0.44 0.50 0.59 0.59 ns
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_P_MREG CLK MREG to P output 1.42 1.64 1.96 1.96 ns
TDSPCKO_CARRYCASCOUT_MREG CLK MREG to
CARRYCASCOUT output
1.63 1.87 2.24 2.24 ns
TDSPCKO_P_ADREG_MULT CLK ADREG to P output using
multiplier
2.30 2.63 3.13 3.13 ns
TDSPCKO_CARRYCASCOUT_ADREG_MULT CLK ADREG to
CARRYCASCOUT output using
multiplier
2.51 2.87 3.41 3.41 ns
Table 70: DSP48E1 Switching Characteristics (Cont’d)
Symbol Description Speed Grade Units
-3E -2E/-2I/-2LI -1C/-1I -1Q/-1LQ
(I XILINXe W Send Feed back
Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics
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Product Specification 60
Clock to Outs from Input Register Clock to Output Pins
TDSPCKO_P_AREG_MULT CLK AREG to P output using
multiplier
3.34 3.83 4.55 4.55 ns
TDSPCKO_P_BREG CLK BREG to P output not
using multiplier
1.39 1.59 1.88 1.88 ns
TDSPCKO_P_CREG CLK CREG to P output not
using multiplier
1.43 1.64 1.95 1.95 ns
TDSPCKO_P_DREG_MULT CLK DREG to P output using
multiplier
3.32 3.80 4.51 4.51 ns
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUT; BCOUT}_{AREG; BREG} CLK (ACOUT, BCOUT) to {A,B}
register output
0.55 0.62 0.74 0.74 ns
TDSPCKO_CARRYCASCOUT_{AREG, BREG}_MULT CLK (AREG, BREG) to
CARRYCASCOUT output using
multiplier
3.55 4.06 4.84 4.84 ns
TDSPCKO_CARRYCASCOUT_BREG CLK BREG to
CARRYCASCOUT output not
using multiplier
1.60 1.82 2.16 2.16 ns
TDSPCKO_CARRYCASCOUT_DREG_MULT CLK DREG to
CARRYCASCOUT output using
multiplier
3.52 4.03 4.79 4.79 ns
TDSPCKO_CARRYCASCOUT_CREG CLK CREG to
CARRYCASCOUT output
1.64 1.88 2.23 2.23 ns
Maximum Frequency
FMAX With all registers used 741.84 650.20 547.95 547.95 MHz
FMAX_PATDET With pattern detector 627.35 549.75 463.61 463.61 MHz
FMAX_MULT_NOMREG Two register multiply without
MREG
412.20 360.75 303.77 303.77 MHz
FMAX_MULT_NOMREG_PATDET Two register multiply without
MREG with pattern detect
374.25 327.65 276.01 276.01 MHz
FMAX_PREADD_MULT_NOADREG Without ADREG 468.82 408.66 342.70 342.70 MHz
FMAX_PREADD_MULT_NOADREG_PATDET Without ADREG with pattern
detect
468.82 408.66 342.70 342.70 MHz
FMAX_NOPIPELINEREG Without pipeline registers
(MREG, ADREG)
306.84 267.81 225.02 225.02 MHz
FMAX_NOPIPELINEREG_PATDET Without pipeline registers
(MREG, ADREG) with pattern
detect
285.23 249.13 209.38 209.38 MHz
Table 70: DSP48E1 Switching Characteristics (Cont’d)
Symbol Description Speed Grade Units
-3E -2E/-2I/-2LI -1C/-1I -1Q/-1LQ
(I XILINXe W Send Feed back
Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics
DS191 (v1.18.1) July 2, 2018 www.xilinx.com
Product Specification 61
Clock Buffers and Networks
Table 71: Global Clock Switching Characteristics (Including BUFGCTRL)
Symbol Description Speed Grade Units
-3E -2E/-2I/-2LI -1C/-1I -1Q/-1LQ
TBCCCK_CE/TBCCKC_CE(1) CE pins setup/hold 0.12/0.30 0.14/0.38 0.26/0.38 0.26/0.92 ns
TBCCCK_S/TBCCKC_S(1) S pins setup/hold 0.12/0.30 0.14/0.38 0.26/0.38 0.26/0.92 ns
TBCCKO_O(2) BUFGCTRL delay from I0/I1 to O 0.08 0.10 0.12 0.12 ns
Maximum Frequency
FMAX_BUFG Global clock tree (BUFG) 741.00 710.00 625.00 625.00 MHz
Notes:
1. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are
optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between
clocks.
2. TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values.
Table 72: Input/Output Clock Switching Characteristics (BUFIO)
Symbol Description Speed Grade Units
-3E -2E/-2I/-2LI -1C/-1I -1Q/-1LQ
TBIOCKO_O Clock to out delay from I to O 1.04 1.14 1.32 1.32 ns
Maximum Frequency
FMAX_BUFIO I/O clock tree (BUFIO) 800.00 800.00 710.00 710.00 MHz
Table 73: Regional Clock Buffer Switching Characteristics (BUFR)
Symbol Description Speed Grade Units
-3E -2E/-2I/-2LI -1C/-1I -1Q/-1LQ
TBRCKO_O Clock to out delay from I to O 0.60 0.65 0.77 0.77 ns
TBRCKO_O_BYP Clock to out delay from I to O with Divide
Bypass attribute set
0.30 0.32 0.38 0.38 ns
T