ams Datasheet Page 1
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TCS3471
Color Light-to-Digital Converter
The TCS3471 family of devices provides red, green, blue, and
clear light sensing (RGBC) that detects light intensity under a
variety of lighting conditions and through a variety of
attenuation materials. An internal state machine provides the
ability to put the device into a low power mode in between
RGBC measurements providing very low average power
consumption.
The TCS3471 is directly useful in lighting conditions containing
minimal IR content such as LED RGB backlight control, reflected
LED color sampler, or fluorescent light color temperature
detector. With the addition of an IR blocking filter, the device is
an excellent ambient light sensor, color temperature monitor,
and general purpose color sensor.
Ordering Information and Content Guide appear at end of
datasheet.
Key Benefits & Features
The benefits and features of TCS3471, Color Light-to-Digital
Converter are listed below:
Figure 1:
Added Value Of Using TCS3471
Color Light Sensing
Programmable Analog Gain, Integration Time, and
Interrupt Function with Upper and Lower Thresholds
Resolution Up to 16 Bits
Very High Sensitivity - Ideally Suited for Operation
Behind Dark Glass
Up to 1,000,000:1 Dynamic Range
Benefits Features
Enables Accurate Color and Ambient Light
Sensing Under Varying Lighting Conditions 1M:1 Dynamic Range
Minimizes Motion / Transient Errors Four Independent Analog-to-Digital Converters
Clear-Channel Provides a Reference Allows for
Isolation of Color Content
A Reference-Channel for Color Analysis (Clear Channel
Photo-diode)
Reduces Micro-Processor Interrupt Overhead Programmable Interrupt Function
Reduces Board Space Requirements While
Simplifying Designs
Area Efficient 2mm x 2.4mm Dual Flat No-Lead (FN)
Package
General Description
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TCS3471 − General Description
Low Power Wait State
•65 μA Typical Current
Wait Timer is Programmable from
2.4 ms to > 7seconds
Sleep Mode - 2.5 μA Typical Current
I²C Interface Compatible
Up to 400 kHz (I²C Fast Mode)
Dedicated Interrupt Pin
Pin and Register Set Compatible with the TCS3x7x Family
of Devices
Applications
TCS3471, Color Light-to-Digital Converter is ideal for:
Color Temperature Sensing
RGB LED Backlight Control
Color Display Closed-Loop Feedback Control
Ambient Light Sensing for Display Brightness Control
Industrial Process Control
Medical Diagnostics
End Products and Market Segments
HDTVs, Mobile Handsets, Tablets, Laptops, Monitors, PMP
(Portable Media Payers)
Medical Instrumentation
Consumer Toys
Industrial/Commercial Lighting
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TCS3471 − General Description
Functional Block Diagram
The functional blocks of this device are shown below:
Figure 2:
TCS3471 Block Diagram
SDA
VDD
INT
SCL
Wait Control
Clear ADC
Upper Limit
Lower Limit
Interrupt
I2C Interface
GND
Red ADC
Green ADC
Blue ADC
Clear Data
Red Data
Green Data
Blue Data
RGBC Control
Blue
Green
Red
Clear
VDD 1 SCL 2 GND 3 5 INT 4 NC
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TCS3471 − Pin Assignments
Figure 3:
Package FN Dual Flat No-Lead (Top View)
Figure 4:
Terminal Functions
Pin Diagram:
Package Drawing Not to Scale
Terminal Type Description
Name No.
VDD 1 Supply voltage.
SCL 2 I I²C Serial clock input terminal - clock signal for I²C serial data.
GND 3 Power supply ground. All voltages are referenced to GND.
NC 4 Do not connect
INT 5 O Interrupt - open drain.
SDA 6 I/O I²C Serial data I/O terminal - serial data I/O for I²C.
Pin Assignments
VDD 1
SCL 2
GND 3
6 SDA
5 INT
4 NC
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TCS3471 − Detailed Description
The TCS3471 light-to-digital device contains a 4 × 4 photodiode
array, integrating amplifiers, ADCs, accumulators, clocks,
buffers, comparators, a state machine, and an I²C interface. The
4 × 4 photodiode array is composed of red-filtered,
green-filtered, blue-filtered, and clear photodiodes — four of
each type. Four integrating ADCs simultaneously convert the
amplified photodiode currents to a digital value providing up
to 16 bits of resolution. Upon completion of the conversion
cycle, the conversion result is transferred to the data registers.
The transfers are double-buffered to ensure that the integrity
of the data is maintained. Communication to the device is
accomplished through a fast (up to 400 kHz), two-wire I²C serial
bus for easy connection to a microcontroller or embedded
controller.
The TCS3471 provides a separate pin for level-style interrupts.
When interrupts are enabled and a pre-set value is exceeded,
the interrupt pin is asserted and remains asserted until cleared
by the controlling firmware. The interrupt feature simplifies and
improves system efficiency by eliminating the need to poll a
sensor for a light intensity value. An interrupt is generated when
the value of an RGBC conversion exceeds either an upper or
lower threshold. In addition, a programmable interrupt
persistence feature allows the user to determine how many
consecutive exceeded thresholds are necessary to trigger an
interrupt.
Detailed Description
I |
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TCS3471Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under
Recommended Operating Conditions is not implied. Exposure
to absolute-maximum-rated conditions for extended periods
may affect device reliability.
Figure 5:
Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)
Note(s):
1. All voltages are with respect to GND.
Figure 6:
Recommended Operating Conditions
Symbol Parameter Min Max Units
VDD(1) Supply voltage 3.8 V
VODigital output voltage range -0.5 3.8 V
IODigital output current -1 20 mA
TSTRG Storage temperature range -40 85 ºC
ESDHBM ESD tolerance, human body model ±2000 V
Symbol Parameter Min Nom Max Unit
VDD Supply voltage 2.7 3 3.3 V
TAOperating free-air temperature -30 70 ºC
Absolute Maximum Ratings
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TCS3471 − Absolute Maximum Ratings
Figure 7:
Operating Characteristics; VDD = 3 V, TA = 25ºC (unless otherwise noted)
Figure 8:
Optical Characteristics; VDD = 3 V, TA = 25ºC, GAIN = 16, ATIME = 0xF6 (unless otherwise noted)
Note(s):
1. The percentage shown represents the ratio of the respective red, green, or blue channel value to the clear channel value.
2. The 465 nm input irradiance is supplied by an InGaN light-emitting diode with the following characteristics:
dominant wavelength λD = 465 nm, spectral halfwidth Δλ½ = 22 nm, and luminous efficacy = 75 lm/W.
3. The 525 nm input irradiance is supplied by an InGaN light-emitting diode with the following characteristics:
dominant wavelength λD = 525 nm, spectral halfwidth Δλ½ = 35 nm, and luminous efficacy = 520 lm/W.
4. The 625 nm input irradiance is supplied by a AlInGaP light-emitting diode with the following characteristics:
dominant wavelength λD = 625 nm, spectral halfwidth Δλ½ = 9 nm, and luminous efficacy = 155 lm/W.
Symbol Parameter Test Conditions Min Typ Max Unit
IDD Supply current
Active 235 330
μA Wait mode 65
Sleep mode - no I²C activity 2.5 10
VOL INT, SDA output low
voltage
3 mA sink current 0 0.4
V
6 mA sink current 0 0.6
ILEAK Leakage current, SDA,
SCL, INT pins −5 5 μA
ILEAK Leakage current, LDR
pin -1 +10 μA
VIH SCL, SDA input high
voltage
TCS34711 & TCS34715 0.7 VDD
V
TCS34713 & TCS34717 1.25
VIL SCL, SDA input low
voltage
TCS34711 & TCS34715 0.3 VDD
V
TCS34713 & TCS34717 0.54
Parameter Test
Conditions
Red
Channel Green
Channel Blue
Channel Clear Channel Unit
Min Max Min Max Min Max Min Typ Max
R
e
Irradiance
responsivtiy
λ
D
= 465 nm
(2)
0% 15% 10% 42% 65% 88% 19.2 24 28.8
counts/
(
μ
W/cm
2
)
λ
D
= 525 nm
(3)
8% 25% 60% 85% 9% 35% 22.4 28 33.6
λ
D
= 625 nm
(4)
85% 110% 0% 15% 5% 25% 27.2 34 40.8
| |
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TCS3471Absolute Maximum Ratings
Figure 9:
RGBC Characteristics; VDD = 3 V, TA = 2C, AGAIN = 16, AEN = 1 (unless otherwise noted)
Figure 10:
Wait Characteristics; VDD = 3 V, TA = 25ºC, Gain = 16, WEN = 1 (unless otherwise noted)
Parameter Test Conditions Min Typ Max Unit
Dark ADC count value Ee = 0, AGAIN = 60×, ATIME= 0xD6
(100 ms) 0 1 5 counts
ADC integration time step
size ATIME = 0xFF 2.27 2.4 2.56 ms
ADC number of integration
steps 1 256 steps
ADC counts per step 0 1024 counts
ADC count value ATIME = 0xC0 (153.6 ms) 0 65535 counts
Gain scaling, relative to 1×
gain setting
4× 3.8 4 4.2
%16× 15 16 16.8
60× 58 60 63
Parameter Test
Conditions Channel Min Typ Max Unit
Wait step size WTIME = 0xFF 2.27 2.4 2.56 ms
Wait number steps 1 256 steps
ams Datasheet Page 9
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TCS3471 − Absolute Maximum Ratings
Figure 11:
AC Electrical Characteristics; VDD = 3 V, TA = 2C, (unless otherwise noted)
Note(s):
1. Specified by design and characterization; not production tested.
Symbol Parameter(1) Test
Conditions Min Typ Max Unit
f(SCL) Clock frequency (I²C) 0 400 kHz
t(BUF) Bus free time between start and stop
condition 1.3 μs
t(HDSTA)
Hold time after (repeated) start
condition. After this period, the first
clock is generated.
0.6 μs
t(SUSTA) Repeated start condition setup time 0.6 μs
t(SUSTO) Stop condition setup time 0.6 μs
t(HDDAT) Data hold time 0 μs
t(SUDAT) Data setup time 100 ns
t(LOW) SCL clock low period 1.3 μs
t(HIGH) SCL clock high period 0.6 μs
tF Clock/data fall time 300 ns
tR Clock/data rise time 300 ns
Ci Input pin capacitance 10 pF
Condition Stan 513.1 147 ‘Awwsixn4‘ scLACK m w momma-<7 «low="" w="" scl="" mul—="" jl="" jl="">
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TCS3471Absolute Maximum Ratings
Parameter Measurement Information
Figure 12:
Timing Diagrams
SDA
SCL
StopStart
SCL
ACK
t
(LOWMEXT)
t
(LOWMEXT)
t
(LOWSEXT)
SCL
ACK
t
(LOWMEXT)
Start
Condition
Stop
Condition
P
SDA
t
(SUSTO)
t
(SUDAT)
t
(HDDAT)
t
(BUF)
V
IH
V
IL
SCL
t
(SUSTA)
t
(HIGH)
t
(F)
t
(R)
t
(HDSTA)
t
(LOW)
V
IH
V
IL
PSS
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TCS3471 − Typical Operating Characteristics
Figure 13:
Photodiode Spectral Responsivity
Figure 14:
Normalized IDD vs.VDD and Temperature
Typical Operating
Characteristics
300 500 700 900
Relative Responsivity
1100
λ − Wavelength − nm
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0
TA = 25°C
Normalized to
Clear
@ 755 nm
Red
Blue
Green
Clear
VDD
and
TEMPERATURE
VDD — V
94%
96%
98%
100%
102%
104%
106%
108%
110%
92%
2.7 2.8 2.9 3 3.1 3.2 3.3
75C
50C 25C
0C
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TCS3471 − Typical Operating Characteristics
Figure 15:
Normalized Responsivity vs. Angular Displacement
Figure 16:
Responsivity Temperature Coefficient
Q − Angular Displacement − °
Normalized Responsivity
0
0.2
0.4
0.6
0.8
1.0
−90 −60 −30 0 30 60 90
Optical Axis
-Q +Q
400 600 800 1000
Temperature Coefficient — ppm/ C
100
1000
10,000
500 700 900
λ − Wavelength − nm
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TCS3471 − Principles Of Operation
System State Machine
The TCS3471 provides control of RGBC and power management
functionality through an internal state machine (Figure 17).
After a power-on-reset, the device is in the sleep mode. As soon
as the PON bit is set, the device will move to the start state. It
will then continue through the Wait and RGBC states. If these
states are enabled, the device will execute each function. If the
PON bit is set to 0, the state machine will continue until all
conversions are completed and then go into a low power sleep
mode.
Figure 17:
Simplified State Diagram
Note(s): In this document, the nomenclature uses the bit field
name in italics followed by the register number and bit number
to allow the user to easily identify the register and bit that
controls the function. For example, the power on (PON) is in
register 0, bit 0. This is represented as PON (r0:b0).
Principles Of Operation
Sleep
Start
RGBC
Wait
PON = 1 (r0:b0) PON = 0 (r0:b0)
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TCS3471 − Principles Of Operation
RGBC Operation
The RGBC engine contains RGBC gain control (AGAIN) and four
integrating analog-to-digital converters (ADC) for the RGBC
photodiodes. The RGBC integration time (ATIME) impacts both
the resolution and the sensitivity of the RGBC reading.
Integration of all four channels occurs simultaneously and upon
completion of the conversion cycle, the results are transferred
t o th e c o l or d a t a re g i st e rs . T hi s d at a i s al s o re f e rr ed t o a s c ha n ne l
count.
The transfers are double-buffered to ensure that invalid data is
not read during the transfer. After the transfer, the device
automatically moves to the next state in accordance with the
configured state machine.
Figure 18:
RGBC Operation
The registers for programming the integration and wait times
are a 2’s compliment values. The actual time can be calculated
as follows:
ATIME = 256 - Integration Time / 2.4 ms
Inversely, the time can be calculated from the register value as
follows:
Integration Time = 2.4 ms × (256 - ATIME)
For example, if a 100ms integration time is needed, the device
needs to be programmed to:
256 - (100 / 2.4) = 256 - 42 = 214 = 0xD6
Conversely, the programmed value of 0xC0 would correspond
to:
(256 - 0xC0) × 2.4 = 64 × 2.4 = 154 ms.
AGAIN(r 0x0F, b1:0)
1, 4, 16, 60 Gain
CDATAH(r0x15), CDATA(r 0x14)
Clear ADC
Red ADC
Green ADC
Blue ADC
Clear Data
Red Data
Green Data
Blue Data
RGBC Control
Blue
Green
Red
Clear
RDATAH(r0x17), RDATA(r 0x16)
GDATAH(r0x19), GDATA(r 0x18)
BDATAH(r0x1B), BDATA(r 0x1A)
ATIME(r 1)
2.4 ms to 700 ms
(EQ1)
(EQ2)
A!
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TCS3471 − Principles Of Operation
Interrupts
The interrupt feature simplifies and improves system efficiency
by eliminating the need to poll the sensor for light intensity
values outside of a user-defined range. While the interrupt
function is always enabled and its status is available in the
status register (0x13), the output of the interrupt state can be
enabled using the RGBC interrupt enable (AIEN) field in the
enable register (0x00).
Two 16-bit interrupt threshold registers allow the user to set
limits below and above a desired light level range. An interrupt
can be generated when the RGBC Clear data (CDATA) falls
outside of the desired light level range, as determined by the
values in the RGBC interrupt low threshold registers (AILTx) and
RGBC interrupt high threshold registers (AIHTx). It is important
to note that the low threshold value must be less than the high
threshold value for proper operation.
To further control when an interrupt occurs, the device provides
a persistence filter. The persistence filter allows the user to
specify the number of consecutive out-of-range RGBC
occurrences before an interrupt is generated. The persistence
register (0x0C) allows the user to set the persistence (APERS)
value. See the Persistence Register (0x0C) for details on the
persistence filter values. Once the persistence filter generates
an interrupt, it will continue until a special function interrupt
clear command is received (see Command Register).
Figure 19:
Programmable Interrupt
Clear
ADC
Clear
Data
Clear
Upper Limit
Lower Limit
AIHTH(r 07), AIHTL(r 06)
RGBC Persistence
AILTH(r 05), AILTL(r 04)
PPERS(r 0x0C, b3:0)
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State Diagram
Figure 20 shows a more detailed flow for the state machine. The
device starts in the sleep mode. The PON bit is written to enable
the device. A 2.4ms delay will occur before entering the start
state. If the WEN bit is set, the state machine will cycle through
the wait state. If the WLONG bit is set, the wait cycles are
extended by 12× over normal operation. When the wait counter
terminates, the state machine will step to the RGBC state.
The AEN should always be set. In this case, a minimum of 1
integration time step should be programmed. The RGBC state
machine will continue until it reaches the terminal count, at
which point the data will be latched in the RGBC register and
the interrupt set, if enabled.
Figure 20:
Expanded State Diagram
Wait
Check
PON = 1 PON = 0
Sleep
ALS
Check
Wait
Start
WEN = 1
ALS
ALS
Delay
AEN = 1
1 to 256steps
Step: 2.4 ms
Time: 2.4 ms − 614 ms
WLONG = 0
1 to 256 steps
Step: 2.4 ms
Time: 2.4 ms − 614 ms
Minimum − 2.4 ms
WLONG = 1
1 to 256 steps
Step: 29 ms
Time: 29 ms − 7.4 s
Minimum − 29 ms Time: 2.4 ms
I26 Read Protocol — Combined Forma EIEI
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TCS3471 − Principles Of Operation
I²C Protocols
Interface and control are accomplished through an I²C serial
compatible interface (standard or fast mode) to a set of registers
that provide access to device control functions and output data.
The devices support the 7-bit I²C addressing protocol.
The I²C standard provides for three types of bus transaction:
read, write, and a combined protocol (Figure 21). During a write
operation, the first byte written is a command byte followed by
data. In a combined protocol, the first byte written is the
command byte followed by reading a series of bytes. If a read
command is issued, the register address from the previous
command will be used for data access. Likewise, if the MSB of
the command is not set, the device will write a series of bytes
at the address stored in the last valid command with a register
address. The command byte contains either control information
or a 5-bit register address. The control commands can also be
used to clear interrupts.
The I²C bus protocol was developed by Philips (now NXP). For
a complete description of the I²C protocol, please review the
NXP I²C design specification at
http://www.i2c-bus.org/references/.
Figure 21:
I²C Protocols
W
7
Data ByteSlave AddressS
1
AAA
811 1 8
Command Code
1
P
1
...
I2C Write Protocol
I2C Read Protocol
I2C Read Protocol — Combined Format
R
7
DataSlave AddressS
1
AAA
811 1 8
Data
1
P
1
...
W
7
Slave AddressSlave AddressS
1
ARA
811 1 7 11
Command Code Sr
1
A
Data AA
81 8
Data
1
P
1
...
AAcknowledge (0)
NNot Acknowledged (1)
PStop Condition
RRead (1)
SStart Condition
Sr Repeated Start Condition
WWrite (0)
... Continuation of protocol
Master-to-Slave
Slave-to-Master
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TCS3471 − Register Description
The TCS3471 is controlled and monitored by data registers and
a command register accessed through the serial interface.
These registers provide for a variety of control functions and
can be read to determine results of the ADC conversions. The
register set is summarized in Figure 22.
Figure 22:
Register Set
The mechanics of accessing a specific register depends on the
specific protocol used. See the section on I²C protocols on the
previous pages. In general, the COMMAND register is written
first to specify the specific control/status register for the
following read/write operations.
Address Register Name R/W Register Function Reset Value
−− COMMAND W Specifies register address 0x00
0x00 ENABLE R/W Enables states and interrupts 0x00
0x01 ATIME R/W RGBC ADC time 0xFF
0x03 WTIME R/W Wait time 0xFF
0x04 AILTL R/W RGBC interrupt low threshold low byte 0x00
0x05 AILTH R/W RGBC interrupt low threshold high byte 0x00
0x06 AIHTL R/W RGBC interrupt high threshold low byte 0x00
0x07 AIHTH R/W RGBC interrupt high threshold high byte 0x00
0x0C PERS R/W Interrupt persistence filters 0x00
0x0D CONFIG R/W Configuration 0x00
0x0F CONTROL R/W Gain control register 0x00
0x12 ID R Device ID ID
0x13 STATUS R Device status 0x00
0x14 CDATA R Clear ADC low data register 0x00
0x15 CDATAH R Clear ADC high data register 0x00
0x16 RDATA R Red ADC low data register 0x00
0x17 RDATAH R Red ADC high data register 0x00
0x18 GDATA R Green ADC low data register 0x00
0x19 GDATAH R Green ADC high data register 0x00
0x1A BDATA R Blue ADC low data register 0x00
0x1B BDATAH R Blue ADC high data register 0x00
Register Description
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TCS3471 − Register Description
Command Register
The command registers specifies the address of the target
register for future write and read operations.
Figure 23:
Command Register
76543210
COMMAND TYPE ADD
Field Bits Description
COMMAND 7 Select Command Register. Must write as 1 when addressing COMMAND register.
TYPE 6:5 Selects type of transaction to follow in subsequent data transfers:
FIELD VALUE INTEGRATION TIME
00 Repeated byte protocol transaction
01 Auto-increment protocol transaction
10 Reserved — Do not use
11 Special function — See description below
Byte protocol will repeatedly read the same register with each data access.
Block protocol will provide auto-increment function to read successive bytes.
ADD 4:0 Address field/special function field. Depending on the transaction type, see above,
this field either specifies a special function command or selects the specific
control-status-register for following write and read transactions. The field values
listed below apply only to special function commands:
FIELD VALUE READ VALUE
00000 Normal — no action
00110 RGBC interrupt clear
other Reserved — Do not write
RGBC Interrupt Clear. Clears any pending RGBC interrupt. This special function is
self clearing.
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TCS3471 − Register Description
Enable Register (0x00)
The Enable register is used primarily to power the TCS3471
device on and off, and enable functions and interrupts as shown
in Figure 24.
Figure 24:
Enable Register
Note(s):
1. A minimum interval of 2.4 ms must pass after PON is asserted before an RGBC can be initiated.
76543210
Reserved AIEN WEN Reserved AEN PON
Field Bits Description
Reserved 7:5 Reserved. Write as 0.
AIEN 4
RGBC interrupt enable. When asserted, permits RGBC interrupts to be
generated.
WEN 3
Wait enable. This bit activates the wait feature. Writing a 1 activates the
wait timer. Writing a 0 disables the wait timer.
Reserved 2 Reserved. Write as 0.
AEN 1
RGBC enable. This bit actives the two-channel ADC. Writing a 1 activates
the RGBC. Writing a 0 disables the RGBC.
PON(1) 0
Power ON. This bit activates the internal oscillator to permit the timers and
ADC channels to operate. Writing a 1 activates the oscillator. Writing a 0
disables the oscillator. During reads and writes over the I²C interface, this
bit is temporarily overridden and the oscillator is enabled, independent of
the state of PON.
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TCS3471 − Register Description
RGBC Timing Register (0x01)
The RGBC timing register controls the internal integration time
of the RGBC clear and IR channel ADCs in 2.4 ms increments.
Max RGBC Count = (256 - ATIME) × 1024 up to a maximum of
65535.
Figure 25:
RGBC Timing Register
Wait Time Register (0x03)
Wait time is set 2.4 ms increments unless the WLONG bit is
asserted, in which case the wait times are 12x longer. WTIME is
programmed as a 2’s complement number.
Figure 26:
Wait Time Register
Field Bits Description
ATIME 7:0
VALUE INTEG_CYCLES TIME MAX COUNT
0xFF 1 2.4 ms 1024
0xF6 10 24 ms 10240
0xD5 42 101 ms 43008
0xC0 64 154 ms 65535
0x00 256 700 ms 65535
Field Bits Description
WTIME 7:0
REGISTER
VALUE WAIT TIME TIME (WLONG = 0) TIME (WLONG = 1)
0xFF 1 2.4 ms 0.029 s
0xAB 85 204 ms 2.45 s
0x00 256 614 ms 7.4 s
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TCS3471 − Register Description
RGBC Interrupt Threshold Registers
(0x04 - 0x07)
The RGBC interrupt threshold registers provides the values to
be used as the high and low trigger points for the comparison
function for interrupt generation. If the value generated by the
clear channel crosses below the lower threshold specified, or
above the higher threshold, an interrupt is asserted on the
interrupt pin.
Figure 27:
RGBC Interrupt Threshold Register
Register Address Bits Description
AILTL 0x04 7:0 RGBC clear channel low threshold lower byte
AILTH 0x05 7:0 RGBC clear channel low threshold upper byte
AIHTL 0x06 7:0 RGBC clear channel high threshold lower byte
AIHTH 0x07 7:0 RGBC clear channel high threshold upper byte
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TCS3471 − Register Description
Persistence Register (0x0C)
The persistence register controls the filtering interrupt
capabilities of the device. Configurable filtering is provided to
allow interrupts to be generated after each integration cycle or
if the integration has produced a result that is outside of the
values specified by the threshold register for some specified
amount of time.
Figure 28:
Persistence Register
76 5 4321 0
Reserved APERS
Field Bits Description
Reserved 7:4 Reserved.
APERS 3:0
Interrupt persistence. Controls rate of interrupt to the host processor.
FIELD VALUE MEANING INTERRUPT PERSISTENCE FUNCTION
0000 Every Every RGBC cycle generates an interrupt
0001 1 1 clear channel value outside of threshold range
0010 2 2 clear channel consecutive values out of range
0011 3 3 clear channel consecutive values out of range
0100 5 5 clear channel consecutive values out of range
0101 10 10 clear channel consecutive values out of range
0110 15 15 clear channel consecutive values out of range
0111 20 20 clear channel consecutive values out of range
1000 25 25 clear channel consecutive values out of range
1001 30 30 clear channel consecutive values out of range
1010 35 35 clear channel consecutive values out of range
1011 40 40 clear channel consecutive values out of range
1100 45 45 clear channel consecutive values out of range
1101 50 50 clear channel consecutive values out of range
1110 55 55 clear channel consecutive values out of range
1111 60 60 clear channel consecutive values out of range
Page 24 ams Datasheet
Document Feedback [v1-01] 2018-Mar-27
TCS3471 − Register Description
Configuration Register (0x0D)
The configuration register sets the wait long time.
Figure 29:
Configuration Register
Control Register (0x0F)
The Control register provides eight bits of miscellaneous
control to the analog block. These bits typically control
functions such as gain settings and/or diode selection.
Figure 30:
Control Register
76 5 4321 0
Reserved WLONG Reserved
Field Bits Description
Reserved 7:2 Reserved. Write as 0.
WLONG 1
Wait Long. When asserted, the wait cycles are increased by a factor 12x from that
programmed in the WTIME register.
Reserved 0 Reserved. Write as 0.
76 5 4321 0
Reserved AGAIN
Field Bits Description
Reserved 7:2 Reserved. Write bits as 0
AGAIN 1:0
RGBC Gain Control.
FIELD VALUE RGBC GAIN VALUE
00 1x gain
01 4x gain
10 16x gain
11 60x gain
ams Datasheet Page 25
[v1-01] 2018-Mar-27 Document Feedback
TCS3471 − Register Description
ID Register (0x12)
The ID Register provides the value for the part number. The ID
register is a read-only register.
Figure 31:
ID Register
Status Register (0x13)
The Status Register provides the internal status of the device.
This register is read only.
Figure 32:
Status Register
76 5 4321 0
ID
Field Bit Description
ID 7:0 Part number identification
0x14 = TCS34711 & TCS34715
0x1D = TCS34713 & TCS34717
76 5 4321 0
Reserved AINT Reserved AVALID
Field Bit Description
Reserved 7:5 Reserved.
AINT 4 RGBC clear channel Interrupt.
Reserved 3:1 Reserved.
AVALID 0
RGBC Valid. Indicates that the RGBC channels have
completed an integration cycle.
Page 26 ams Datasheet
Document Feedback [v1-01] 2018-Mar-27
TCS3471 − Register Description
RGBC Channel Data Registers (0x14 - 0x1B)
Clear, red, green, and blue data is stored as 16-bit values. To
ensure the data is read correctly, a two-byte read I²C transaction
should be used with a read word protocol bit set in the
command register. With this operation, when the lower byte
register is read, the upper eight bits are stored into a shadow
register, which is read by a subsequent read to the upper byte.
The upper register will read the correct value even if additional
ADC integration cycles end between the reading of the lower
and upper registers.
Figure 33:
ADC Channel Data Registers
Register Address Bits Description
CDATA 0x14 7:0 Clear data low byte
CDATAH 0x15 7:0 Clear data high byte
RDATA 0x16 7:0 Red data low byte
RDATAH 0x17 7:0 Red data high byte
GDATA 0x18 7:0 Green data low byte
GDATAH 0x19 7:0 Green data high byte
BDATA 0x1A 7:0 Blue data low byte
BDATAH 0x1B 7:0 Blue data high byte
w
ams Datasheet Page 27
[v1-01] 2018-Mar-27 Document Feedback
TCS3471 − Application Information: Hardware
Typical Hardware Application
A typical hardware application circuit is shown in Figure 34.
A 1-μF low-ESR decoupling capacitor should be placed as close
as possible to the VDD pin.
Figure 34:
Typical Application Hardware Circuit
VBUS in Figure 34 refers to the I²C bus voltage, which is either
VDD or 1.8 V. Be sure to apply the specified I²C bus voltage shown
in the Available Options table for the specific device being used.
The I²C signals and the Interrupt are open-drain outputs and
require pull-up resistors. The pull-up resistor (RP) value is a
function of the I²C bus speed, the I²C bus voltage, and the
capacitive load. The ams EVM running at 400 kbps, uses 1.5-kΩ
resistors. A 10-kΩ pull-up resistor (RPI) can be used for the
interrupt line.
Application Information:
Hardware
TCS3471 INT
SDA
SCL
VDD
1 mF
GND
VBUS
RPRPRPI
VDD
Page 28 ams Datasheet
Document Feedback [v1-01] 2018-Mar-27
TCS3471 − Application I nformation: Hardware
PCB Pad Layouts
Suggested PCB pad layout guidelines for the Dual Flat No-Lead
(FN) surface mount package are shown in Figure 35.
Note(s): Pads can be extended further if hand soldering is
needed.
Figure 35:
Suggested FN Package PCB Layout
Note(s):
1. All linear dimensions are in micrometers.
2. This drawing is subject to change without notice.
400
2500
400
1000
1700
650
1000
650
r / ¢ 550 1 5n BOTTOM VIEW a! Phaladmde Avmy Area (Mme PIN ‘
ams Datasheet Page 29
[v1-01] 2018-Mar-27 Document Feedback
TCS3471 − Mechanical Data
Figure 36:
Package FN — Dual Flat No-Lead Packaging Configuration
Note(s):
1. All linear dimensions are in micrometers.
2. The die is centered within the package within a tolerance of ± 75 μm.
3. Package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.55.
4. Contact finish is copper alloy A194 with pre-plated NiPdAu lead finish.
5. This package contains no lead (Pb).
6. This drawing is subject to change without notice.
Mechanical Data
PACKAGE FN Dual Flat No-Lead
650
BSC
203 8
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Lead Fre
e
Pb
300
50
2000
75
2400 75
PIN 1
PIN 1
END VIEW
650 50
PIN OUT
TOP VIEW
750 100
295
Nominal
406
10
C
Lof Solder Contacts and
Photodiode Array Area (Note B)
C
Lof Solder Contacts
of Photodiode Array Area (Note B)
C
L
125 Nominal
6 SDA
5 INT
4 NC
VDD 1
SCL 2
GND 3
496 10
Photodiode Active Area
Green
RoHS
2
2
Page 30 ams Datasheet
Document Feedback [v1-01] 2018-Mar-27
TCS3471 − Mechanical Data
Figure 37:
Package FN Carrier Tape
Note(s):
1. All linear dimensions are in millimeters. Dimension tolerance is ±0.10 mm unless otherwise noted.
2. The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly.
3. Symbols on drawing Ao, Bo, and Ko are defined in ANSI EIA Standard 481-B 2001.
4. Each reel is 178 millimeters in diameter and contains 3500 parts.
5. ams packaging tape and reel conform to the requirements of EIA Standard 481-B.
6. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape.
7. This drawing is subject to change without notice.
Green
RoHS
TOP VIEW
DETAIL A
2.21 0.05
Ao
0.254
0.02
5 Max
4.00
8.00
3.50 0.05
1.50
4.00
2.00 0.05
+ 0.30
− 0.10
1.75
B
B
AA
0.50
0.05
DETAIL B
2.61 0.05
Bo
5 Max
0.83 0.05
Ko
ams Datasheet Page 31
[v1-01] 2018-Mar-27 Document Feedback
TCS3471 − Manufacturing Information
The FN package has been tested and has demonstrated an
ability to be reflow soldered to a PCB substrate.
The solder reflow profile describes the expected maximum heat
exposure of components during the solder reflow process of
product on a PCB. Temperature is measured on top of
component. The components should be limited to a maximum
of three passes through this solder reflow profile.
Figure 38:
Solder Reflow Profile
Figure 39:
Solder Reflow Profile Graph
Note(s):
1. Not to scale — for reference only
Parameter Reference Device
Average temperature gradient in preheating 2.5°C/s
Soak time tsoak 2 to 3 minutes
Time above 217°C (T1)t
1 Max 60 s
Time above 230°C (T2)t
2 Max 50 s
Time above Tpeak −10°C (T3)t
3 Max 10 s
Peak temperature in reflow Tpeak 260°C
Temperature gradient in cooling Max −5°C/s
Manufacturing Information
t3
t2
t1
tsoak
T3
T2
T1
Tpeak
Not to scale — for reference o
Time (s)
Temperature (C)
Page 32 ams Datasheet
Document Feedback [v1-01] 2018-Mar-27
TCS3471 − Manufacturing Information
Moisture Sensitivity
Optical characteristics of the device can be adversely affected
during the soldering process by the release and vaporization of
moisture that has been previously absorbed into the package.
To ensure the package contains the smallest amount of
absorbed moisture possible, each device is dry-baked prior to
being packed for shipping. Devices are packed in a sealed
aluminized envelope with silica gel to protect them from
ambient moisture during shipping, handling, and storage
before use.
The FN package has been assigned a moisture sensitivity level
of MSL 3 and the devices should be stored under the following
conditions:
Temperature Range: 5ºC to 50ºC
Relative Humidity: 60% maximum
Total Time: 12 months from the date code on the
aluminized envelope — if unopened
Opened Time: 168 hours or fewer
Rebaking will be required if the devices have been stored
unopened for more than 12 months or if the aluminized
envelope has been open for more than 168 hours. If rebaking
is required, it should be done at 50ºC for 12 hours.
ams Datasheet Page 33
[v1-01] 2018-Mar-27 Document Feedback
TCS3471 − Ordering & Contact Information
Figure 40:
Ordering Information
Buy our products or get free samples online at:
www.ams.com/ICdirect
Technical Support is available at:
www.ams.com/Technical-Support
Provide feedback about this document at:
www.ams.com/Document-Feedback
For further information and requests, e-mail us at:
ams_sales@ams.com
For sales offices, distributors and representatives, please visit:
www.ams.com/contact
Headquarters
ams AG
Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
Ordering Code Description Device Address Package - Leads
TCS34711FN I²C Vbus = VDD Interface TCS34711 0x39 FN−6
TCS34713FN I²C Vbus = 1.8 V Interface TCS34713 0x39 FN−6
TCS34715FN I²C Vbus = VDD Interface TCS34715 0x29 FN−6
TCS34717FN I²C Vbus = 1.8 V Interface TCS34717 0x29 FN−6
Ordering & Contact Information
Page 34 ams Datasheet
Document Feedback [v1-01] 2018-Mar-27
TCS3471 − RoHS Compliant & ams Green Statement
RoHS: The term RoHS compliant means that ams AG products
fully comply with current RoHS directives. Our semiconductor
products do not contain any chemicals for all 6 substance
categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to
be soldered at high temperatures, RoHS compliant products are
suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br): ams Green
defines that in addition to RoHS compliance, our products are
free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous
material).
Important Information: The information provided in this
statement represents ams AG knowledge and belief as of the
date that it is provided. ams AG bases its knowledge and belief
on information provided by third parties, and makes no
representation or warranty as to the accuracy of such
information. Efforts are underway to better integrate
information from third parties. ams AG has taken and continues
to take reasonable steps to provide representative and accurate
information but may not have conducted destructive testing or
chemical analysis on incoming materials and chemicals. ams AG
and ams AG suppliers consider certain information to be
proprietary, and thus CAS numbers and other limited
information may not be available for release.
RoHS Compliant & ams Green
Statement
ams Datasheet Page 35
[v1-01] 2018-Mar-27 Document Feedback
TCS3471 − Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten,
Austria-Europe. Trademarks Registered. All rights reserved. The
material herein may not be reproduced, adapted, merged,
translated, stored, or used without the prior written consent of
the copyright owner.
Devices sold by ams AG are covered by the warranty and patent
indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied,
or by description regarding the information set forth herein.
ams AG reserves the right to change specifications and prices
at any time and without notice. Therefore, prior to designing
this product into a system, it is necessary to check with ams AG
for current information. This product is intended for use in
commercial applications. Applications requiring extended
temperature range, unusual environmental requirements, or
high reliability applications, such as military, medical
life-support or life-sustaining equipment are specifically not
recommended without additional processing by ams AG for
each application. This product is provided by ams AG “AS IS”
and any express or implied warranties, including, but not
limited to the implied warranties of merchantability and fitness
for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any
damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interruption of business or
indirect, special, incidental or consequential damages, of any
kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation
or liability to recipient or any third party shall arise or flow out
of ams AG rendering of technical or other services.
Copyrights & Disclaimer
Page 36 ams Datasheet
Document Feedback [v1-01] 2018-Mar-27
TCS3471 − Document Status
Document Status Product Status Definition
Product Preview Pre-Development
Information in this datasheet is based on product ideas in
the planning phase of development. All specifications are
design goals without any warranty and are subject to
change without notice
Preliminary Datasheet Pre-Production
Information in this datasheet is based on products in the
design, validation or qualification phase of development.
The performance and parameters shown in this document
are preliminary without any warranty and are subject to
change without notice
Datasheet Production
Information in this datasheet is based on products in
ramp-up to full production or full production which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade
Datasheet (discontinued) Discontinued
Information in this datasheet is based on products which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade, but these products have been superseded and
should not be used for new designs
Document Status
ams Datasheet Page 37
[v1-01] 2018-Mar-27 Document Feedback
TCS3471 − Revision Information
Note(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision
2. Correction of typographical errors is not explicitly mentioned.
Changes from 1-00 (2016-May-23) to current revision 1-01 (2018-Mar-27) Page
Updated Figure 40 33
Revision Information
Page 38 ams Datasheet
Document Feedback [v1-01] 2018-Mar-27
TCS3471 − Content Guide
1 General Description
1 Key Benefits & Features
2 Applications
2 End Products and Market Segments
3 Functional Block Diagram
4 Pin Assignments
5 Detailed Description
6Absolute Maximum Ratings
10 Parameter Measurement Information
11 Typical Operating Characteristics
13 Principles Of Operation
13 System State Machine
14 RGBC Operation
15 Interrupts
16 State Diagram
17 I²C Protocols
18 Register Description
19 Command Register
20 Enable Register (0x00)
21 RGBC Timing Register (0x01)
21 Wait Time Register (0x03)
22 RGBC Interrupt Threshold Registers
(0x04 - 0x07)
23 Persistence Register (0x0C)
24 Configuration Register (0x0D)
24 Control Register (0x0F)
25 ID Register (0x12)
25 Status Register (0x13)
26 RGBC Channel Data Registers (0x14 - 0x1B)
27 Application Information: Hardware
27 Typical Hardware Application
28 PCB Pad Layouts
29 Mechanical Data
31 Manufacturing Information
32 Moisture Sensitivity
33 Ordering & Contact Information
34 RoHS Compliant & ams Green Statement
35 Copyrights & Disclaimer
36 Document Status
37 Revision Information
Content Guide

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