AD5243,48 Datasheet by Analog Devices Inc.

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ANALOG osition, PEI-Compatible DEVICES Digital Potentiometers A05243/A05248
Dual, 256-Position, I2C-Compatible
Digital Potentiometers
Data Sheet
AD5243/AD5248
Rev. C Document Feedback
Information
furnished by Analog Devices is believed to be accurate and reliable. However, no
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©20042016 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
2-channel, 256-position potentiometers
End-to-end resistance: 2.5 k, 10 k, 50 k, and 100 k
Compact 10-lead MSOP (3 mm × 4.9 mm) package
Fast settling time: tS = 5 µs typical on power-up
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pins: AD0 and AD1 (AD5248 only)
Computer software replaces microcontroller in factory
programming applications
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power: IDD = 6 µA maximum
Wide operating temperature: 40°C to +125°C
Evaluation board available
APPLICATIONS
Systems calibrations
Electronics level settings
Mechanical trimmers replacement in new designs
Permanent factory printed circuit board (PCB) setting
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Gain control and offset adjustment
FUNCTIONAL BLOCK DIAGRAMS
A1
V
DD
GND
SDA
SCL
W1
WIPER
REGISTER 1
PC INTERFACE
AD5243
04109-0-001
B1 A2 W2
WIPER
REGISTER 2
B2
Figure 1. AD5243
V
DD
GND
SDA
SCL
AD0
AD1
W1
RDAC
REGISTER 1
ADDRESS
DECODE
SERIAL INPUT
REGISTER
AD5248
B1 W2
RDAC
REGISTER 2
B2
/
8
04109-0-002
Figure 2. AD5248
GENERAL DESCRIPTION
The AD5243 and AD5248 provide a compact 3 mm × 4.9 mm
packaged solution for dual, 256-position adjustment applications.
The AD5243 performs the same electronic adjustment function
as a 3-terminal mechanical potentiometer, and the AD5248
performs the same adjustment function as a 2-terminal variable
resistor. Available in four end-to-end resistance values (2.5 kΩ,
10 kΩ, 50 kΩ, and 100 kΩ), these low temperature coefficient
devices are ideal for high accuracy and stability-variable
resistance adjustments. The wiper settings are controllable
through the I2C-compatible digital interface. The AD5248 has
extra package address decode pins, AD0 and AD1, allowing
multiple parts to share the same I2C, 2-wire bus on a PCB. The
resistance between the wiper and either endpoint of the fixed
resistor varies linearly with respect to the digital code transferred
into the RDAC latch. (The terms digital potentiometer, VR,
and RDAC are used interchangeably.)
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 6 µA allows the AD5243/AD5248 to be used in
portable battery-operated applications.
For applications that program the AD5243/AD5248 at the
factory, Analog Devices, Inc., offers device programming
software running on Windows® NT/2000/XP operating systems.
This software effectively replaces the need for external I2C
controllers, which in turn enhances the time to market of
systems. An AD5243/AD5248 evaluation kit and software are
available. The kit includes a cable and instruction manual.
AD5243/AD5248 Data Sheet
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics: 2.5 kVe rsion ................................. 3
Electrical Characteristics: 10 k, 50 kΩ, and 100 kΩ
Versions .......................................................................................... 4
Timing Characteristics: All Versions ......................................... 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Test Circuits ..................................................................................... 12
Theory of Operation ...................................................................... 13
Programming the Variable Resistor and Voltage ................... 13
Programming the Potentiometer Divider ............................... 14
ESD Protection ........................................................................... 14
Terminal Voltage Operating Range ......................................... 14
Power-Up Sequence ................................................................... 14
Layout and Power Supply Bypassing ....................................... 14
Constant Bias to Retain Resistance Setting ............................. 15
I2C Interface .................................................................................... 16
I2C Compatible, 2-Wire Serial Bus .......................................... 16
I2C Controller Programming .................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
4/16Rev. B to Rev. C
Changes to Applications Section and General Description
Section ................................................................................................ 1
Changed Digital Inputs and Outputs Parameter to Digital
Inputs Parameter, Table 1 ................................................................ 3
Changed Digital Inputs and Outputs Parameter to Digital
Inputs Parameter, Table 2 ................................................................ 4
Changes to Ordering Guide .......................................................... 19
4/12Rev. A to Rev. B
Changes to Rheostat Operation Section, Table 7, and
Table 8 .............................................................................................. 13
Changes to Voltage Output Operation Section .......................... 14
Deleted Evaluation Board Section and Figure 45, Renumbered
Sequentially ..................................................................................... 15
Changes to Table 13 ........................................................................ 17
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19
4/09Rev. 0 to Rev. A
Changes to DC CharacteristicsRheostat Mode Parameter and
to DC CharacteristicsPotentiometer Divider Mode Parameter,
Table 1 ................................................................................................. 3
Moved Figure 3 .................................................................................. 5
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19
1/04Revision 0: Initial Version
Table L
Data Sheet AD5243/AD5248
Rev. C | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS: 2.5 kΩ VERSION
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ 1 Max Unit
DC CHARACTERISTICSRHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect 2 ±0.1 +2 LSB
Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect 14 ±2 +14 LSB
Nominal Resistor Tolerance3 ∆RAB TA = 25°C 20 +55 %
Resistance Temperature Coefficient (∆RAB/RAB )/∆T VAB = VDD, wiper = no connect 35 ppm/°C
Wiper Resistance RWB Code = 0x00, VDD = 5 V 160 200
DC CHARACTERISTICSPOTENTIOMETER
DIVIDER MODE4
Differential Nonlinearity5 DNL 1.5 ±0.1 +1.5 LSB
Integral Nonlinearity5 INL 2 ±0.6 +2 LSB
Voltage Divider Temperature Coefficient
(∆V
W
/V
W
)/∆T
15
ppm/°C
Full-Scale Error
V
WFSE
14
−5.5
0
LSB
Zero-Scale Error VWZSE Code = 0x00 0 4.5 12 LSB
RESISTOR TERMINALS
Voltage Range6 VA, VB, VW GND VDD V
Capacitance A, B7 CA, CB f = 1 MHz, measured to GND,
code = 0x80
45 pF
Capacitance W7 CW f = 1 MHz, measured to GND,
code = 0x80
60 pF
Shutdown Supply Current8 IA_SD VDD = 5.5 V 0.01 1 µA
Common-Mode Leakage ICM VA = VB = VDD/2 1 nA
DIGITAL INPUTS
Input Logic High
V
IH
DD
2.4
V
Input Logic Low VIL VDD = 5 V 0.8 V
Input Logic High VIH VDD = 3 V 2.1 V
Input Logic Low VIL VDD = 3 V 0.6 V
Input Current IIL VIN = 0 V or 5 V ±1 µA
Input Capacitance7 CIL 5 pF
POWER SUPPLIES
Power Supply Range VDD RANGE 2.7 5.5 V
Supply Current IDD VIH = 5 V or VIL = 0 V 3.5 6 µA
Power Dissipation9 PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V 30 µW
Power Supply Sensitivity PSS VDD = 5 V ± 10%, code = midscale ±0.02 ±0.08 %/%
DYNAMIC CHARACTERISTICS10
Bandwidth, −3 dB BW Code = 0x80 4.8 MHz
Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz 0.1 %
VW Settling Time tS VA = 5 V, VB = 0 V, ±1 LSB error band 1 µs
Resistor Noise Voltage Density eN_WB RWB = 1.25 k, RS = 0 3.2 nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3 VA = VDD, VB = 0 V, wiper (VW) = no connect.
4 Specifications apply to all VRs.
5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter (DAC). VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
7 Guaranteed by design, but not subject to production test.
8 Measured at the A terminal. The A terminal is open circuited in shutdown mode.
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10 All dynamic characteristics use VDD = 5 V.
AD5243/AD5248 Data Sheet
Rev. C | Page 4 of 20
ELECTRICAL CHARACTERISTICS: 10 kΩ, 50 kΩ, AND 100 kΩ VERSIONS
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V;40°C < TA < 125°C; unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICSRHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect 1 ±0.1 +1 LSB
Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect 2.5 ±0.25 +2.5 LSB
Nominal Resistor Tolerance3 ∆RAB TA = 25°C 20 +20 %
Resistance Temperature Coefficient
(∆R
AB
/R
AB
)/∆T
V
AB
= V
DD
, wiper = no connect
35
ppm/°C
Wiper Resistance RWB Code = 0x00, VDD = 5 V 160 200
DC CHARACTERISTICSPOTENTIOMETER
DIVIDER MODE4
Differential Nonlinearity5
DNL
1
±0.1
+1
LSB
Integral Nonlinearity5 INL 1 ±0.3 +1 LSB
Voltage Divider Temperature Coefficient (∆VW/VW)/∆T Code = 0x80 15 ppm/°C
Full-Scale Error VWFSE Code = 0xFF 2.5 1 0 LSB
Zero-Scale Error VWZSE Code = 0x00 0 1 2.5 LSB
RESISTOR TERMINALS
Voltage Range6 VA, VB, VW GND VDD V
Capacitance A, B7 CA, CB f = 1 MHz, measured to GND,
code = 0x80
45 pF
Capacitance W7 CW f = 1 MHz, measured to GND,
code = 0x80
60 pF
Shutdown Supply Current8 IA_SD VDD = 5.5 V 0.01 1 µA
Common-Mode Leakage ICM VA = VB = VDD/2 1 nA
DIGITAL INPUTS
Input Logic High VIH VDD = 5 V 2.4 V
Input Logic Low VIL VDD = 5 V 0.8 V
Input Logic High VIH VDD = 3 V 2.1 V
Input Logic Low VIL VDD = 3 V 0.6 V
Input Current
I
IL
V
IN
= 0 V or 5 V
±1
µA
Input Capacitance CIL 5 pF
POWER SUPPLIES
Power Supply Range VDD RANGE 2.7 5.5 V
Supply Current IDD VIH = 5 V or VIL = 0 V 3.5 6 µA
Power Dissipation PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V 30 µW
Power Supply Sensitivity PSS VDD = 5 V ± 10%, code = midscale ±0.02 ±0.08 %/%
DYNAMIC CHARACTERISTICS
Bandwidth, −3 dB BW RAB = 10 kΩ/50 kΩ/100 kΩ, code = 0x80
600/100/40 kHz
Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz,
RAB = 10 kΩ
0.1 %
VW Settling Time tS VA = 5 V, VB = 0 V, ±1 LSB error band 2 µs
Resistor Noise Voltage Density eN_WB RWB = 5 k, RS = 0 9 nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3 VA = VDD, VB = 0 V, wiper (VW) = no connect.
4 Specifications apply to all VRs.
5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
7 Guaranteed by design, but not subject to production test.
8 Measured at the A terminal. The A terminal is open circuited in shutdown mode.
Data Sheet AD5243/AD5248
Rev. C | Page 5 of 20
TIMING CHARACTERISTICS: ALL VERSIONS
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ Max Unit
I2C INTERFACE TIMING CHARACTERISTICS1
SCL Clock Frequency fSCL 0 400 kHz
Bus-Free Time Between Stop and Start, tBUF t
1 1.3 μs
Hold Time (Repeated Start), tHD;STA t
2 After this period, the first clock pulse is
generated.
0.6 μs
Low Period of SCL Clock, tLOW t
3 1.3 μs
High Period of SCL Clock, tHIGH t
4 0.6 μs
Setup Time for Repeated Start Condition, tSU;STA t
5 0.6 μs
Data Hold Time, tHD;DAT2 t
6 0.9 μs
Data Setup Time, tSU;DAT t
7 100 ns
Fall Time of Both SDA and SCL Signals, tF t
8 300 ns
Rise Time of Both SDA and SCL Signals, tR t
9 300 ns
Setup Time for Stop Condition, tSU;STO t
10 0.6 μs
1 See the timing diagrams for the locations of measured values (that is, see Figure 3 and Figure 45 to Figure 48).
2 The maximum tHD:DAT must be met only if the device does not stretch the low period (tLOW) of the SCL signal.
04109-0-021
t
1
t
2
t
3
t
8
t
8
t
9
t
9
t
6
t
4
t
7
t
5
t
2
t
10
PS S
SCL
SDA
P
Figure 3. I2C Interface Detailed Timing Diagram
Am ESD [electrnsla‘iz disiharge] xensilive device. Charged dnwms and (Hum bozvdx (an dwschavgc wmhom daemon Akhough ms pvodud feawve: paxemed a. mammary prmewon tummy, damage may occuv on dewces summed m hlgh energy ESD Thevelave, plopev ESD pmauuans mama be xaken m mm performance degvadanun 0! loss of functlonahty
AD5243/AD5248 Data Sheet
Rev. C | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to GND 0.3 V to +7 V
VA, VB, VW to GND VDD
Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx1
Pulsed ±20 mA
Continuous ±5 mA
Digital Inputs and Output Voltage to GND 0 V to 7 V
Operating Temperature Range
40°C to +125°C
Maximum Junction Temperature (TJMAX) 150°C
Storage Temperature 65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Thermal Resistance, θJA for 10-Lead MSOP2 230°C/W
1The maximum terminal current is bound by the maximum current handling
of the switches, the maximum power dissipation of the package, and the
maximum applied voltage across any two of the A, B, and W terminals at a
given resistance.
2The package power dissipation is (TJMAX − TA)/θJA.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
DDDDD .EEEEE DDDDD .EEEEE
Data Sheet AD5243/AD5248
Rev. C | Page 7 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
10
9
8
7
1
2
3
4
B1
A1
W2
W1
B2
A2
SDAGND
6
5SCLVDD
TOP VIEW
AD5243
04109-0-027
Figure 4. AD5243 Pin Configuration
10
9
8
7
1
2
3
4
B1
AD0
W2
W1
B2
AD1
SDAGND
6
5SCL
VDD
TOP VIEW
AD5248
04109-0-028
Figure 5. AD5248 Pin Configuration
Table 5. AD5243 Pin Function Descriptions
Pin
No. Mnemonic Description
1 B1 B1 Terminal.
2 A1 A1 Terminal.
3 W2 W2 Terminal.
4 GND Digital Ground.
5 VDD Positive Power Supply.
6 SCL Serial Clock Input. Positive-edge
triggered.
7 SDA Serial Data Input/Output.
8 A2 A2 Terminal.
9 B2 B2 Terminal.
10 W1 W1 Terminal.
Table 6. AD5248 Pin Function Descriptions
Pin
No. Mnemonic Description
1 B1 B1 Terminal.
2 AD0 Programmable Address Bit 0 for Multiple
Package Decoding.
3 W2 W2 Terminal.
4 GND Digital Ground.
5
V
DD
Positive Power Supply.
6 SCL Serial Clock Input. Positive-edge
triggered.
7 SDA Serial Data Input/Output.
8 AD1 Programmable Address Bit 1 for Multiple
Package Decoding.
9
B2
B2 Terminal.
10 W1 W1 Terminal.
AD5243/AD5248 Data Sheet
Rev. C | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
–1.5
–1.0
–0.5
0
0.5
RHEOSTAT MODE INL (LSB)
1.0
1.5
2.0
12896
32 64
0 160 192 224 256
CODE (DECIMAL)
04109-0-030
V
DD
= 5.5V
T
A
= 25°C
R
AB
= 10k
V
DD
= 2.7V
Figure 6. R-INL vs. Code vs. Supply Voltages
–0.5
–0.4
–0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
RHEOSTAT MODE DNL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04109-0-031
T
A
= 25°C
R
AB
= 10k
V
DD
= 2.7V
V
DD
= 5.5V
Figure 7. R-DNL vs. Code vs. Supply Voltages
–0.5
–0.4
–0.3
–0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
POTENTIOMETER MODE INL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04109-0-032
R
AB
= 10k
V
DD
= 2.7V
T
A
= –40°C, +25°C, +85°C, +125°C
V
DD
= 5.5V
T
A
= –40°C, +25°C, +85°C, +125°C
Figure 8. INL vs. Code vs. Temperature
0.5
–0.4
0.3
0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTENTIOMETER MODE DNL (LSB)
128
96
32 64
0 160 192 224 256
CODE (DECIMAL)
04109-0-033
V
DD
= 2.7V; T
A
= 40°C, +25°C, +85°C, +125°C
R
AB
= 10k
Figure 9. DNL vs. Code vs. Temperature
–1.0
–0.8
–0.6
–0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
POTENTIOMETER MODE INL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04109-0-034
T
A
= 25°C
R
AB
= 10k
V
DD
= 2.7V
V
DD
= 5.5V
Figure 10. INL vs. Code vs. Supply Voltages
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTENTIOMETER MODE DNL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04109-0-035
TA = 25°C
RAB = 10k
VDD = 2.7V
VDD = 5.5V
Figure 11. DNL vs. Code vs. Supply Voltages
.7v / I / H W,—
Data Sheet AD5243/AD5248
Rev. C | Page 9 of 20
–2.0
–1.5
–1.0
–0.5
0
0.5
RHEOSTAT MODE INL (LSB)
1.0
1.5
2.0
1289632 640 160 192 224 256
CODE (DECIMAL)
04109-0-036
R
AB
= 10k
V
DD
= 2.7V
T
A
= –40°C, +25°C, +85°C, +125°C
V
DD
= 5.5V
T
A
= –40°C, +25°C, +85°C, +125°C
Figure 12. R-INL vs. Code vs. Temperature
–0.5
0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
RHEOSTAT MODE DNL (LSB)
128
96
32 640 160 192 224 256
CODE (DECIMAL)
04109-0-037
V
DD
= 2.7V, 5.5V; T
A
= –40°C, +25°C, +85°C, +125°C
R
AB
= 10k
Figure 13. R-DNL vs. Code vs. Temperature
–2.0
–1.5
–1.0
–0.5
0
0.5
FSE, FULL-SCALE ERROR (LSB)
1.0
1.5
2.0
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
04109-0-038
VDD = 5.5V, VA = 5.0V
RAB = 10k
VDD = 2.7V, VA = 2.7V
Figure 14. Full-Scale Error vs. Temperature
0
0.75
1.50
2.25
3.00
3.75
4.50
ZSE, ZERO-SCALE ERROR (LSB)
TEMPERATURE (°C)
40 –25 –10 5 20 35 50 65 80 95 110 125
04109-0-039
V
DD
= 5.5V, V
A
= 5.0V
R
AB
= 10k
V
DD
= 2.7V, V
A
= 2.7V
Figure 15. Zero-Scale Error vs. Temperature
I
DD
, SUPPLY CURRENT (µA)
0.1
1
10
–40 –7 26 59 92 125
TEMPERATURE (°C)
04109-0-040
V
DD
= 5V
V
DD
= 3V
Figure 16. Supply Current vs. Temperature
–20
0
20
40
60
80
100
120
RHEOSTAT MODE TEMPCO (ppm/°C)
1289632 640 160 192 224 256
CODE (DECIMAL)
04109-0-041
R
AB
= 10k
V
DD
= 2.7V
T
A
= –40°C TO +85°C, –40°C TO +125°C
V
DD
= 5.5V
T
A
= –40°C TO +85°C, –40°C TO +125°C
Figure 17. Rheostat Mode Tempco ΔRWBT vs. Code
AD5243/AD5248 Data Sheet
Rev. C | Page 10 of 20
–30
–20
–10
0
10
20
POTENTIOMETER MODE TEMPCO (ppm/°C)
30
40
50
12896
32 640 160 192 224 256
CODE (DECIMAL)
04109-0-042
R
AB
= 10k
V
DD
= 2.7V
T
A
= –40°C TO +85°C, –40°C TO +125°C
V
DD
= 5.5V
T
A
= –40°C TO +85°C, –40°C TO +125°C
Figure 18. Potentiometer Mode Tempco ΔVWBT vs. Code
60
54
48
–42
–36
30
–24
18
12
–6
0
GAIN (dB)
FREQUENCY (Hz)
10k 1M
100k 10M
04109-0-043
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 19. Gain vs. Frequency vs. Code, RAB = 2.5 k
60
–54
–48
–42
–36
–30
–24
–18
–12
6
0
GAIN (dB)
FREQUENCY (Hz)
1k 100k10k 1M
04109-0-044
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 20. Gain vs. Frequency vs. Code, RAB = 10 k
60
54
48
42
36
30
24
18
12
6
0
GAIN (dB)
FREQUENCY (Hz)
1k 100k
10k 1M
04109-0-045
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 21. Gain vs. Frequency vs. Code, RAB = 50 k
60
–54
–48
42
36
–30
24
18
–12
6
0
GAIN (dB)
FREQUENCY (Hz)
1k 100k
10k 1M
04109-0-046
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 22. Gain vs. Frequency vs. Code, RAB = 100 k
–60
–54
–48
–42
–36
–30
–24
–18
12
–6
0
GAIN (dB)
FREQUENCY (Hz)
10k1k 100k 1M 10M
04109-0-047
100k
60kHz 50k
120kHz 10k
570kHz
2.5k
2.2MHz
Figure 23. 3 dB Bandwidth at Code = 0x80
H 200mm 012 svoov mum cm 1 24m cm snnv m 2nnmvmw2nnns Ncm \ 2m chlsnnmx _ snnv MmNChZI no A, um snnmvw m anus} N on \ mmv .__._..__.J5 cm snnv m snnv 5mm; Man; 25:.
Data Sheet AD5243/AD5248
Rev. C | Page 11 of 20
I
DD
, SUPPLY CURRENT (mA)
0.01
1
0.1
10
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
DIGITAL INPUT VOLTAGE (V)
04109-0-052
T
A
= 25°C
V
DD
= 2.7V
V
DD
= 5.5V
Figure 24. Supply Current vs. Digital Input Voltage
04109-0-048
SCL
V
W
Figure 25. Digital Feedthrough
04109-0-049
V
W1
V
W2
Figure 26. Digital Crosstalk
04109-0-051
V
W1
V
W2
Figure 27. Analog Crosstalk
04109-0-053
V
W
Figure 28. Midscale Glitch, Code 0x80 to Code 0x7F
04109-0-050
SCL
V
W
Figure 29. Large-Signal Settling Time
Av”;
AD5243/AD5248 Data Sheet
Rev. C | Page 12 of 20
TEST CIRCUITS
Figure 30 through Figure 36 illustrate the test circuits that define the test conditions used in the product specification tables (see Table 1
and Table 2).
04109-0-003
V
MS
AW
B
DUT
V+
V+ = V
DD
1LSB = V+/2
N
Figure 30. Test Circuit for Potentiometer Divider Nonlinearity Error
(INL, DNL)
04109-0-004
NO CONNECT
I
W
V
MS
AW
B
DUT
Figure 31. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation: R-INL, R-DNL)
04109-0-005
V
MS2
V
MS1
V
W
AW
B
DUT
I
W
= V
DD
/R
NOMINAL
R
W
= [V
MS1
– V
MS2
]/I
W
Figure 32. Test Circuit for Wiper Resistance
04109-0-006
V
MS
%
DUT
( )
AW
B
V+ V
DD
%
V
MS
V
DD
V
DD
V
A
V
MS
V+ = V
DD
± 10%
PSRR (dB) = 20 LOG
PSS (%/%) =
Figure 33. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
04109-0-009
+15V
–15V
W
A
2.5V
BV
OUT
OFFSET
GND
DUT
AD8610
V
IN
Figure 34. Test Circuit for Gain vs. Frequency
04109-0-010
W
B
V
SS
TO V
DD
DUT
I
SW
CODE = 0x00
R
SW
=0.1V
I
SW
0.1V
Figure 35. Test Circuit for Incremental On Resistance
W
BV
CM
I
CM
A
NC
GND
NC
V
DD
DUT
NC = NO CONNECT
04109-0-011
Figure 36. Test Circuit for Common-Mode Leakage Current
Data Sheet AD5243/AD5248
Rev. C | Page 13 of 20
THEORY OF OPERATION
The AD5243/AD5248 are 256-position, digitally controlled
variable resistor (VR) devices.
An internal power-on preset places the wiper at midscale
during power-on, which simplifies the fault condition recovery
at power-up.
PROGRAMMING THE VARIABLE RESISTOR AND
VOLTAGE
Rheostat Operation
The nominal resistance of the RDAC between Terminal A and
Terminal B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ.
The nominal resistance (RAB) of the VR has 256 contact points
accessed by the wiper terminal and the B terminal contact. The
8-bit data in the RDAC latch is decoded to select one of the 256
possible settings.
A
W
B
A
W
B
A
W
B
04109-0-012
Figure 37. Rheostat Mode Configuration
Assuming that a 10 kΩ part is used, the first connection of the
wiper starts at the B terminal for Data 0x00. Because there is
a 160 Ω wiper contact resistance, such a connection yields a
minimum of 320 Ω (2 × 160 Ω) resistance between Terminal W
and Terminal B. The second connection is the first tap point,
which corresponds to 359 Ω (RWB = RAB/256 + 2 × RW = 39 Ω +
2 × 160 Ω) for Data 0x01. The third connection is the next tap
point, representing 398 Ω (2 × 39 Ω + 2 × 160 Ω) for Data 0x02,
and so on. Each LSB data value increase moves the wiper up the
resistor ladder until the last tap point is reached at 10,281 Ω
(RAB + 2 × RW).
D5
D4
D3
D7
D6
D2
D1
D0
RDAC
LATCH
AND
DECODER
R
S
R
S
R
S
R
S
A
W
B
04109-0-013
Figure 38. AD5243 Equivalent RDAC Circuit
The general equation determining the digitally programmed
output resistance between W and B is
W
AB
WB RR
D
DR 2
256
)( (1)
where:
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on resistance of
the internal switch.
In summary, if RAB is 10 kΩ and the A terminal is open circuited,
the following output resistance, RWB, is set for the indicated
RDAC latch codes.
Table 7. Codes and Corresponding RWB Resistance
D (Dec) RWB (Ω) Output State
255 10,281 Full scale (RAB − 1 LSB + 2 × RW)
128 5380 Midscale
1 359 1 LSB + 2 × RW
0 320 Zero scale (wiper contact resistance)
Note that in the zero-scale condition, a finite wiper resistance of
320 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of no
more than 20 mA. Otherwise, degradation or possible destruction
of the internal switch contact may occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A also produces a
digitally controlled complementary resistance, RWA . When these
terminals are used, the B terminal can be opened. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
W
ABWA RR
D
DR
2
256
256
)( (2)
When RAB is 10 kΩ and the B terminal is open circuited, the
output resistance, RWA , is set according to the RDAC latch
codes, as listed in Table 8.
Table 8. Codes and Corresponding RWA Resistance
D (Dec) RWA (Ω) Output State
255 359 Full scale
128 5320 Midscale
1 10,280 1 LSB + 2 × RW
0 10,320 Zero scale
Typical device-to-device matching is process-lot dependent and
may vary by up to ±30%. Because the resistance element is pro-
cessed in thin-film technology, the change in RAB with temperature
has a very low temperature coefficient of 35 ppm/°C.
2 55555
AD5243/AD5248 Data Sheet
Rev. C | Page 14 of 20
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper to B and wiper to A, proportional to the input voltage at
A to B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
A
V
I
W
B
V
O
04109-0-014
Figure 39. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper to B, starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage
applied across Terminal A and Terminal B divided by the
256 positions of the potentiometer divider. The general equation
defining the output voltage at VW with respect to ground for any
valid input voltage applied to Terminal A and Terminal B is
B
A
WV
D
V
D
DV
256
256
256
)(
+=
(3)
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Unlike in
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, RWA and RWB, not on the
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
ESD PROTECTION
All digital inputs are protected with a series of input resistors
and parallel Zener ESD structures, as shown in Figure 40 and
Figure 41. This applies to the SDA, SCL, AD0, and AD1 digital
input pins (AD5248 only).
LOGIC
340
GND
04109-0-015
Figure 40. ESD Protection of Digital Pins
A, B, W
GND
04109-0-016
Figure 41. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5243/AD5248 VDD and GND power supply defines the
boundary conditions for proper 3-terminal digital potentiometer
operation. Supply signals present on the A, B, and W terminals
that exceed VDD or GND are clamped by the internal forward-
biased diodes (see Figure 42).
GND
A
W
B
V
DD
04109-0-017
Figure 42. Maximum Terminal Voltages Set by VDD and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at the A, B, and W terminals (see Figure 42), it is important to
power VDD/GND before applying voltage to the A, B, and W
terminals; otherwise, the diode is forward-biased such that VDD
is powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and then VA, VB, and VW. The relative
order of powering VA, VB, VW, and the digital inputs is not
important, as long as they are powered after VDD/GND.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies with
quality capacitors for optimum stability. Supply leads to the device
should be bypassed with disc or chip ceramic capacitors of 0.01 µF
to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors
should also be applied at the supplies to minimize any transient
disturbance and low frequency ripple (see Figure 43). In addition,
note that the digital ground should be joined remotely to the
analog ground at one point to minimize the ground bounce.
V
DD
GND
V
DD
C3
10µFC1
0.1µF
AD5243
+
04109-0-018
Figure 43. Power Supply Bypassing
Data Sheet AD5243/AD5248
Rev. C | Page 15 of 20
CONSTANT BIAS TO RETAIN RESISTANCE SETTING
For users who desire nonvolatility but cannot justify the addi-
tional cost of an EEMEM, the AD5243/AD5248 can be considered
low cost alternatives by maintaining a constant bias to retain the
wiper setting. The AD5243/AD5248 are designed specifically for
low power applications, allowing low power consumption even
in battery-operated systems. The graph in Figure 44 demonstrates
the power consumption from a 3.4 V, 450 mAhr Li-Ion cell phone
battery connected to the AD5243/AD5248. The measurement
over time shows that the device draws approximately 1.3 µA
and consumes negligible power. Over a course of 30 days, the
battery is depleted by less than 2%, the majority of which is due
to the intrinsic leakage current of the battery itself.
DAYS
BATTERY LIFE DEPLETED (%)
0
90
92
94
96
510 15
98
100
102
104
106
108
110
20 25 30
04109-0-019
T
A
= 25°C
Figure 44. Battery Operating Life Depletion
This demonstrates that constantly biasing the potentiometer
can be a practical approach. Most portable devices do not
require the removal of batteries for the purpose of charging.
Although the resistance setting of the AD5243/AD5248 is lost
when the battery needs replacement, such events occur rather
infrequently such that this inconvenience is justified by the
lower cost and smaller size offered by the AD5243/AD5248. If
total power is lost, the user should be provided with a means to
adjust the setting accordingly.
re» byl R/\’\’ {or dam R/W NW
AD5243/AD5248 Data Sheet
Rev. C | Page 16 of 20
I2C INTERFACE
I2C COMPATIBLE, 2-WIRE SERIAL BUS
The 2-wire, I2C-compatible serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 45). The
following byte is the slave address byte, which consists of
the slave address followed by an R/W bit (this bit deter-
mines whether data is read from or written to the slave
device). The AD5243 has a fixed slave address byte,
whereas the AD5248 has two configurable address bits,
AD0 and AD1 (see Figure 10).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is called the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/W bit is high, the master reads
from the slave device. On the other hand, if the R/W bit is
low, the master writes to the slave device.
2. In the write mode, the second byte is the instruction byte.
The first bit (MSB) of the instruction byte is the RDAC
subaddress select bit. A logic low selects Channel 1 and a
logic high selects Channel 2.
The second MSB, SD, is a shutdown bit. A logic high causes
an open circuit at Terminal A while shorting the wiper to
Terminal B. This operation yields almost 0 Ω in rheostat
mode or 0 V in potentiometer mode. It is important to
note that the shutdown operation does not disturb the
contents of the register. When the AD5243 or AD5248 is
brought out of shutdown, the previous setting is applied to
the RDAC. In addition, during shutdown, new settings can
be programmed. When the part is returned from shutdown,
the corresponding VR setting is applied to the RDAC.
The remainder of the bits in the instruction byte are dont
care bits (see Figure 10).
After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Figure 45
and Figure 46).
3. In the read mode, the data byte follows immediately after the
acknowledgment of the slave address byte. Data is transmitted
over the serial bus in sequences of nine clock pulses (a slight
difference with the write mode, where there are eight data bits
followed by an acknowledge bit). Similarly, the transitions
on the SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Figure 47
and Figure 48).
Note that the channel of interest is the one that is previously
selected in write mode. If users need to read the RDAC
values of both channels, they need to program the first
channel in write mode and then change to read mode to
read the first channel value. After that, the user must return
the device to write mode with the second channel selected
and read the second channel value in read mode. It is not
necessary for users to issue the Frame 3 data byte in write
mode for subsequent readback operation. Users should refer
to Figure 47 and Figure 48 for the programming format.
4. After all data bits have been read or written, a stop condition
is established by the master. A stop condition is defined as
a low-to-high transition on the SDA line while SCL is high.
In write mode, the master pulls the SDA line high during
the 10th clock pulse to establish a stop condition (see Figure
45 and Figure 46). In read mode, the master issues a no
acknowledge for the ninth clock pulse (that is, the SDA line
remains high). The master then brings the SDA line low
before the 10th clock pulse, which goes high to establish a
stop condition (see Figure 47 and Figure 48).
A repeated write function provides the user with the flexibility
of updating the RDAC output multiple times after addressing
and instructing the part only once. For example, after the
RDAC has acknowledged its slave address and instruction
bytes in write mode, the RDAC output updates on each
successive byte. If different instructions are needed, however,
the write/read mode must restart with a new slave address,
instruction, and data byte. Similarly, a repeated read function
of the RDAC is also allowed.
Table 10. AD5248 Write Mode E‘
Data Sheet AD5243/AD5248
Rev. C | Page 17 of 20
Write Mode
Table 9. AD5243 Write Mode
S 0 1 0 1 1 1 1 W A A0 SD X X X X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave address byte Instruction byte Data byte
Table 10. AD5248 Write Mode
S 0 1 0 1 1 AD1 AD0 W A A0 SD X X X X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave address byte Instruction byte Data byte
Read Mode
Table 11. AD5243 Read Mode
S
0
1
0
1
1
1
1
R
A
D7
D6
D5
D4
D3
D2
D1
D0
A
P
Slave address byte Data byte
Table 12. AD5248 Read Mode
S 0 1 0 1 1 AD1 AD0 R A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave address byte Data byte
Table 13. SDA Bits Descriptions
Bit Description
S Start condition.
P
Stop condition.
A Acknowledge.
AD0, AD1 Package pin-programmable address bits.
X Don’t care.
W Write.
R Read.
A0 RDAC subaddress select bit.
SD Shutdown connects wiper to B terminal and open circuits the A terminal. It does not change the
contents of the wiper register.
D7, D6, D5, D4, D3, D2, D1, D0 Data bits.
AD5243/AD5248 Data Sheet
Rev. C | Page 18 of 20
I2C CONTROLLER PROGRAMMING
Write Bit Patterns
04109-0-022
SCL
START BY
MASTER
SDA 01
1
FRAME 1
SLAVE ADDRESS BYTE
01111
FRAME 2
INSTRUCTION BYTE
ACK BY
AD5243
R/W A0 SD X X X X
19
D7 D6 D5 D4 D3
ACK BY
AD5243
FRAME 3
DATA BYTE
19
X
STOP BY
MASTER
9
D2 D1 D0
ACK BY
AD5243
X
Figure 45. Writing to the RDAC RegisterAD5243
04109-0-023
SCL
START BY
MASTER
SDA 0 1
1
FRAME 1
SLAVE ADDRESS BYTE
0 1 1 AD1 AD0
FRAME 2
INSTRUCTION BYTE
ACK BY
AD5248
R/W A0 SD X X X X
19
D7 D6 D5 D4 D3
ACK BY
AD5248
FRAME 3
DATA BYTE
1
9
X
STOP BY
MASTER
9
D2 D1 D0
ACK BY
AD5248
X
Figure 46. Writing to the RDAC RegisterAD5248
Read Bit Patterns
04109-0-024
SCL
START BY
MASTER STOP BY
MASTER
SDA 01
1
FRAME 1
SLAVE ADDRESS BYTE
01 1 1 1
FRAME 2
RDAC REGISTER
ACK BY
AD5243
R/W D7 D6 D4 D3 D2 D1 D0
19
NO ACK
BY MASTER
9
D5
Figure 47. Reading Data from a Previously Selected RDAC Register in Write ModeAD5243
04109-0-025
SCL
START BY
MASTER
SDA 0 1
1
FRAME 1
SLAVE ADDRESS BYTE
0 1 1 AD1 AD0
FRAME 2
RDAC REGISTER
ACK BY
AD5248
R/W D7 D6 D4 D3 D2 D1 D0
19 9
D5
STOP BY
MASTER
NO ACK
BY MASTER
Figure 48. Reading Data from a Previously Selected RDAC Register in Write ModeAD5248
Multiple Devices on One Bus (Applies Only to AD5248)
Figure 49 shows four AD5248 devices on the same serial bus.
Each has a different slave address because the states of their
AD0 and AD1 pins are different. This allows each device on the
bus to be written to or read from independently. The master
device output bus line drivers are open-drain pull-downs in a
fully I2C-compatible interface.
SDA
SDA
AD1
AD0
MASTER
SCL
SCL
AD5248
SDA
AD1
AD0
SCL
AD5248
SDA
AD1
AD0
SCL
AD5248
SDA
5V
R
P
R
P
5V
5V
5V
AD1
AD0
SCL
AD5248
04109-0-026
Figure 49. Multiple AD5248 Devices on One I2C Bus
: 1/* twj ’fl *4 JLW 6;: L, 4 LE ORDERING GUIDE
Data Sheet AD5243/AD5248
Rev. C | Page 19 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 50. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2 RAB Temperature Package Description Package Option Branding
AD5243BRM2.5 2.5 kΩ −40°C to +125°C 10-Lead MSOP RM-10 D0L
AD5243BRM10 10 kΩ −40°C to +125°C 10-Lead MSOP RM-10 D0M
AD5243BRM100 100 kΩ −40°C to +125°C 10-Lead MSOP RM-10 D0P
AD5243BRMZ2.5 2.5 kΩ −40°C to +125°C 10-Lead MSOP RM-10 D9X
AD5243BRMZ2.5-RL7 2.5 kΩ 40°C to +125°C 10-Lead MSOP RM-10 D9X
AD5243BRMZ10
10 kΩ
−40°C to +125°C
10-Lead MSOP
RM-10
D0M
AD5243BRMZ10-RL7 10 kΩ 40°C to +125°C 10-Lead MSOP RM-10 D0M
AD5243BRMZ50 50 kΩ −40°C to +125°C 10-Lead MSOP RM-10 D0N
AD5243BRMZ50-RL7 50 kΩ 40°C to +125°C 10-Lead MSOP RM-10 D0N
AD5243BRMZ100 100 kΩ −40°C to +125°C 10-Lead MSOP RM-10 D0P
AD5243BRMZ100-RL7 100 kΩ −40°C to +125°C 10-Lead MSOP RM-10 D0P
EVAL-AD5243SDZ Evaluation Board
AD5248BRM100 100 kΩ −40°C to +125°C 10-Lead MSOP RM-10 D1J
AD5248BRMZ2.5 2.5 kΩ −40°C to +125°C 10-Lead MSOP RM-10 D1F
AD5248BRMZ2.5-RL7 2.5 kΩ 40°C to +125°C 10-Lead MSOP RM-10 D1F
AD5248BRMZ10 10 kΩ −40°C to +125°C 10-Lead MSOP RM-10 D8Z
AD5248BRMZ10-RL7 10 kΩ 40°C to +125°C 10-Lead MSOP RM-10 D8Z
AD5248BRMZ50 50 kΩ −40°C to +125°C 10-Lead MSOP RM-10 D90
AD5248BRMZ50-RL7 50 kΩ 40°C to +125°C 10-Lead MSOP RM-10 D90
AD5248BRMZ100
100 kΩ
−40°C to +125°C
10-Lead MSOP
RM-10
D91
AD5248BRMZ100-RL7 100 kΩ −40°C to +125°C 10-Lead MSOP RM-10 D91
1 Z = RoHS Compliant Part.
2 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
‘fllonlrlméAnalug nuim, Inn All light: mama. Yvademavksand ANALOG DEVICES www.analug.cum
AD5243/AD5248 Data Sheet
Rev. C | Page 20 of 20
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©20042016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04109-0-4/16(C)

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