MC(10,100)EP52 Datasheet by onsemi

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3 ON Scanninondllctor‘a www.0nseml.com @aé HHHH HHHH E I— o. "’ HHHH 13333 HHHH HHHH % I— HHHH 13333 M “For addmona‘ marking Norma ANDBDOZ/D
© Semiconductor Components Industries, LLC, 2016
August, 2016 Rev. 8
1Publication Order Number:
MC10EP52/D
MC10EP52, MC100EP52
3.3V / 5V ECL Differential
Data and Clock D Flip‐Flop
Description
The MC10EP/100EP52 is a differential data, differential clock D
flip-flop. The device is pin and functionally equivalent to the EL52
device.
Data enters the master portion of the flipflop when the clock is
LOW and is transferred to the slave, and thus the outputs, upon a
positive transition of the clock. The differential clock inputs of the
EP52 allow the device to also be used as a negative edge triggered
device.
The EP52 employs input clamping circuitry so that under open input
conditions (pulled down to VEE) the outputs of the device will remain
stable.
The 100 Series contains temperature compensation.
Features
330 ps Typical Propagation Delay
Maximum Frequency = u 4 GHz Typical
PECL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode: VCC = 0 V with VEE = 3.0 V to 5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output Will Default LOW with Inputs Open or at VEE
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
SOIC8 NB
D SUFFIX
CASE 75107
MARKING DIAGRAMS*
TSSOP8
DT SUFFIX
CASE 948R02
ALYWG
G
HP01
ALYWG
G
KP01
1
8
1
8
1
8
www.onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
1
8
HEP01
ALYW
G
1
8
KEP01
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
SOIC8 NB TSSOP8 DFN8
5T MG
G
14
3OMG
G
14
H = MC10 A = Assembly Location
K = MC100 L = Wafer Lot
5T = MC10 Y = Year
3O = MC100 W = Work Week
M= Date Code
G= Pb-Free Package
(Note: Microdot may be in either location)
ELK" CTR D‘, U For addmona‘ \ntormatlon‘ see Apphcatlon Nole ANDaooa D
MC10EP52, MC100EP52
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2
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
1
2
3
45
6
7
8
Q
VEE
VCC
D
QCLK
CLK
D
D
Flip-Flop
PIN
CLK*, CLK*
FUNCTION
ECL Clock Inputs
D*, D* ECL Data Input
Q, Q ECL Data Outputs
VCC Positive Supply
VEE Negative Supply
* Pins will default LOW when left open.
Table 1. PIN DESCRIPTION
D
L
H
CLK
Z
Z
Q
L
H
Z = LOW to HIGH Transition
Table 2. TRUTH TABLE
EP (DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect to
the most negative supply (GND) or
leave unconnected, floating open.
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor 75 kW
Internal Input Pullup Resistor N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg
SOIC8 NB
TSSOP8
DFN8
Level 1
Level 3
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 @ 0.125 in
Transistor Count 155 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC PECL Mode Power Supply VEE = 0 V 6 V
VEE NECL Mode Power Supply VCC = 0 V 6 V
VIPECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VI VCC
VI VEE
6
6
V
Iout Output Current Continuous
Surge
50
100
mA
IBB VBB Sink/Source ±0.5 mA
TAOperating Temperature Range 40 to +85 °C
Tstg Storage Temperature Range 65 to +150 °C
qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC8 NB
SOIC8 NB
190
130
°C/W
qJC Thermal Resistance (Junction-to-Case) Standard Board SOIC8 NB 41 to 44 °C/W
qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
TSSOP8
TSSOP8
185
140
°C/W
qJC Thermal Resistance (Junction-to-Case) Standard Board TSSOP841 to 44 °C/W
qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
Tsol Wave Solder (Pb-Free) < 2 to 3 sec @ 260°C 265 °C
qJC Thermal Resistance (Junction-to-Case) (Note 2) DFN8 35 to 40 °C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board 2S2P (2 signal, 2 power)
Table 5. 10EP DC CHARACTERISTICS, PECL (VCC = 3.3 V, VEE = 0 V (Note 1))
Symbol Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 20 34 44 20 35 45 20 37 47 mA
VOH Output HIGH Voltage (Note 2) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV
VOL Output LOW Voltage (Note 2) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV
VIH Input HIGH Voltage (Single-Ended) 2090 2415 2155 2480 2215 2540 mV
VIL Input LOW Voltage (Single-Ended) 1365 1690 1430 1755 1490 1815 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
2.0 3.3 2.0 3.3 2.0 3.3 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to 2.2 V.
2. All loading with 50 W to VCC 2.0 V.
3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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Table 6. 10EP DC CHARACTERISTICS, PECL (VCC = 5.0 V, VEE = 0 V (Note 1))
Symbol Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 20 34 44 20 35 45 20 37 47 mA
VOH Output HIGH Voltage (Note 2) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV
VOL Output LOW Voltage (Note 2) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV
VIH Input HIGH Voltage (Single-Ended) 3790 4115 3855 4180 3915 4240 mV
VIL Input LOW Voltage (Single-Ended) 3065 3390 3130 3455 3190 3515 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
2.0 5.0 2.0 5.0 2.0 5.0 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to 0.5 V.
2. All loading with 50 W to VCC 2.0 V.
3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 7. 10EP DC CHARACTERISTICS, NECL (VCC = 0 V, VEE = 5.5 V to 3.0 V (Note 1))
Symbol Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 20 34 44 20 35 45 20 37 47 mA
VOH Output HIGH Voltage (Note 2) 1135 1010 885 1070 945 820 1010 885 760 mV
VOL Output LOW Voltage (Note 2) 1935 1810 1685 1870 1745 1620 1810 1685 1560 mV
VIH Input HIGH Voltage (Single-Ended) 1210 885 1145 820 1085 760 mV
VIL Input LOW Voltage (Single-Ended) 1935 1610 1870 1545 1810 1485 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
VEE+2.0 0.0 VEE+2.0 0.0 VEE+2.0 0.0 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC.
2. All loading with 50 W to VCC 2.0 V.
3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP52, MC100EP52
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Table 8. 100EP DC CHARACTERISTICS, PECL (VCC = 3.3 V, VEE = 0 V (Note 1))
Symbol Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 20 34 44 20 35 45 20 37 47 mA
VOH Output HIGH Voltage (Note 2) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV
VOL Output LOW Voltage (Note 2) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV
VIH Input HIGH Voltage (Single-Ended) 2075 2420 2075 2420 2075 2420 mV
VIL Input LOW Voltage (Single-Ended) 1355 1675 1355 1675 1355 1675 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
2.0 3.3 2.0 3.3 2.0 3.3 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to 2.2 V.
2. All loading with 50 W to VCC 2.0 V.
3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 9. 100EP DC CHARACTERISTICS, PECL (VCC = 5.0 V, VEE = 0 V (Note 1))
Symbol Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 20 34 44 20 35 45 20 37 47 mA
VOH Output HIGH Voltage (Note 2) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV
VOL Output LOW Voltage (Note 2) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV
VIH Input HIGH Voltage (Single-Ended) 3775 4120 3775 4120 3775 4120 mV
VIL Input LOW Voltage (Single-Ended) 3055 3375 3055 3375 3055 3375 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
2.0 5.0 2.0 5.0 2.0 5.0 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to 0.5 V.
2. All loading with 50 W to VCC 2.0 V.
3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP52, MC100EP52
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Table 10. 100EP DC CHARACTERISTICS, NECL (VCC = 0 V, VEE = 5.5 V to 3.0 V (Note 1))
Symbol Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 20 34 44 20 35 45 20 37 47 mA
VOH Output HIGH Voltage (Note 2) 1145 1020 895 1145 1020 895 1145 1020 895 mV
VOL Output LOW Voltage (Note 2) 1945 1820 1695 1945 1820 1695 1945 1820 1695 mV
VIH Input HIGH Voltage (Single-Ended) 1225 880 1225 880 1225 880 mV
VIL Input LOW Voltage (Single-Ended) 1945 1625 1945 1625 1945 1625 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
VEE+2.0 0.0 VEE+2.0 0.0 VEE+2.0 0.0 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC.
2. All loading with 50 W to VCC 2.0 V.
3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 11. AC CHARACTERISTICS (VCC = 0 V; VEE = 3.0 V to 5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 1))
Symbol Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
VOUTpp Output Voltage Amplitude @ 3.0 GHz
(Figure 2)
630 750 610 730 520 640 GHz
tPLH,
tPHL
Propagation Delay to
Output Differential
CLK, CLK> Q, Q 250 300 350 280 330 380 310 360 410
ps
tS
tH
Setup Time
Hold Time
50
0
50
0
50
0
ps
tJITTER CLOCK Random Jitter (RMS)
(Figure 2)
0.2 1 0.2 1 0.2 1 ps
VPP Input Voltage Swing
(Differential Configuration)
150 800 1200 150 800 1200 150 800 1200 mV
tr
tf
Output Rise/Fall Times (20%80%)
Q, Q 70 110 170 80 120 180 90 130 200
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC 2.0 V.
(See Application Note ANDaozozD
MC10EP52, MC100EP52
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7
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Figure 2. Fmax Typical
FREQUENCY (MHz)
VOUTpp (mV)
3.3 V
5V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D Termination of ECL Logic Devices)
Driver
Device
Receiver
Device
QD
Q D
Zo = 50 W
Zo = 50 W
50 W50 W
VTT
VTT = VCC 2.0 V
and ree‘ spe BRDEOH/D
MC10EP52, MC100EP52
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ORDERING INFORMATION
Device Package Shipping
MC10EP52DG SOIC8 NB
(Pb-Free)
98 Units / Tube
MC10EP52DR2G SOIC8 NB
(Pb-Free)
2500 Tape & Reel
MC10EP52DTG TSSOP8
(Pb-Free)
100 Units / Tube
MC10EP52DTR2G TSSOP8
(Pb-Free)
2500 Tape & Reel
MC10EP52MNR4G DFN8
(Pb-Free)
1000 / Tape & Reel
MC100EP52DG SOIC8 NB
(Pb-Free)
98 Units / Tube
MC100EP52DR2G SOIC8 NB
(Pb-Free)
2500 Tape & Reel
MC100EP52DTG TSSOP8
(Pb-Free)
100 Units / Tube
MC100EP52DTR2G TSSOP8
(Pb-Free)
2500 Tape & Reel
MC100EP52MNR4G DFN8
(Pb-Free)
1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D ECL Clock Distribution Techniques
AN1406/D Designing with PECL (ECL at +5.0 V)
AN1503/D ECLinPSt I/O SPiCE Modeling Kit
AN1504/D Metastability and the ECLinPS Family
AN1568/D Interfacing Between LVDS and ECL
AN1672/D The ECL Translator Guide
AND8001/D Odd Number Counters Design
AND8002/D Marking and Date Codes
AND8020/D Termination of ECL Logic Devices
AND8066/D Interfacing with ECLinPS
AND8090/D AC Characteristics of ECL Devices
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PACKAGE DIMENSIONS
SOIC8 NB
D SUFFIX
CASE 75107
ISSUE AK
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 75101 THRU 75106 ARE OBSOLETE. NEW
STANDARD IS 75107.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
X
Y
G
M
Y
M
0.25 (0.010)
Z
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
1i mm A 0 «A4» |:| HWWMV DETAILE mumzvzas mm mm MW um um MAX A um um um m: C a um um um um ,\ c m Hn mm mm / :H: n nus n15 mm; was r now um um am 333329 j a , a m‘m mam DETAIL E L ‘ an ass a mess I: u‘ s“ a“ a” www.cnsemi.com 10
MC10EP52, MC100EP52
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PACKAGE DIMENSIONS
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.90 3.10 0.114 0.122
B2.90 3.10 0.114 0.122
C0.80 1.10 0.031 0.043
D0.05 0.15 0.002 0.006
F0.40 0.70 0.016 0.028
G0.65 BSC 0.026 BSC
L4.90 BSC 0.193 BSC
M0 6 0 6
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
____
SEATING
PLANE
PIN 1
14
85
DETAIL E
B
C
D
A
G
DETAIL E
F
M
L
2X L/2
U
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
T
V
W
0.25 (0.010)
8x REFK
IDENT
K0.25 0.40 0.010 0.016
TSSOP8
DT SUFFIX
CASE 948R02
ISSUE A
Ejfii \ffi I L IS‘HJHJ'J ’E‘FJIF’ 7 52 ¢ T” mmm‘ ’ 3 SIDE VIEW 5 %j a; BOTTOM VIEW
MC10EP52, MC100EP52
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PACKAGE DIMENSIONS
DFN8 2x2, 0.5 P
MN SUFFIX
CASE 506AA
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
D
E
B
C0.10
PIN ONE
2X
REFERENCE
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
A
L
(A3)
D2
E2
C
C0.10
C0.10
C0.08
NOTE 4 A1 SEATING
PLANE
e/2
e
8X
K
NOTE 3
b
8X
0.10 C
0.05 C
ABB
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.20 0.30
D2.00 BSC
D2 1.10 1.30
E2.00 BSC
E2 0.70 0.90
e0.50 BSC
K
L0.25 0.35
14
85
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
2.30
0.50
0.50
8X
DIMENSIONS: MILLIMETERS
0.30 PITCH
8X
1
PACKAGE
OUTLINE
RECOMMENDED
L1
DETAIL A
L
OPTIONAL
CONSTRUCTIONS
L
DETAIL B
DETAIL A
L1 −−− 0.10
0.30 REF
0.90
1.30
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
A1
A3
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