MC(10,100)EP51 Datasheet by onsemi

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© Semiconductor Components Industries, LLC, 2012
April, 2021 Rev. 11
1Publication Order Number:
MC10EP51/D
3.3 V/5 VECL D Flip-Flop
with Reset and Differential
Clock
MC10EP51, MC100EP51
Description
The MC10/100EP51 is a differential clock D flipflop with reset.
The device is functionally equivalent to the EL51 and LVEL51
devices.
The reset input is an asynchronous, level triggered signal. Data
enters the master portion of the flipflop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition
of the clock. The differential clock inputs of the EP51 allow the device
to be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability
under open input conditions. When left open, the CLK input will be
pulled down to VEE and the CLK input will be biased at VCC/2.
The 100 Series contains temperature compensation.
Features
350 ps Typical Propagation Delay
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 3.0 V to 5.5 V
Open Input Default State
Safety Clamp on Inputs
These Devices are PbFree and are RoHS Compliant
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A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= PbFree Package
H = MC10
K = MC100
5S = MC10
M= Date Code
SOIC8
D SUFFIX
CASE 751
MARKING DIAGRAMS*
TSSOP8
DT SUFFIX
CASE 948R
HP51
ALYWG
G
KP51
ALYWG
G
1
8
1
8
1
8
*For additional marking information, refer to
Application Note AND8002/D.
DFN8
MN SUFFIX
CASE 506AA
5S MG
G
(Note: Microdot may be in either location)
HEP51
ALYW
G
1
8
KEP51
ALYW
G
1
8
1
8
1
1
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 8 of this data sheet.
CLK‘, CW For addmonal mformauon, see Appncanon Note AN Daooa/D
MC10EP51, MC100EP51
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2
Figure 1. 8Lead Pinout (Top View) and Logic Diagram
1
2
3
45
6
7
8
Q
VEE
VCC
D
Q
CLK
CLK
RESET
D
R
Flip-Flop
Table 1. PIN DESCRIPTION
PIN
CLK*, CLK*
Reset* ECL Asynchronous Reset
FUNCTION
ECL Clock Inputs
D* ECL Data Input
Q, Q ECL Data Outputs
VCC Positive Supply
VEE Negative Supply
Table 2. TRUTH TABLE
D
L
H
X
R
L
L
H
CLK
Z
Z
X
Q
L
H
L
Z = LOW to HIGH Transition
* Pins will default LOW when left open.
EP (DFN8 only) Thermal exposed
pad must be connected to a suf-
ficient thermal conduit. Electric-
ally connect to the most negative
supply (GND) or leave uncon-
nected, floating open.
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor 75 kW
Internal Input Pullup Resistor N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) PbFree Pkg
SOIC8
TSSOP8
DFN8
Level 1
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34 UL 94 V0 @ 0.125 in
Transistor Count 165 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC PECL Mode Power Supply VEE = 0 V 6 V
VEE NECL Mode Power Supply VCC = 0 V 6 V
VIPECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VI v VCC
VI w VEE
6
6
V
V
Iout Output Current Continuous
Surge
50
100
mA
mA
TAOperating Temperature Range 40 to +85 °C
Tstg Storage Temperature Range 65 to +150 °C
qJA Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
SOIC8
SOIC8
190
130
°C/W
°C/W
qJC Thermal Resistance (JunctiontoCase) Standard Board SOIC841 to 44 °C/W
qJA Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
TSSOP8
TSSOP8
185
140
°C/W
°C/W
qJC Thermal Resistance (JunctiontoCase) Standard Board TSSOP841 to 44 °C/W
qJA Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
qJC Thermal Resistance (JunctiontoCase) (Note 2) DFN8 35 to 40 °C/W
Tsol Wave Solder Pb
PbFree
265
265
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board 2S2P (2 signal, 2 power).
Table 5. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
Symbol Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 26 34 44 26 35 45 28 37 47 mA
VOH Output HIGH Voltage (Note 4) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV
VOL Output LOW Voltage (Note 4) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV
VIH Input HIGH Voltage (SingleEnded) 2090 2415 2155 2480 2215 2540 mV
VIL Input LOW Voltage (SingleEnded) 1365 1690 1430 1755 1490 1815 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 5)
2.0 3.3 2.0 3.3 2.0 3.3 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to 2.2 V.
4. All loading with 50 W to VCC 2.0 V.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP51, MC100EP51
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Table 6. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
Symbol Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 26 34 44 26 35 45 28 37 47 mA
VOH Output HIGH Voltage (Note 7) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV
VOL Output LOW Voltage (Note 7) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV
VIH Input HIGH Voltage (SingleEnded) 3790 4115 3855 4180 3915 4240 mV
VIL Input LOW Voltage (SingleEnded) 3065 3390 3130 3455 3190 3515 mV
VIHCMR Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 8)
2.0 5.0 2.0 5.0 2.0 5.0 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to 0.5 V.
7. All loading with 50 W to VCC 2.0 V.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 7. 10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = 5.5 V to 3.0 V (Note 9)
Symbol Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 23 30 40 23 30 40 23 30 40 mA
IEE Power Supply Current 26 34 44 26 35 45 28 37 47 mA
VOH Output HIGH Voltage (Note 10) 1135 1010 885 1070 945 820 1010 885 760 mV
VOL Output LOW Voltage (Note 10) 1935 1810 1685 1870 1745 1620 1810 1685 1560 mV
VIH Input HIGH Voltage (SingleEnded) 1210 885 1145 820 1085 760 mV
VIL Input LOW Voltage (SingleEnded) 1935 1610 1870 1545 1810 1485 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 11)
VEE + 2.0 0.0 VEE + 2.0 0.0 VEE + 2.0 0.0 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
9. Input and output parameters vary 1:1 with VCC.
10.All loading with 50 W to VCC 2.0 V.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
Symbol Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 26 34 44 26 35 45 28 37 47 mA
VOH Output HIGH Voltage (Note 13) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV
VOL Output LOW Voltage (Note 13) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV
VIH Input HIGH Voltage (SingleEnded) 2075 2420 2075 2420 2075 2420 mV
VIL Input LOW Voltage (SingleEnded) 1355 1675 1355 1675 1355 1675 mV
VIHCMR Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 14)
2.0 3.3 2.0 3.3 2.0 3.3 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
12.Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to 2.2 V.
13.All loading with 50 W to VCC 2.0 V.
14.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 9. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
Symbol Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 26 34 44 26 35 45 28 37 47 mA
VOH Output HIGH Voltage (Note 16) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV
VOL Output LOW Voltage (Note 16) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV
VIH Input HIGH Voltage (SingleEnded) 3775 4120 3775 4120 3775 4120 mV
VIL Input LOW Voltage (SingleEnded) 3055 3375 3055 3375 3055 3375 mV
VIHCMR Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 17)
2.0 5.0 2.0 5.0 2.0 5.0 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
15.Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to 0.5 V.
16.All loading with 50 W to VCC 2.0 V.
17.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Propagauon De‘ay ELK, Wm Q E RESET to Q, Q 0,0
MC10EP51, MC100EP51
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Table 10. 100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = 5.5 V to 3.0 V (Note 18)
Symbol Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 26 34 44 26 35 45 28 37 47 mA
VOH Output HIGH Voltage (Note 19) 1145 1020 895 1145 1020 895 1145 1020 895 mV
VOL Output LOW Voltage (Note 19) 1945 1820 1695 1945 1820 1695 1945 1820 1695 mV
VIH Input HIGH Voltage (SingleEnded) 1225 880 1225 880 1225 880 mV
VIL Input LOW Voltage (SingleEnded) 1945 1625 1945 1625 1945 1625 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 20)
VEE + 2.0 0.0 VEE + 2.0 0.0 VEE + 2.0 0.0 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
18.Input and output parameters vary 1:1 with VCC.
19.All loading with 50 W to VCC 2.0 V.
20.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = 3.0 V to 5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
Symbol Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
fmax Maximum Frequency (Figure 2) > 3 > 3 > 3 GHz
tPLH,
tPHL
Propagation Delay to Output Differential
CLK, CLK to Q, Q 10
100
RESET to Q, Q
250
275
300
300
340
380
350
425
450
270
300
325
320
375
400
370
450
475
300
350
350
350
425
425
420
500
500
ps
tRR Reset Recovery 150 150 150 ps
tS
tH
Setup Time
Hold Time
100
100
100
100
80
40
100
100
ps
tPW Minimum Pulse Width
RESET 500 440 500 440 500 440
ps
tJITTER CycletoCycle Jitter (Figure 2) 0.2 < 1 0.2 < 1 0.2 < 1 ps
tr
tf
Output Rise/Fall Times Q, Q
(20% 80%) 70 120 170 80 130 180 100 150 200
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
21.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC 2.0 V.
200 1 00 0 1 000 (JITI’ER) 2000 3000 4000 5000 6000 FREQUENCV (MHz) Figure 2. FmaX/Jiller _‘ | | | J on Note ANDaozozD OOOOO“ m www.cnsemi.com 7
MC10EP51, MC100EP51
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7
0
100
200
300
400
500
600
700
800
900
1000
1100
0 1000 2000 3000 4000 5000 6000
Figure 2. Fmax/Jitter
FREQUENCY (MHz)
1
2
3
4
5
6
7
8
Measured
Simulated
(JITTER)
VOUTpp (mV)
JITTEROUT ps (RMS)
9
10
11
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q D
Zo = 50 W
Zo = 50 W
50 W50 W
VTT
VTT = VCC 2.0 V
Figure 4. Tape and Reel Pin 1 Quadrant Orientation
Round Sprocket Holes
User Direction
of Unreeling
Designations
Quadrant A = Upper Left
Quadrant B = Upper Right
Quadrant C = Lower Left
Quadrant D = Lower Right
Quadrant
AQuadrant
B
Quadrant Quadrant
CD
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ORDERING INFORMATION
Device Package Shipping
MC10EP51DG SOIC8
(PbFree)
98 Units / Rail
MC10EP51DR2G SOIC8
(PbFree)
2500 / Tape & Reel
MC10EP51DTG TSSOP8
(PbFree)
100 Units / Rail
MC10EP51MNTAG DFN8
(PbFree)
1000 / Tape & Reel
(Pin 1 Orientation in Quadrant A, Figure 4)
MC100EP51DG SOIC8
(PbFree)
98 Units / Rail
MC100EP51DR2G SOIC8
(PbFree)
2500 / Tape & Reel
MC100EP51DTG TSSOP8
(PbFree)
100 Units / Rail
MC100EP51DTR2G TSSOP8
(PbFree)
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D ECL Clock Distribution Techniques
AN1406/D Designing with PECL (ECL at +5.0 V)
AN1503/D ECLinPSt I/O SPiCE Modeling Kit
AN1504/D Metastability and the ECLinPS Family
AN1568/D Interfacing Between LVDS and ECL
AN1672/D The ECL Translator Guide
AND8001/D Odd Number Counters Design
AND8002/D Marking and Date Codes
AND8020/D Termination of ECL Logic Devices
AND8066/D Interfacing with ECLinPS
AND8090/D AC Characteristics of ECL Devices
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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DFN8 2x2, 0.5P
CASE 506AA01
ISSUE E
DATE 22 JAN 2010
SCALE 4:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
D
E
B
C0.10
PIN ONE
2X
REFERENCE
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
A
L
(A3)
D2
E2
C
C0.10
C0.10
C0.08
NOTE 4 A1 SEATING
PLANE
e/2
e
8X
K
NOTE 3
b
8X
0.10 C
0.05 C
ABB
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.20 0.30
D2.00 BSC
D2 1.10 1.30
E2.00 BSC
E2 0.70 0.90
e0.50 BSC
K
L0.25 0.35
1
14
85
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
2.30
0.50
0.50
8X
DIMENSIONS: MILLIMETERS
0.30 PITCH
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “ G”,
may or may not be present.
GENERIC
MARKING DIAGRAM*
8X
1
PACKAGE
OUTLINE
RECOMMENDED
XX = Specific Device Code
M = Date Code
G= PbFree Device
XXMG
G
1
L1
DETAIL A
L
OPTIONAL
CONSTRUCTIONS
L
DETAIL B
MOLD CMPDEXPOSED Cu
OPTIONAL
CONSTRUCTION
DETAIL B
DETAIL A
L1 −−− 0.10
0.30 REF
0.90
1.30
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON18658D
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
DFN8, 2.0X2.0, 0.5MM PITCH
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
0N Semiwndudw" m @ HHHH HHHH HHHH HERE 4 FUDGE] !HHH !HHH gHHH EHHH 1 1 } x ‘ 1 (...... a. ............. ... ......M .. SW. CW ........ .. ... 0. SW .. W- .. ...... ...... ...... ...... 0. SW ...... ... .... .. .... ...... ...... .. ... ...... ...... o. ......m... .. ...... .. ...... ...... ... 5...... .. .. ...... ... .. ...... a. s............ ...... ... ...... ...... ...... .....w... .. .. ... ...... ......w... ....-. ... ... ... ...... ...... ...... ...... ...5......... .. ...... ...... o. 5.--.-. .... ...... ... ...... ...... .... ..............
SOIC8 NB
CASE 75107
ISSUE AK
DATE 16 FEB 2011
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 75101 THRU 75106 ARE OBSOLETE. NEW
STANDARD IS 75107.
A
BS
D
H
C
0.10 (0.004)
SCALE 1:1
STYLES ON PAGE 2
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
X
Y
G
M
Y
M
0.25 (0.010)
Z
Y
M
0.25 (0.010) ZSXS
M
____
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= PbFree Package
GENERIC
MARKING DIAGRAM*
1
8
XXXXX
ALYWX
1
8
IC Discrete
XXXXXX
AYWW
G
1
8
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
Discrete
XXXXXX
AYWW
1
8
(PbFree)
XXXXX
ALYWX
G
1
8
IC
(PbFree)
XXXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G= PbFree Package
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42564B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
SOIC8 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
ON Semxcunduclm and ave hademavks av Semxcanduclur Campunenls lnduslnes. uc dha ON Semxcanduclar Dr K: suhsxdmnes m xna Umled sxaxas andJm mhev cmm‘nes ON Semxcunduclar vesewes me “gm to make changes wuhum mnna. mouse to any pruduns necem ON Semanduc‘m makes nu wanamy. represenlalmn m guarantee regardmg ma sumahmly at W; manual: can any pamcu‘av purpase nnv dues ON Semumnduclm assume any Mammy snsmg mm xna aapncauan m use M any pmduclnv mum and specmcsl‘y dwsc‘axms any and an Mammy mc‘udmg wxlham hmma‘mn spema‘ cansequemm m \nmdeula‘ damages ON Semxmnduclar dues nn| away any hcense under Ms pa|EM nghls Ivar xna ngms av mhers
SOIC8 NB
CASE 75107
ISSUE AK
DATE 16 FEB 2011
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. NSOURCE
2. NGATE
3. PSOURCE
4. PGATE
5. PDRAIN
6. PDRAIN
7. NDRAIN
8. NDRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42564B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
SOIC8 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
TSSOP 8 CASE 948H—02 ISSUE A .H‘. $_.I0(0004I® _w- U® ]]__E HHIHH em/ I4 g 0.15(0.onsp T u @ SENIIIG mu: «A» WE? sfi a WEI J W F DETAIL E DETAIL E I)" Semiwndudw" an GAVE mas sum Mm EXCEED u I5 mum PER sun: ommsmn a DOES Mm memos INVERLEIW FLASH 0R mmusmn Immm FLASH 0R anomusm mum EXCEED n 25 In mm PER 5an vsmmnmuuagns ARE SHOWN ron REFERENCE ow ommsmn A AND a ARE to BE ngsmmm AI mm PLANE ewe mummns IIICIIES mu MIN um um MAX A 29H m um m: a 29H m um m: c m I m mm an»: n nus ms unnz anus r non um um am a n 65:86 I] nzs‘ esc L mass memo II If I 6° u° I a” ON Sennaenaaew and J neaemenne a. Seneaneaemn Canaanene .naueunee. Lu: mm ON Semeanaaexan an us eaaeenanee n ma Unnea sxexee enexe. amen aaannee‘ ON Sennaeneaem neeeeew me nam [a make enanaee We“. We. naee. [a any mane neen 0N Semneanaaa‘en nanee na wenenw. neeneeenxenan en guarantee regenana .ne sumahmw a. ne emaaae «an anY psmcuIsv maee aaee ON Semeanaaew eeeme any Mammy anena my me aeeneanan e. a. any mad-mm anew. and eeeeneany enee‘enne anY and an new nemana Ween hmma‘mn eeeene‘ eaneeaaenne‘ e. neaena‘ aennagee ON Sennmneaexan aeee ne. amen anY naenee under ms pa.en. nane me
CASE 948R02
ISSUE A DATE 04/07/2000
TSSOP 8
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.90 3.10 0.114 0.122
B2.90 3.10 0.114 0.122
C0.80 1.10 0.031 0.043
D0.05 0.15 0.002 0.006
F0.40 0.70 0.016 0.028
G0.65 BSC 0.026 BSC
L4.90 BSC 0.193 BSC
M0 6 0 6
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
___ _
SEATING
PLANE
PIN 1
14
85
DETAIL E
B
C
D
A
G
DETAIL E
F
M
L
2X L/2
U
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
T
V
W
0.25 (0.010)
8x REFK
SCALE 2:1
IDENT
K0.25 0.40 0.010 0.016
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON00236D
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
TSSOP 8
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
a a e lrademavks av Semxcunduclm Cnmvnnems In "sine \ghlsmanumhernlpalems \rademavks Dav www menu cumrsuerguwaxem Mavkmg gm 9 www nnserm cum
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/PatentMarking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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