Spartan-3A FPGA Datasheet

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DS529 December 18, 2018 www.xilinx.com 1
Product Specification
© Copyright 2006–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.
Module 1:
Introduction and Ordering Information
DS529 (v2.1) December 18, 2018
Introduction
•Features
Architectural and Configuration Overview
General I/O Capabilities
Production Status
Supported Packages and Package Marking
Ordering Information
Module 2:
Spartan-3A FPGA Family: Functional
Description
DS529 (v2.1) December 18, 2018
The functionality of the Spartan®-3A FPGA family is
described in the following documents.
UG331: Spartan-3 Generation FPGA User Guide
Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
Configurable Logic Blocks (CLBs)
- Distributed RAM
- SRL16 Shift Registers
- Carry and Arithmetic Logic
I/O Resources
Embedded Multiplier Blocks
Programmable Interconnect
ISE® Design Tools and IP Cores
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Powering FPGAs
Power Management
UG332: Spartan-3 Generation Configuration User Guide
Configuration Overview
Configuration Pins and Behavior
Bitstream Sizes
Detailed Descriptions by Mode
- Master Serial Mode using Platform Flash PROM
- Master SPI Mode using Commodity Serial Flash
- Master BPI Mode using Commodity Parallel Flash
- Slave Parallel (SelectMAP) using a Processor
- Slave Serial using a Processor
-JTAG Mode
ISE iMPACT Programming Examples
MultiBoot Reconfiguration
Design Authentication using Device DNA
UG334: Spartan-3A/3AN FPGA Starter Kit User Guide
Module 3:
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018
DC Electrical Characteristics
Absolute Maximum Ratings
Supply Voltage Specifications
Recommended Operating Conditions
Switching Characteristics
I/O Timing
Configurable Logic Block (CLB) Timing
Multiplier Timing
Block RAM Timing
Digital Clock Manager (DCM) Timing
Suspend Mode Timing
Device DNA Timing
Configuration and JTAG Timing
Module 4:
Pinout Descriptions
DS529 (v2.1) December 18, 2018
Pin Descriptions
Package Overview
Pinout Tables
Footprint Diagrams
For more information on the Spartan-3A FPGA family, go to
www.xilinx.com/spartan3a
0
Spartan-3A FPGA Family:
Data Sheet
DS529 December 18, 2018 00Product Specification
Spartan-3A FPGA Status
XC3S50A Production
XC3S200A Production
XC3S400A Production
XC3S700A Production
XC3S1400A Production
Spartan-3A FPGA Family: Data Sheet
2 www.xilinx.com DS529 December 18, 2018
Product Specification
DS529 (v2.1) December 18, 2018 www.xilinx.com 3
© Copyright 2006–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.
Introduction
The Spartan®-3A family of Field-Programmable Gate
Arrays (FPGAs) solves the design challenges in most
high-volume, cost-sensitive, I/O-intensive electronic
applications.
The five-member family offers densities ranging
from 50,000 to 1.4 million system gates, as shown in Table 1.
The Spartan-3A FPGAs are part of the Extended
Spartan-3A family, which also include the non-volatile
Spartan-3AN and the higher density Spartan-3A DSP
FPGAs. The Spartan-3A family builds on the success of the
earlier Spartan-3E and Spartan-3 FPGA families. New
features improve system performance and reduce the cost
of configuration.
These Spartan-3A family enhancements,
combined with proven 90 nm process technology, deliver
more functionality and bandwidth per dollar than ever before,
setting the new standard in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3A FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home networking,
display/projection, and digital television equipment.
The Spartan-3A family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial cost,
lengthy development cycles, and the inherent inflexibility of
conventional ASICs, and permit field design upgrades.
Features
Very low cost, high-performance logic solution for
high-volume, cost-conscious applications
Dual-range VCCAUX supply simplifies 3.3V-only design
Suspend, Hibernate modes reduce system power
Multi-voltage, multi-standard SelectIO™ interface pins
Up to 502 I/O pins or 227 differential signal pairs
LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
Selectable output drive, up to 24 mA per pin
QUIETIO standard reduces I/O switching noise
Full 3.3V ± 10% compatibility and hot swap compliance
640+ Mb/s data transfer rate per differential I/O
LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O
with integrated differential termination resistors
Enhanced Double Data Rate (DDR) support
DDR/DDR2 SDRAM support up to 400 Mb/s
Fully compliant 32-/64-bit, 33/66 MHz PCI® technology
support
Abundant, flexible logic resources
Densities up to 25,344 logic cells, including optional shift
register or distributed RAM support
Efficient wide multiplexers, wide logic
Fast look-ahead carry logic
Enhanced 18 x 18 multipliers with optional pipeline
IEEE 1149.1/1532 JTAG programming/debug port
Hierarchical SelectRAM™ memory architecture
Up to 576 Kbits of fast block RAM with byte write enables
for processor applications
Up to 176 Kbits of efficient distributed RAM
Up to eight Digital Clock Managers (DCMs)
Clock skew elimination (delay locked loop)
Frequency synthesis, multiplication, division
High-resolution phase shifting
Wide frequency range (5 MHz to over 320 MHz)
Eight low-skew global clock networks, eight additional
clocks per half device, plus abundant low-skew routing
Configuration interface to industry-standard PROMs
Low-cost, space-saving SPI serial Flash PROM
x8 or x8/x16 BPI parallel NOR Flash PROM
Low-cost Xilinx® Platform Flash with JTAG
Unique Device DNA identifier for design authentication
Load multiple bitstreams under FPGA control
Post-configuration CRC checking
Complete Xilinx ISE® and WebPACK™ development
system software support plus Spartan-3A Starter Kit
MicroBlaze™ and PicoBlaze embedded processors
Low-cost QFP and BGA packaging, Pb-free options
Common footprints support easy density migration
Compatible with select Spartan-3AN nonvolatile FPGAs
Compatible with higher density Spartan-3A DSP FPGAs
XA Automotive version available
8Spartan-3A FPGA Family:
Introduction and Ordering Information
DS529 (v2.1) December 18, 2018 Product Specification
Table 1: Summary of Spartan-3A FPGA Attributes
Device
System
Gates
Equivalent
Logic Cells
CLB Array
(One CLB = Four Slices) Distributed
RAM bits(1)
Block
RAM
bits(1)Dedicated
Multipliers DCMs
Maximum
User I/O
Maximum
Differential
I/O PairsRows Columns CLBs Slices
XC3S50A 50K 1,584 16 12 176 704 11K 54K 3 2 144 64
XC3S200A 200K 4,032 32 16 448 1,792 28K 288K 16 4 248 112
XC3S400A 400K 8,064 40 24 896 3,584 56K 360K 20 4 311 142
XC3S700A 700K 13,248 48 32 1,472 5,888 92K 360K 20 8 372 165
XC3S1400A 1400K 25,344 72 40 2,816 11,264 176K 576K 32 8 502 227
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
Introduction and Ordering Information
4 www.xilinx.com DS529 (v2.1) December 18, 2018
Architectural Overview
The Spartan-3A family architecture consists of five
fundamental programmable functional elements:
Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. IOBs support bidirectional data flow plus 3-state
operation. Supports a variety of signal standards,
including several high-performance differential
standards. Double Data-Rate (DDR) registers are
included.
Block RAM provides data storage in the form of 18-Kbit
dual-port blocks.
Multiplier Blocks accept two 18-bit binary numbers as
inputs and calculate the product.
Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
These elements are organized as shown in Figure 1. A dual
ring of staggered IOBs surrounds a regular array of CLBs.
Each device has two columns of block RAM except for the
XC3S50A, which has one column. Each RAM column
consists of several 18-Kbit RAM blocks. Each block RAM is
associated with a dedicated multiplier. The DCMs are
positioned in the center with two at the top and two at the
bottom of the device. The XC3S50A has DCMs only at the
top, while the XC3S700A and XC3S1400A add two DCMs in
the middle of the two columns of block RAM and multipliers.
The Spartan-3A family features a rich network of routing that
interconnect all five functional elements, transmitting signals
among them. Each functional element has an associated
switch matrix that permits multiple connections to the
routing.
Figure 1: Spartan-3A FPGA Architecture
CLB
Block RAM
Multiplier
DCM
IOBs
IOBs
DS312-1_01_032606
IOBs
IOBs
DCM
Block RAM / Multiplier
DCM
CLBs
IOBs
OB
s
D
C
M
Notes:
1. The XC3S700A and XC3S1400A have two additional DCMs on both the left and right sides as indicated by the
dashed lines. The XC3S50A has only two DCMs at the top and only one Block RAM/Multiplier column.
Introduction and Ordering Information
DS529 (v2.1) December 18, 2018 www.xilinx.com 5
Configuration
Spartan-3A FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored externally in a PROM or some
other non-volatile medium, either on or off the board. After
applying power, the configuration data is written to the
FPGA using any of seven different modes:
Master Serial from a Xilinx Platform Flash PROM
Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
Byte Peripheral Interface (BPI) Up from an
industry-standard x8 or x8/x16 parallel NOR Flash
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
Boundary Scan (JTAG), typically downloaded from a
processor or system tester
Furthermore, Spartan-3A FPGAs support MultiBoot
configuration, allowing two or more FPGA configuration
bitstreams to be stored in a single SPI serial Flash or a BPI
parallel NOR Flash. The FPGA application controls which
configuration to load next and when to load it.
Additionally, each Spartan-3A FPGA contains a unique,
factory-programmed Device DNA identifier useful for
tracking purposes, anti-cloning designs, or IP protection.
I/O Capabilities
The Spartan-3A FPGA SelectIO interface supports many
popular single-ended and differential standards. Table 2
shows the number of user I/Os as well as the number of
differential I/O pairs available for each device/package
combination. Some of the user I/Os are unidirectional
input-only pins as indicated in Table 2.
Spartan-3A FPGAs support the following single-ended
standards:
3.3V low-voltage TTL (LVTTL)
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
3.3V PCI at 33 MHz or 66 MHz
HSTL I, II, and III at 1.5V and 1.8V, commonly used in
memory applications
SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used
for memory applications
Spartan-3A FPGAs support the following differential
standards:
LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or
3.3V
Bus LVDS I/O at 2.5V
TMDS I/O at 3.3V
Differential HSTL and SSTL I/O
LVPECL inputs at 2.5V or 3.3V
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
Package VQ100
VQG100
TQ144
TQG144
FT256
FTG256
FG320
FGG320
FG400
FGG400
FG484
FGG484
FG676
FGG676
Body Size
(mm) 14 x 14(2) 20 x 20(2) 17 x 17 19 x 19 21 x 21 23 x 23 27 x 27
Device User Diff User Diff User Diff User Diff User Diff User Diff User Diff
XC3S50A 68
(13)
60
(24)
108
(7)
50
(24)
144
(32)
64
(32) - - - - - - - -
XC3S200A 68
(13)
60
(24) - - 195
(35)
90
(50)
248
(56)
112
(64) - - - - - -
XC3S400A - - - - 195
(35)
90
(50)
251
(59)
112
(64)
311
(63)
142
(78) - - - -
XC3S700A - - - - 161
(13)
74
(36) - - 311
(63)
142
(78)
372
(84)
165
(93) - -
XC3S1400A - - - - 161
(13)
74
(36) - - - - 375
(87)
165
(93)
502
(94)
227
(131)
Notes:
1. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins
within I/O banks that are restricted to differential inputs.
2. The footprints for the VQ/TQ packages are larger than the package body. See the Package Drawings for details.
Introduction and Ordering Information
6 www.xilinx.com DS529 (v2.1) December 18, 2018
Production Status
Table 3 indicates the production status of each Spartan-3A
FPGA by temperature range and speed grade. The table
also lists the earliest speed file version required for creating
a production configuration bitstream. Later versions are also
supported.
Package Marking
Figure 2 provides a top marking example for Spartan-3A
FPGAs in the quad-flat packages. Figure 3 shows the top
marking for Spartan-3A FPGAs in BGA packages. The
markings for the BGA packages are nearly identical to those
for the quad-flat packages, except that the marking is
rotated with respect to the ball A1 indicator.
The “5C” and “4I” Speed Grade/Temperature Range part
combinations may be dual marked as “5C/4I”. Devices with
a single mark are only guaranteed for the marked speed
grade and temperature range.
Table 3: Spartan-3A FPGA Production Status (Production Speed File)
Temperature Range Commercial (C) Industrial
Speed Grade Standard (–4) High-Performance (–5) Standard (–4)
Part Number
XC3S50A Production
(v1.35)
Production
(v1.35)
Production
(v1.35)
XC3S200A Production
(v1.35)
Production
(v1.35)
Production
(v1.35)
XC3S400A Production
(v1.36)
Production
(v1.36)
Production
(v1.36)
XC3S700A Production
(v1.34)
Production
(v1.35)
Production
(v1.34)
XC3S1400A Production
(v1.34)
Production
(v1.35)
Production
(v1.34)
Figure 2: Spartan-3A QFP Package Marking Example
Figure 3: Spartan-3A BGA Package Marking Example
Date Code
Mask Revision Code
Process Technology
XC3S50ATM
TQ144AGQ0625
D1234567A
4C
SPARTAN
Device Type
Package
Speed Grade
Temperature Range
Fabrication Code
Pin P1
R
R
DS529-1_03_080406
Lot Code
Lot Code
Date Code
XC3S50ATM
4C
SPARTAN
Device Type
BGA Ball A1
Package
Speed Grade
Temperature Range
R
R
DS529-1_02_021206
FT256 AGQ0625
D1234567A
Mask Revision Code
Process Code
Fabrication Code
Introduction and Ordering Information
DS529 (v2.1) December 18, 2018 www.xilinx.com 7
Ordering Information
Spartan-3A FPGAs are available in both standard and Pb-free packaging options for all device/package combinations. The
Pb-free packages include a ‘G’ character in the ordering code.
Revision History
The following table shows the revision history for this document.
Device Speed Grade Package Type / Number of Pins(1) Temperature Range ( TJ
)
XC3S50A –4 Standard Performance VQ100/
VQG100
100-pin Very Thin Quad Flat Pack (VQFP) C Commercial (0°C to 85°C)
XC3S200A –5 High Performance
(Commercial only)
TQ144/
TQG144
144-pin Thin Quad Flat Pack (TQFP) I Industrial (–40°C to 100°C)
XC3S400A FT256/
FTG256
256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)
XC3S700A FG320/
FGG320
320-ball Fine-Pitch Ball Grid Array (FBGA)
XC3S1400A FG400/
FGG400
400-ball Fine-Pitch Ball Grid Array (FBGA)
FG484/
FGG484
484-ball Fine-Pitch Ball Grid Array (FBGA)
FG676
FGG676
676-ball Fine-Pitch Ball Grid Array (FBGA)
Notes:
1. See Table 2 for specific device/package combinations.
2. See DS681 for the XA Automotive Spartan-3A FPGAs.
Date Version Revision
12/05/06 1.0 Initial release.
02/02/07 1.1 Promoted to Preliminary status. Updated maximum differential I/O count for XC3S50A in Table 1.
Updated differential input-only pin counts in Table 2.
03/16/07 1.2 Minor formatting updates.
04/23/07 1.3 Added "Production Status" section.
05/08/07 1.4 Updated XC3S400A to Production.
07/10/07 1.4.1 Minor updates.
04/15/08 1.6 Added VQ100 for XC3S50A and XC3S200A and extended FT256 to XC3S700A and XC3S1400A
Added reference to SCD 4103 for 750 Mbps performance.
05/28/08 1.7 Added reference to XA Automotive version.
03/06/09 1.8 Simplified Ordering Information. Added references to Extended Spartan-3A Family.
Removed reference to SCD 4103.
08/19/10 2.0 Updated Table 2 to clarify TQ/VQ size.
12/18/2018 2.1 Updated for Lead-Frame Plating Composition Change For Legacy Eutectic Products (XCN18024).
XC3S50A -4 FT 256 C
Device Type
Speed Grade
Temperature Range
Package Type/Number of Pins
Example:
DS529-1_05_011309
Introduction and Ordering Information
8 www.xilinx.com DS529 (v2.1) December 18, 2018
DS529 (v2.1) December 18, 2018 www.xilinx.com 9
© Copyright 2006–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.
Spartan-3A FPGA Design Documentation
The functionality of the Spartan®-3A FPGA Family is
described in the following documents. The topics covered in
each guide is listed below.
DS706: Extended Spartan-3A Family Overview
www.xilinx.com/support/documentation/
data_sheets/ds706.pdf
UG331: Spartan-3 Generation FPGA User Guide
www.xilinx.com/support/documentation/
user_guides/ug331.pdf
Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
Configurable Logic Blocks (CLBs)
-Distributed RAM
-SRL16 Shift Registers
-Carry and Arithmetic Logic
I/O Resources
Embedded Multiplier Blocks
Programmable Interconnect
ISE® Software Design Tools
•IP Cores
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Powering FPGAs
Power Management
UG332: Spartan-3 Generation Configuration User
Guide
www.xilinx.com/support/documentation/
user_guides/ug332.pdf
Configuration Overview
-Configuration Pins and Behavior
-Bitstream Sizes
Detailed Descriptions by Mode
-Master Serial Mode using Xilinx® Platform
Flash PROM
-Master SPI Mode using Commodity SPI Serial
Flash PROM
-Master BPI Mode using Commodity Parallel
NOR Flash PROM
-Slave Parallel (SelectMAP) using a Processor
-Slave Serial using a Processor
-JTAG Mode
ISE iMPACT Programming Examples
MultiBoot Reconfiguration
Design Authentication using Device DNA
For application examples, see the Spartan-3A FPGA
application notes.
Spartan-3A FPGA Application Notes
www.xilinx.com/support/documentation/
spartan-3a_application_notes.htm
For specific hardware examples, please see the Spartan-3A
FPGA Starter Kit board web page, which has links to
various design examples and the user guide.
Spartan-3A/3AN FPGA Starter Kit Board Page
www.xilinx.com/s3astarter
UG334: Spartan-3A/3AN FPGA Starter Kit User
Guide
www.xilinx.com/support/documentation/
boards_and_kits/ug334.pdf
For information on the XA Automotive version of the
Spartan-3A family, see the following data sheet.
XA Spartan-3A Automotive FPGA Family Data Sheet
www.xilinx.com/support/documentation/data_sheets/
ds681.pdf
Create a Xilinx user account and sign up to receive
automatic e-mail notification whenever this data sheet or
the associated user guides are updated.
Sign Up for Alerts
www.xilinx.com/support/answers/18683.htm
10 Spartan-3A FPGA Family:
Functional Description
DS529 (v2.1) December 18, 2018 0Product Specification
Spartan-3A FPGA Family: Functional Description
10 www.xilinx.com DS529 (v2.1) December 18, 2018
Related Product Families
The Spartan-3AN nonvolatile FPGA family is architecturally
identical to the Spartan-3A FPGA family, except that it has
in-system flash memory and is offered in select
pin-compatible package options.
DS557: Spartan-3AN Family Data Sheet
www.xilinx.com/support/documentation/
data_sheets/ds557.pdf
The compatible Spartan-3A DSP FPGA family replaces the
18-bit multiplier with the DSP48A block, while also
increasing the block RAM capability and quantity. The two
members of the Spartan-3A DSP FPGA family extend the
Spartan-3A density range up to 37,440 and 53,712 logic
cells.
DS610: Spartan-3A DSP FPGA Family Data Sheet
www.xilinx.com/support/documentation/
data_sheets/ds610.pdf
UG431: XtremeDSP DSP48A for Spartan-3A DSP
FPGAs
www.xilinx.com/support/documentation/
user_guides/ug431.pdf
Revision History
The following table shows the revision history for this document.
Date Version Revision
12/05/06 1.0 Initial release.
02/02/07 1.1 Promoted to Preliminary status.
03/16/07 1.2 Added cross-reference to nonvolatile Spartan-3AN FPGA family.
04/23/07 1.3 Added cross-reference to compatible Spartan-3A DSP family.
07/10/07 1.4 Updated Starter Kit reference to new UG334.
04/15/08 1.6 Updated trademarks.
05/28/08 1.7 Added reference to XA Automotive version.
03/06/09 1.8 Added link to DS706 on Extended Spartan-3A family.
08/19/10 2.0 Updated link to sign up for Alerts.
12/18/18 Updated for Lead-Frame Plating Composition Change For Legacy Eutectic Products (XCN18024).
DS529 (v2.1) December 18, 2018 www.xilinx.com 11
© Copyright 2006–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.
DC Electrical Characteristics
In this section, specifications may be designated as
Advance, Preliminary, or Production. These terms are
defined as follows:
Advance: Initial estimates are based on simulation, early
characterization, and/or extrapolation from the
characteristics of other families. Values are subject to
change. Use as estimates, not for production.
Preliminary: Based on characterization. Further changes
are not expected.
Production: These specifications are approved once the
silicon has been characterized over numerous production
lots. Parameter values are considered stable with no future
changes expected.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan®-3A devices. AC and DC characteristics
are specified using the same numbers for both
commercial and industrial grades.
Absolute Maximum Ratings
Stresses beyond those listed under Table 4: Absolute
Maximum Ratings may cause permanent damage to the
device. These are stress ratings only; functional operation
of the device at these or any other conditions beyond those
listed under the Recommended Operating Conditions is not
implied. Exposure to absolute maximum conditions for
extended periods of time adversely affects device reliability.
64 Spartan-3A FPGA Family:
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 0Product Specification
Table 4: Absolute Maximum Ratings
Symbol Description Conditions Min Max Units
VCCINT Internal supply voltage –0.5 1.32 V
VCCAUX Auxiliary supply voltage –0.5 3.75 V
VCCO Output driver supply voltage –0.5 3.75 V
VREF Input reference voltage –0.5 VCCO
+ 0.5 V
VIN
Voltage applied to all User I/O pins and
dual-purpose pins
Driver in a high-impedance state –0.95 4.6 V
Voltage applied to all Dedicated pins –0.5 4.6 V
IIK Input clamp current per I/O pin –0.5V < VIN < (VCCO + 0.5V) (1) –±100mA
VESD Electrostatic Discharge Voltage
Human body model ±2000 V
Charged device model –±500V
Machine model –±200V
TJJunction temperature –125°C
TSTG Storage temperature –65 150 °C
Notes:
1. Upper clamp applies only when using PCI IOSTANDARDs.
2. For soldering guidelines, see UG112: Device Packaging and Thermal Characteristics and XAPP427: Implementation and Solder Reflow
Guidelines for Pb-Free Packages.
DC and Switching Characteristics
12 www.xilinx.com DS529 (v2.1) December 18, 2018
Power Supply Specifications
Table 5: Supply Voltage Thresholds for Power-On Reset
Symbol Description Min Max Units
VCCINTT Threshold for the VCCINT supply 0.4 1.0 V
VCCAUXT Threshold for the VCCAUX supply 1.0 2.0 V
VCCO2T Threshold for the VCCO Bank 2 supply 1.0 2.0 V
Notes:
1. VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (Platform Flash,
SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration
source. Apply VCCINT last for lowest overall power consumption (see UG331 chapter “Powering Spartan-3 Generation FPGAs” for more
information).
2. To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 6: Supply Voltage Ramp Rate
Symbol Description Min Max Units
VCCINTR Ramp rate from GND to valid VCCINT supply level 0.2 100 ms
VCCAUXR Ramp rate from GND to valid VCCAUX supply level 0.2 100 ms
VCCO2R Ramp rate from GND to valid VCCO Bank 2 supply level 0.2 100 ms
Notes:
1. VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (Platform Flash,
SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration
source. Apply VCCINT last for lowest overall power consumption (see UG331 chapter "Powering Spartan-3 Generation FPGAs" for more
information).
2. To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 7: Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM
Data
Symbol Description Min Units
VDRINT VCCINT level required to retain CMOS Configuration Latch (CCL) and RAM data 1.0 V
VDRAUX VCCAUX level required to retain CMOS Configuration Latch (CCL) and RAM data 2.0 V
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 13
General Recommended Operating Conditions
Table 8: General Recommended Operating Conditions
Symbol Description Min Nominal Max Units
TJ Junction temperature Commercial 0 –85°C
Industrial –40 100 °C
VCCINT Internal supply voltage 1.14 1.20 1.26 V
VCCO
(1) Output driver supply voltage 1.10 –3.60V
VCCAUX Auxiliary supply voltage(2) VCCAUX = 2.5 2.25 2.50 2.75 V
VCCAUX = 3.3 3.00 3.30 3.60 V
VIN Input voltage(3)
PCI IOSTANDARD –0.5 –V
CCO+0.5 V
All other
IOSTANDARDs
IP or IO_# –0.5 –4.10V
IO_Lxxy_# (4) –0.5 –4.10V
TIN Input signal transition time(5) 500 ns
Notes:
1. This VCCO range spans the lowest and highest operating voltages for all supported I/O standards. Table 11 lists the recommended VCCO
range specific to each of the single-ended I/O standards, and Table 13 lists that specific to the differential standards.
2. Define VCCAUX selection using CONFIG VCCAUX constraint.
3. See XAPP459, “Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins.”
4. For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.5V is supported but can cause increased leakage
between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide .
5. Measured between 10% and 90% VCCO. Follow Signal Integrity recommendations.
DC and Switching Characteristics
14 www.xilinx.com DS529 (v2.1) December 18, 2018
General DC Characteristics for I/O Pins
Table 9: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins (1)
Symbol Description Test Conditions Min Typ Max Units
IL(2) Leakage current at User I/O,
input-only, dual-purpose, and
dedicated pins, FPGA powered
Driver is in a high-impedance state,
VIN = 0V or VCCO max, sample-tested
–10 +10 µA
IHS Leakage current on pins during
hot socketing, FPGA unpowered
All pins except INIT_B, PROG_B, DONE, and JTAG
pins when PUDC_B = 1.
–10 +10 µA
INIT_B, PROG_B, DONE, and JTAG pins or other
pins when PUDC_B = 0. Add IHS + IRPU µA
IRPU(3) Current through pull-up resistor
at User I/O, dual-purpose,
input-only, and dedicated pins.
Dedicated pins are powered by
VCCAUX.
VIN = GND VCCO or VCCAUX =
3.0V to 3.6V
–151 –315 –710 µA
VCCO or VCCAUX =
2.3V to 2.7V
–82 –182 –437 µA
VCCO = 1.7V to 1.9V –36 –88 –226 µA
VCCO = 1.4V to 1.6V –22 –56 –148 µA
VCCO = 1.14V to 1.26V 11 –31 –83 µA
RPU(3) Equivalent pull-up resistor value
at User I/O, dual-purpose,
input-only, and dedicated pins
(based on IRPU per Note 3)
VIN = GND VCCO = 3.0V to 3.6V 5.1 11.4 23.9 kΩ
VCCO = 2.3V to 2.7V 6.2 14.8 33.1 kΩ
VCCO = 1.7V to 1.9V 8.4 21.6 52.6 kΩ
VCCO = 1.4V to 1.6V 10.8 28.4 74.0 kΩ
VCCO = 1.14V to 1.26V 15.3 41.1 119.4 kΩ
IRPD(3) Current through pull-down
resistor at User I/O,
dual-purpose, input-only, and
dedicated pins. Dedicated pins
are powered by VCCAUX.
VIN = VCCO VCCAUX = 3.0V to 3.6V 167 346 659 µA
VCCAUX = 2.25V to 2.75V
100 225 457 µA
RPD(3) Equivalent pull-down resistor
value at User I/O, dual-purpose,
input-only, and dedicated pins
(based on IRPD per Note 3)
VCCAUX = 3.0V to 3.6V VIN = 3.0V to 3.6V 5.5 10.4 20.8 kΩ
VIN = 2.3V to 2.7V 4.1 7.8 15.7 kΩ
VIN = 1.7V to 1.9V 3.0 5.7 11.1 kΩ
VIN = 1.4V to 1.6V 2.7 5.1 9.6 kΩ
VIN = 1.14V to 1.26V 2.4 4.5 8.1 kΩ
VCCAUX = 2.25V to 2.75V VIN = 3.0V to 3.6V 7.9 16.0 35.0 kΩ
VIN = 2.3V to 2.7V 5.9 12.0 26.3 kΩ
VIN = 1.7V to 1.9V 4.2 8.5 18.6 kΩ
VIN = 1.4V to 1.6V 3.6 7.2 15.7 kΩ
VIN = 1.14V to 1.26V 3.0 6.0 12.5 kΩ
IREF VREF current per pin All VCCO levels –10 +10 µA
CIN Input capacitance –10pF
RDT Resistance of optional differential
termination circuit within a
differential I/O pair. Not available
on Input-only pairs.
VCCO = 3.3V ± 10% LVDS_33,
MINI_LVDS_33,
RSDS_33
90 100 115 Ω
VCCO = 2.5V ± 10% LVDS_25,
MINI_LVDS_25,
RSDS_25
90 110 Ω
Notes:
1. The numbers in this table are based on the conditions set forth in Table 8.
2. For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.5V is supported but can cause increased leakage
between the two pins. See "Parasitic Leakage" in UG331, Spartan-3 Generation FPGA User Guide .
3. This parameter is based on characterization. The pull-up resistance RPU = VCCO / IRPU. The pull-down resistance RPD = VIN / IRPD.
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 15
Quiescent Current Requirements
Table 10: Quiescent Supply Current Characteristics
Symbol Description Device Typical(2) Commercial
Maximum(2) Industrial
Maximum(2) Units
ICCINTQ Quiescent VCCINT supply current XC3S50A 2 20 30 mA
XC3S200A 7 50 70 mA
XC3S400A 10 85 125 mA
XC3S700A 13 120 185 mA
XC3S1400A 24 220 310 mA
ICCOQ Quiescent VCCO supply current XC3S50A 0.2 2 3 mA
XC3S200A 0.2 2 3 mA
XC3S400A 0.3 3 4 mA
XC3S700A 0.3 3 4 mA
XC3S1400A 0.3 3 4 mA
ICCAUXQ Quiescent VCCAUX supply current XC3S50A 3 8 10 mA
XC3S200A 5 12 15 mA
XC3S400A 5 18 24 mA
XC3S700A 6 28 34 mA
XC3S1400A 10 50 58 mA
Notes:
1. The numbers in this table are based on the conditions set forth in Table 8.
2. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads
disabled. Typical values are characterized using typical devices at room temperature (TJ of 25°C at VCCINT = 1.2V, VCCO = 3.3V, and VCCAUX
= 2.5V). The maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage
limits with VCCINT = 1.26V, VCCO = 3.6V, and VCCAUX = 3.6V. The FPGA is programmed with a “blank” configuration data file (that is, a design
with no functional elements instantiated). For conditions other than those described above (for example, a design including functional
elements), measured quiescent current levels will be different than the values in the table.
3. For more accurate estimates for a specific design, use the Xilinx XPower tools. There are two recommended ways to estimate the total power
consumption (quiescent plus dynamic) for a specific design: a) The Spartan-3A FPGA XPower Estimator provides quick, approximate,
typical estimates, and does not require a netlist of the design. b) XPower Analyzer uses a netlist as input to provide maximum estimates as
well as more accurate typical estimates.
4. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully.
5. For information on the power-saving Suspend mode, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs. Suspend mode
typically saves 40% total power consumption compared to quiescent current.
DC and Switching Characteristics
16 www.xilinx.com DS529 (v2.1) December 18, 2018
Single-Ended I/O Standards
Table 11: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
IOSTANDARD
Attribute
VCCO for Drivers(2) VREF VIL VIH
Min (V) Nom (V) Max (V) Min (V) Nom (V) Max (V) Max (V) Min (V)
LVTTL 3.0 3.3 3.6
VREF is not used for
these I/O standards
0.8 2.0
LVCMOS33(4) 3.0 3.3 3.6 0.8 2.0
LVCMOS25(4,5) 2.3 2.5 2.7 0.7 1.7
LVCMOS18 1.65 1.8 1.95 0.4 0.8
LVCMOS15 1.4 1.5 1.6 0.4 0.8
LVCMOS12 1.1 1.2 1.3 0.4 0.7
PCI33_3(6) 3.0 3.3 3.6 0.3 VCCO 0.5 VCCO
PCI66_3(6) 3.0 3.3 3.6 0.3 VCCO 0.5 VCCO
HSTL_I 1.4 1.5 1.6 0.68 0.75 0.9 VREF – 0.1 VREF + 0.1
HSTL_III 1.4 1.5 1.6 0.9 - VREF – 0.1 VREF + 0.1
HSTL_I_18 1.7 1.8 1.9 0.8 0.9 1.1 VREF – 0.1 VREF + 0.1
HSTL_II_18 1.7 1.8 1.9 0.9 – VREF – 0.1 VREF + 0.1
HSTL_III_18 1.7 1.8 1.9 1.1 – VREF – 0.1 VREF + 0.1
SSTL18_I 1.7 1.8 1.9 0.833 0.900 0.969 VREF – 0.125 VREF + 0.125
SSTL18_II 1.7 1.8 1.9 0.833 0.900 0.969 VREF – 0.125 VREF + 0.125
SSTL2_I 2.3 2.5 2.7 1.13 1.25 1.38 VREF – 0.150 VREF + 0.150
SSTL2_II 2.3 2.5 2.7 1.13 1.25 1.38 VREF – 0.150 VREF + 0.150
SSTL3_I 3.0 3.3 3.6 1.3 1.5 1.7 VREF – 0.2 VREF + 0.2
SSTL3_II 3.0 3.3 3.6 1.3 1.5 1.7 VREF – 0.2 VREF + 0.2
Notes:
1. Descriptions of the symbols used in this table are as follows:
VCCO – the supply voltage for output drivers
VREF – the reference voltage for setting the input switching threshold
VIL – the input voltage that indicates a Low logic level
VIH – the input voltage that indicates a High logic level
2. In general, the VCCO rails supply only output drivers, not input circuits. The exceptions are for LVCMOS25 inputs when VCCAUX = 3.3V range
and for PCI I/O standards.
3. For device operation, the maximum signal voltage (VIH max) can be as high as VIN max. See Table 8.
4. There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards.
5. All Dedicated pins (PROG_B, DONE, SUSPEND, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail and use the LVCMOS25 or
LVCMOS33 standard depending on VCCAUX. The dual-purpose configuration pins use the LVCMOS standard before the User mode. When
using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the VCCO lines of Banks 0, 1, and 2 at power-on as well as
throughout configuration.
6. For information on PCI IP solutions, see www.xilinx.com/pci. The PCI IOSTANDARD is not supported on input-only pins. The PCIX
IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported.
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 17
Table 12: DC Characteristics of User I/Os Using
Single-Ended Standards
IOSTANDARD
Attribute
Test
Conditions
Logic Level
Characteristics
IOL
(mA)
IOH
(mA)
VOL
Max (V)
VOH
Min (V)
LVTTL(3) 2 2 –2 0.4 2.4
444
666
888
12 12 –12
16 16 –16
24 24 –24
LVCMOS33(3) 2 2 –2 0.4 VCCO 0.4
444
666
888
12 12 –12
16 16 –16
24(4) 24 –24
LVCMOS25(3) 2 2 –2 0.4 VCCO 0.4
444
666
888
12 12 –12
16(4) 16 –16
24(4) 24 –24
LVCMOS18(3) 2 2 –2 0.4 VCCO 0.4
444
666
888
12(4) 12 –12
16(4) 16 –16
LVCMOS15(3) 2 2 –2 0.4 VCCO 0.4
444
666
8(4) 8–8
12(4) 12 –12
LVCMOS12(3) 2 2 –2 0.4 VCCO 0.4
4(4) 4–4
6(4) 6–6
PCI33_3(5) 1.5 –0.5 10% VCCO 90% VCCO
PCI66_3(5) 1.5 –0.5 10% VCCO 90% VCCO
HSTL_I(4) 8–8 0.4 V
CCO - 0.4
HSTL_III(4) 24 –8 0.4 VCCO - 0.4
HSTL_I_18 8 –8 0.4 VCCO - 0.4
HSTL_II_18(4) 16 –16 0.4 VCCO - 0.4
HSTL_III_18 24 –8 0.4 VCCO - 0.4
SSTL18_I 6.7 –6.7 VTT – 0.475 VTT + 0.475
SSTL18_II(4) 13.4 –13.4 VTT – 0.603 VTT + 0.603
SSTL2_I 8.1 –8.1 VTT – 0.61 VTT + 0.61
SSTL2_II(4) 16.2 –16.2 VTT – 0.81 VTT + 0.81
SSTL3_I 8 –8 VTT – 0.6 VTT + 0.6
SSTL3_II 16 –16 VTT – 0.8 VTT + 0.8
Notes:
1. The numbers in this table are based on the conditions set forth in
Table 8 and Table 11.
2. Descriptions of the symbols used in this table are as follows:
IOL the output current condition under which VOL is tested
IOH the output current condition under which VOH is tested
VOL the output voltage that indicates a Low logic level
VOH the output voltage that indicates a High logic level
VCCO the supply voltage for output drivers
VTT the voltage applied to a resistor termination
3. For the LVCMOS and LVTTL standards: the same VOL and VOH
limits apply for the Fast, Slow, and QUIETIO slew attributes.
4. These higher-drive output standards are supported only on
FPGA banks 1 and 3. Inputs are unrestricted. See the chapter
"Using I/O Resources" in UG331.
5. Tested according to the relevant PCI specifications. For
information on PCI IP solutions, see www.xilinx.com/pci. The
PCIX IOSTANDARD is available and has equivalent
characteristics but no PCI-X IP is supported.
Table 12: DC Characteristics of User I/Os Using
Single-Ended Standards(Continued)
IOSTANDARD
Attribute
Test
Conditions
Logic Level
Characteristics
IOL
(mA)
IOH
(mA)
VOL
Max (V)
VOH
Min (V)
DC and Switching Characteristics
18 www.xilinx.com DS529 (v2.1) December 18, 2018
Differential I/O Standards
Differential Input Pairs
Figure 4: Differential Input Voltages
Table 13: Recommended Operating Conditions for User I/Os Using Differential Signal Standards
IOSTANDARD Attribute
VCCO for Drivers(1) VID VICM(2)
Min (V) Nom (V) Max (V) Min (mV) Nom (mV) Max (mV) Min (V) Nom (V) Max (V)
LVDS_25(3) 2.25 2.5 2.75 100 350 600 0.3 1.25 2.35
LVDS_33(3) 3.0 3.3 3.6 100 350 600 0.3 1.25 2.35
BLVDS_25(4) 2.25 2.5 2.75 100 300 0.3 1.3 2.35
MINI_LVDS_25(3) 2.25 2.5 2.75 200 600 0.3 1.2 1.95
MINI_LVDS_33(3) 3.0 3.3 3.6 200 600 0.3 1.2 1.95
LVPECL_25(5) Inputs Only 100 800 1000 0.3 1.2 1.95
LVPECL_33(5) Inputs Only 100 800 1000 0.3 1.2 2.8(6)
RSDS_25(3) 2.25 2.5 2.75 100 200 –0.31.21.5
RSDS_33(3) 3.0 3.3 3.6 100 200 –0.31.21.5
TMDS_33(3, 4, 7) 3.14 3.3 3.47 150 –12002.7 –3.23
PPDS_25(3) 2.25 2.5 2.75 100 400 0.2 –2.3
PPDS_33(3) 3.0 3.3 3.6 100 400 0.2 –2.3
DIFF_HSTL_I_18 1.7 1.8 1.9 100 –0.8–1.1
DIFF_HSTL_II_18(8) 1.7 1.8 1.9 100 –0.8–1.1
DIFF_HSTL_III_18 1.7 1.8 1.9 100 –0.8–1.1
DIFF_HSTL_I 1.4 1.5 1.6 100 –0.68 0.9
DIFF_HSTL_III 1.4 1.5 1.6 100 –0.9
DIFF_SSTL18_I 1.7 1.8 1.9 100 –0.7–1.1
DIFF_SSTL18_II(8) 1.7 1.8 1.9 100 –0.7–1.1
DIFF_SSTL2_I 2.3 2.5 2.7 100 –1.0–1.5
DIFF_SSTL2_II(8) 2.3 2.5 2.7 100 –1.0–1.5
DIFF_SSTL3_I 3.0 3.3 3.6 100 –1.1–1.9
DIFF_SSTL3_II 3.0 3.3 3.6 100 –1.1–1.9
Notes:
1. The VCCO rails supply only differential output drivers, not input circuits.
2. VICM must be less than VCCAUX.
3. These true differential output standards are supported only on FPGA banks 0 and 2. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331.
4. See "External Termination Requirements for Differential I/O," page 20.
5. LVPECL is supported on inputs only, not outputs. LVPECL_33 requires VCCAUX=3.3V ± 10%.
6. LVPECL_33 maximum VICM = the lower of 2.8V or VCCAUX – (VID / 2)
7. Requires VCCAUX = 3.3V ± 10% for inputs. (VCCAUX – 300 mV) VICM (VCCAUX – 37 mV)
8. These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331.
9. All standards except for LVPECL and TMDS can have VCCAUX at either 2.5V or 3.3V. Define your VCCAUX level using the CONFIG VCCAUX constraint.
DS529-3_10_012907
VINN
VINP
GND level
50%
VICM
VICM = Input common mode voltage =
VID
VINP
Internal
Logic
Differential
I/O Pair Pins
VINN
N
P
2
VINP + VINN
VID = Differential input voltage = VINP - VINN
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 19
Differential Output Pairs
Figure 5: Differential Output Voltages
Table 14: DC Characteristics of User I/Os Using Differential Signal Standards
IOSTANDARD Attribute
VOD VOCM VOH VOL
Min (mV)
Typ
(mV) Max (mV) Min (V) Typ (V) Max (V) Min (V) Max (V)
LVDS_25 247 350 454 1.125 –1.375 – –
LVDS_33 247 350 454 1.125 –1.375 – –
BLVDS_25 240 350 460 –1.30 – –
MINI_LVDS_25 300 –600 1.0 –1.4 – –
MINI_LVDS_33 300 –600 1.0 –1.4 – –
RSDS_25 100 –400 1.0 –1.4 – –
RSDS_33 100 –400 1.0 –1.4 – –
TMDS_33 400 –800V
CCO – 0.405 –V
CCO – 0.190 – –
PPDS_25 100 – 400 0.5 0.8 1.4 – –
PPDS_33 100 – 400 0.5 0.8 1.4 – –
DIFF_HSTL_I_18 – – –V
CCO – 0.4 0.4
DIFF_HSTL_II_18 – – –V
CCO – 0.4 0.4
DIFF_HSTL_III_18 – – –V
CCO – 0.4 0.4
DIFF_HSTL_I VCCO – 0.4 0.4
DIFF_HSTL_III VCCO – 0.4 0.4
DIFF_SSTL18_I – – –V
TT + 0.475 VTT – 0.475
DIFF_SSTL18_II – – –V
TT + 0.603 VTT – 0.603
DIFF_SSTL2_I – – –V
TT + 0.61 VTT – 0.61
DIFF_SSTL2_II – – –V
TT + 0.81 VTT – 0.81
DIFF_SSTL3_I – – –V
TT + 0.6 VTT – 0.6
DIFF_SSTL3_II – – –V
TT + 0.8 VTT – 0.8
Notes:
1. The numbers in this table are based on the conditions set forth in Table 8 and Table 13.
2. See "External Termination Requirements for Differential I/O," page 20.
3. Output voltage measurements for all differential standards are made with a termination resistor (RT) of 100Ω across the N and P pins of the
differential signal pair.
4. At any given time, no more than two of the following differential output standards can be assigned to an I/O bank: LVDS_25, RSDS_25,
MINI_LVDS_25, PPDS_25 when VCCO=2.5V, or LVDS_33, RSDS_33, MINI_LVDS_33, TMDS_33, PPDS_33 when VCCO = 3.3V
VOUTN
VOUTP
GND level
50%
VOCM
V
OCM
VOD
V
OL
VOH
VOUTP
Internal
Logic VOUTN
N
P
= Output common mode voltage = 2
VOUTP +V
OUTN
V
OD = Output differential voltage =
V
OH = Output voltage indicating a High logic level
V
OL = Output voltage indicating a Low logic level
VOUTP -V
OUTN
Differential
I/O Pair Pins
DS529-3_11_012907
DC and Switching Characteristics
20 www.xilinx.com DS529 (v2.1) December 18, 2018
External Termination Requirements for Differential I/O
LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
BLVDS_25 I/O Standard
TMDS_33 I/O Standard
Device DNA Read Endurance
Figure 6: External Input Termination for LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
Figure 7: External Output and Input Termination Resistors for BLVDS_25 I/O Standard
Figure 8: External Input Resistors Required for TMDS_33 I/O Standard
Table 15: Device DNA Identifier Memory Characteristics
Symbol Description Minimum Units
DNA_CYCLES Number of READ operations or JTAG ISC_DNA read operations. Unaffected by
HOLD or SHIFT operations. 30,000,000 Read
cycles
Z0 = 50Ω
Z0 = 50Ω
140Ω
165Ω
165Ω
100Ω
VCCO = 2.5V No VCCO Requirement
DS529-3_07_020107
BLVDS_25 BLVDS_25
CAT16-LV4F12
Part Number
/ th of Bourns
14
CAT16-PT4F4
Part Number
/ th of Bourns
14
Bank 0
Bank 2
Bank 3
Bank 1
Any Bank
Bank 0
Bank 2
Bank 3
Bank 1
Any Bank
50Ω
VCCO = 3.3VVCCAUX = 3.3V
DS529-3_08_020107DVI/HDMI cable
50Ω
3.3V
TMDS_33 TMDS_33
Bank 0
Bank 2
Bank 0 and 2
Bank 0
Bank 2
Bank 3
Bank 1
Any Bank
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 21
Switching Characteristics
All Spartan-3A FPGAs ship in two speed grades: –4 and the
higher performance –5. Switching characteristics in this
document are designated as Advance, Preliminary, or
Production, as shown in Table 16. Each category is defined
as follows:
Advance: These specifications are based on simulations
only and are typically available soon after establishing
FPGA specifications. Although speed grades with this
designation are considered relatively stable and
conservative, some under-reporting might still occur.
Preliminary: These specifications are based on complete
early silicon characterization. Devices and speed grades
with this designation are intended to give a better indication
of the expected performance of production silicon. The
probability of under-reporting preliminary delays is greatly
reduced compared to Advance data.
Production: These specifications are approved once
enough production silicon of a particular device has been
characterized to provide full correlation between speed files
and devices over numerous production lots. There is no
under-reporting of delays, and customers receive formal
notification of any subsequent changes. Typically, the
slowest speed grades transition to Production before faster
speed grades.
Software Version Requirements
Production-quality systems must use FPGA designs
compiled using a speed file designated as PRODUCTION
status. FPGA designs using a less mature speed file
designation should only be used during system prototyping
or pre-production qualification. FPGA designs with speed
files designated as Advance or Preliminary should not be
used in a production-quality system.
Whenever a speed file designation changes, as a device
matures toward Production status, rerun the latest Xilinx®
ISE® software on the FPGA design to ensure that the FPGA
design incorporates the latest timing information and
software updates.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan-3A devices. AC and DC characteristics
are specified using the same numbers for both
commercial and industrial grades.
To create a Xilinx user account and sign up for automatic
E-mail notification whenever this data sheet is updated:
Sign Up for Alerts
www.xilinx.com/support/answers/18683.htm
Timing parameters and their representative values are
selected for inclusion below either because they are
important as general design requirements or they indicate
fundamental device performance characteristics. The
Spartan-3A FPGA speed files (v1.41), part of the Xilinx
Development Software, are the original source for many but
not all of the values. The speed grade designations for these
files are shown in Table 16. For more complete, more
precise, and worst-case data, use the values reported by the
Xilinx static timing analyzer (TRACE in the Xilinx
development software) and back-annotated to the
simulation netlist.
Table 17 provides the recent history of the Spartan-3A
FPGA speed files.
Table 16: Spartan-3A v1.41 Speed Grade Designation
Device Advance Preliminary Production
XC3S50A -4, -5
XC3S200A -4, -5
XC3S400A -4, -5
XC3S700A -4, -5
XC3S1400A -4, -5
Table 17: Spartan-3A Speed File Version History
Version
ISE
Release Description
1.41 ISE 10.1.03 Updated Automotive output delays
1.40 ISE 10.1.02 Updated Automotive input delays.
1.39 ISE 10.1.01 Added Automotive parts.
1.38 ISE 9.2.03i Added Absolute Minimum values.
1.37 ISE 9.2.01i
Updated pin-to-pin setup and hold
times (Table 19), TMDS output
adjustment (Table 26) multiplier
setup/hold times (Table 34), and block
RAM clock width (Table 35).
1.36
ISE 9.2i;
previously
available via
Answer
Record
AR24992
XC3S400A, all speed grades and all
temperature grades, upgraded to
Production
1.35
Answer
Record
AR24992
XC3S50A, XC3S200A, XC3S700A,
XC3S1400A, all speed grades and all
temperature grades, upgraded to
Production.
1.34 ISE 9.1.03i
XC3S700A and XC3S1400A -4 speed
grade upgraded to Production. Updated
pin-to-pin timing numbers.
DC and Switching Characteristics
22 www.xilinx.com DS529 (v2.1) December 18, 2018
I/O Timing
Pin-to-Pin Clock-to-Output Times
Table 18: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Symbol Description Conditions Device
Speed Grade
Units
-5 -4
Max Max
Clock-to-Output Times
TICKOFDCM When reading from the Output
Flip-Flop (OFF), the time from the
active transition on the Global
Clock pin to data appearing at the
Output pin. The DCM is in use.
LVCMOS25(2), 12mA
output drive, Fast slew
rate, with DCM(3)
XC3S50A 3.18 3.42 ns
XC3S200A 3.21 3.27 ns
XC3S400A 2.97 3.33 ns
XC3S700A 3.39 3.50 ns
XC3S1400A 3.51 3.99 ns
TICKOF When reading from OFF, the time
from the active transition on the
Global Clock pin to data appearing
at the Output pin. The DCM is not
in use.
LVCMOS25(2), 12mA
output drive, Fast slew
rate, without DCM
XC3S50A 4.59 5.02 ns
XC3S200A 4.88 5.24 ns
XC3S400A 4.68 5.12 ns
XC3S700A 4.97 5.34 ns
XC3S1400A 5.06 5.69 ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from Table 23. If the latter is true, add the appropriate Output adjustment from Table 26.
3. DCM output jitter is included in all measurements.
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 23
Pin-to-Pin Setup and Hold Times
Table 19: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Symbol Description Conditions Device
Speed Grade
Units
-5 -4
Min Min
Setup Times
TPSDCM When writing to the Input
Flip-Flop (IFF), the time from the
setup of data at the Input pin to
the active transition at a Global
Clock pin. The DCM is in use. No
Input Delay is programmed.
LVCMOS25(2),
IFD_DELAY_VALUE = 0,
with DCM(4)
XC3S50A 2.45 2.68 ns
XC3S200A 2.59 2.84 ns
XC3S400A 2.38 2.68 ns
XC3S700A 2.38 2.57 ns
XC3S1400A 1.91 2.17 ns
TPSFD When writing to IFF, the time from
the setup of data at the Input pin
to an active transition at the
Global Clock pin. The DCM is not
in use. The Input Delay is
programmed.
LVCMOS25(2),
IFD_DELAY_VALUE = 5,
without DCM
XC3S50A 2.55 2.76 ns
XC3S200A 2.32 2.76 ns
XC3S400A 2.21 2.60 ns
XC3S700A 2.28 2.63 ns
XC3S1400A 2.33 2.41 ns
Hold Times
TPHDCM When writing to IFF, the time from
the active transition at the Global
Clock pin to the point when data
must be held at the Input pin. The
DCM is in use. No Input Delay is
programmed.
LVCMOS25(3),
IFD_DELAY_VALUE = 0,
with DCM(4)
XC3S50A -0.36 -0.36 ns
XC3S200A -0.52 -0.52 ns
XC3S400A -0.33 -0.29 ns
XC3S700A -0.17 -0.12 ns
XC3S1400A -0.07 0.00 ns
TPHFD When writing to IFF, the time from
the active transition at the Global
Clock pin to the point when data
must be held at the Input pin. The
DCM is not in use. The Input
Delay is programmed.
LVCMOS25(3),
IFD_DELAY_VALUE = 5,
without DCM
XC3S50A -0.63 -0.58 ns
XC3S200A -0.56 -0.56 ns
XC3S400A -0.42 -0.42 ns
XC3S700A -0.80 -0.75 ns
XC3S1400A -0.69 -0.69 ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 23. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
3. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 23. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
4. DCM output jitter is included in all measurements.
DC and Switching Characteristics
24 www.xilinx.com DS529 (v2.1) December 18, 2018
Input Setup and Hold Times
Table 20: Setup and Hold Times for the IOB Input Path
Symbol Description Conditions
IFD_
DELAY_
VALUE Device
Speed Grade
Units
-5 -4
Min Min
Setup Times
TIOPICK Time from the setup of data at the
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
No Input Delay is programmed.
LVCMOS25(2) 0 XC3S50A 1.56 1.58 ns
XC3S200A 1.71 1.81 ns
XC3S400A 1.30 1.51 ns
XC3S700A 1.34 1.51 ns
XC3S1400A 1.36 1.74 ns
TIOPICKD Time from the setup of data at the
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
The Input Delay is programmed.
LVCMOS25(2) 1 XC3S50A 2.16 2.18 ns
23.103.12
ns
33.513.76ns
44.044.32ns
53.884.24
ns
64.725.09ns
75.475.94ns
85.976.52
ns
1XC3S200A 2.05 2.20 ns
22.722.93ns
33.383.78
ns
43.884.37ns
53.694.20ns
64.565.23
ns
75.346.11ns
85.856.71ns
1XC3S400A 1.79 2.02 ns
22.432.67ns
33.023.43ns
43.493.96
ns
53.413.95ns
64.204.81ns
74.965.66
ns
85.446.19ns
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 25
TIOPICKD Time from the setup of data at the
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
The Input Delay is programmed.
LVCMOS25(2) 1XC3S700A 1.82 1.95 ns
22.622.83
ns
33.323.72ns
43.834.31ns
53.694.14ns
64.605.19
ns
75.396.10ns
85.926.73ns
1 XC3S1400A 1.79 2.17 ns
22.552.92ns
33.383.76ns
43.754.32
ns
53.814.19ns
64.395.09ns
75.165.98
ns
85.696.57ns
Hold Times
TIOICKP Time from the active transition at the
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. No Input Delay is
programmed.
LVCMOS25(3) 0 XC3S50A –0.66 –0.64 ns
XC3S200A –0.85 –0.65 ns
XC3S400A –0.42 –0.42 ns
XC3S700A –0.81 –0.67 ns
XC3S1400A –0.71 –0.71 ns
TIOICKPD Time from the active transition at the
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. The Input Delay is
programmed.
LVCMOS25(3) 1 XC3S50A –0.88 –0.88 ns
2 –1.33 –1.33 ns
3 –2.05 –2.05 ns
4 –2.43 –2.43 ns
5 –2.34 –2.34 ns
6 –2.81 –2.81 ns
7 –3.03 –3.03 ns
8 –3.83 –3.57 ns
1 XC3S200A –1.51 1.51 ns
2 –2.09 –2.09 ns
3 –2.40 –2.40 ns
4 –2.68 –2.68 ns
5 –2.56 –2.56 ns
6 –2.99 –2.99 ns
7 –3.29 –3.29 ns
8 –3.61 –3.61 ns
Table 20: Setup and Hold Times for the IOB Input Path(Continued)
Symbol Description Conditions
IFD_
DELAY_
VALUE Device
Speed Grade
Units
-5 -4
Min Min
DC and Switching Characteristics
26 www.xilinx.com DS529 (v2.1) December 18, 2018
TIOICKPD Time from the active transition at the
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. The Input Delay is
programmed.
LVCMOS25(3) 1 XC3S400A –1.12 1.12 ns
2 –1.70 –1.70 ns
3 –2.08 –2.08 ns
4 –2.38 –2.38 ns
5 –2.23 –2.23 ns
6 –2.69 –2.69 ns
7 –3.08 –3.08 ns
8 –3.35 –3.35 ns
1 XC3S700A –1.67 1.67 ns
2 –2.27 –2.27 ns
3 –2.59 –2.59 ns
4 –2.92 –2.92 ns
5 –2.89 –2.89 ns
6 –3.22 –3.22 ns
7 –3.52 –3.52 ns
8 –3.81 –3.81 ns
1 XC3S1400A –1.60 –1.60 ns
2 –2.06 –2.06 ns
3 –2.46 –2.46 ns
4 –2.86 –2.86 ns
5 –2.88 –2.88 ns
6 –3.24 –3.24 ns
7 –3.55 –3.55 ns
8 –3.89 –3.89 ns
Set/Reset Pulse Width
TRPW_IOB Minimum pulse width to SR control
input on IOB
- - All 1.33 1.61 ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 23.
3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 23. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
Table 21: Sample Window (Source Synchronous)
Symbol Description Max Units
TSAMP Setup and hold
capture window of
an IOB flip-flop.
The input capture sample window value is highly specific to a particular application, device,
package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult the
appropriate Xilinx Answer Record for application-specific values.
Answer Record 30879
ps
Table 20: Setup and Hold Times for the IOB Input Path(Continued)
Symbol Description Conditions
IFD_
DELAY_
VALUE Device
Speed Grade
Units
-5 -4
Min Min
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 27
Input Propagation Times
Table 22: Propagation Times for the IOB Input Path
Symbol Description Conditions DELAY_VALUE Device
Speed Grade
Units
-5 -4
Max Max
Propagation Times
TIOPI The time it takes for data to travel
from the Input pin to the I output with
no input delay programmed
LVCMOS25(2) IBUF_DELAY_VALUE=0 XC3S50A 1.04 1.12 ns
XC3S200A 0.87 0.87 ns
XC3S400A 0.65 0.72 ns
XC3S700A 0.92 0.92 ns
XC3S1400A 0.96 1.21 ns
TIOPID The time it takes for data to travel
from the Input pin to the I output with
the input delay programmed
LVCMOS25(2) 1 XC3S50A 1.79 2.07 ns
2 2.13 2.46 ns
3 2.36 2.71 ns
4 2.88 3.21 ns
5 3.11 3.46 ns
6 3.45 3.84 ns
7 3.75 4.19 ns
8 4.00 4.47 ns
9 3.61 4.11 ns
10 3.95 4.50 ns
11 4.18 4.67 ns
12 4.75 5.20 ns
13 4.98 5.44 ns
14 5.31 5.95 ns
15 5.62 6.28 ns
16 5.86 6.57 ns
1 XC3S200A 1.57 1.65 ns
2 1.87 1.97 ns
3 2.16 2.33 ns
4 2.68 2.96 ns
5 2.87 3.19 ns
6 3.20 3.60 ns
7 3.57 4.02 ns
8 3.79 4.26 ns
9 3.42 3.86 ns
10 3.79 4.25 ns
11 4.02 4.55 ns
12 4.62 5.24 ns
13 4.86 5.53 ns
14 5.18 5.94 ns
DC and Switching Characteristics
28 www.xilinx.com DS529 (v2.1) December 18, 2018
TIOPID The time it takes for data to travel
from the Input pin to the I output with
the input delay programmed
LVCMOS25(2) 15 XC3S200A 5.43 6.24 ns
16 5.75 6.59 ns
1 XC3S400A 1.32 1.43 ns
2 1.67 1.83 ns
3 1.90 2.07 ns
4 2.33 2.52 ns
5 2.60 2.91 ns
6 2.94 3.20 ns
7 3.23 3.51 ns
8 3.50 3.85 ns
9 3.18 3.55 ns
10 3.53 3.95 ns
11 3.76 4.20 ns
12 4.26 4.67 ns
13 4.51 4.97 ns
14 4.85 5.32 ns
15 5.14 5.64 ns
16 5.40 5.95 ns
1 XC3S700A 1.84 1.87 ns
2 2.20 2.27 ns
3 2.46 2.60 ns
4 2.93 3.15 ns
5 3.21 3.45 ns
6 3.54 3.80 ns
7 3.86 4.16 ns
8 4.13 4.48 ns
9 3.82 4.19 ns
10 4.17 4.58 ns
11 4.43 4.89 ns
12 4.95 5.49 ns
13 5.22 5.83 ns
14 5.57 6.21 ns
15 5.89 6.55 ns
16 6.16 6.89 ns
1 XC3S1400A 1.95 2.18 ns
2 2.29 2.59 ns
3 2.54 2.84 ns
4 2.96 3.30 ns
Table 22: Propagation Times for the IOB Input Path(Continued)
Symbol Description Conditions DELAY_VALUE Device
Speed Grade
Units
-5 -4
Max Max
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 29
TIOPID The time it takes for data to travel
from the Input pin to the I output with
the input delay programmed
LVCMOS25(2) 5 XC3S1400A 3.17 3.52 ns
6 3.52 3.92 ns
7 3.82 4.18 ns
8 4.10 4.57 ns
9 3.84 4.31 ns
10 4.20 4.79 ns
11 4.46 5.06 ns
12 4.87 5.51 ns
13 5.07 5.73 ns
14 5.43 6.08 ns
15 5.73 6.33 ns
16 6.01 6.77 ns
TIOPLI The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with no input
delay programmed
LVCMOS25(2) IFD_DELAY_VALUE=0 XC3S50A 1.70 1.81 ns
XC3S200A 1.85 2.04 ns
XC3S400A 1.44 1.74 ns
XC3S700A 1.48 1.74 ns
XC3S1400A 1.50 1.97 ns
TIOPLID The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with the input
delay programmed
LVCMOS25(2) 1 XC3S50A 2.30 2.41 ns
2 3.24 3.35 ns
3 3.65 3.98 ns
4 4.18 4.55 ns
5 4.02 4.47 ns
6 4.86 5.32 ns
7 5.61 6.17 ns
8 6.11 6.75 ns
1 XC3S200A 2.19 2.43 ns
2 2.86 3.16 ns
3 3.52 4.01 ns
4 4.02 4.60 ns
5 3.83 4.43 ns
6 4.70 5.46 ns
7 5.48 6.33 ns
8 5.99 6.94 ns
1 XC3S400A 1.93 2.25 ns
2 2.57 2.90 ns
3 3.16 3.66 ns
4 3.63 4.19 ns
Table 22: Propagation Times for the IOB Input Path(Continued)
Symbol Description Conditions DELAY_VALUE Device
Speed Grade
Units
-5 -4
Max Max
DC and Switching Characteristics
30 www.xilinx.com DS529 (v2.1) December 18, 2018
TIOPLID The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with the input
delay programmed
LVCMOS25(2) 5 XC3S400A 3.55 4.18 ns
6 4.34 5.03 ns
7 5.09 5.88 ns
8 5.58 6.42 ns
1 XC3S700A 1.96 2.18 ns
2 2.76 3.06 ns
3 3.45 3.95 ns
4 3.97 4.54 ns
5 3.83 4.37 ns
6 4.74 5.42 ns
7 5.53 6.33 ns
8 6.06 6.96 ns
1 XC3S1400A 1.93 2.40 ns
2 2.69 3.15 ns
3 3.52 3.99 ns
4 3.89 4.55 ns
5 3.95 4.42 ns
6 4.53 5.32 ns
7 5.30 6.21 ns
8 5.83 6.80 ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from Table 23.
Table 22: Propagation Times for the IOB Input Path(Continued)
Symbol Description Conditions DELAY_VALUE Device
Speed Grade
Units
-5 -4
Max Max
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 31
Input Timing Adjustments
Table 23: Input Timing Adjustments by IOSTANDARD
Convert Input Time from
LVCMOS25 to the Following
Signal Standard
(IOSTANDARD)
Add the
Adjustment Below
Units
Speed Grade
-5 -4
Single-Ended Standards
LVTTL 0.62 0.62 ns
LVCMOS33 0.54 0.54 ns
LVCMOS25 0 0 ns
LVCMOS18 0.83 0.83 ns
LVCMOS15 0.60 0.60 ns
LVCMOS12 0.31 0.31 ns
PCI33_3 0.41 0.41 ns
PCI66_3 0.41 0.41 ns
HSTL_I 0.72 0.72 ns
HSTL_III 0.77 0.77 ns
HSTL_I_18 0.69 0.69 ns
HSTL_II_18 0.69 0.69 ns
HSTL_III_18 0.79 0.79 ns
SSTL18_I 0.71 0.71 ns
SSTL18_II 0.71 0.71 ns
SSTL2_I 0.68 0.68 ns
SSTL2_II 0.68 0.68 ns
SSTL3_I 0.78 0.78 ns
SSTL3_II 0.78 0.78 ns
Differential Standards
LVDS_25 0.76 0.76 ns
LVDS_33 0.79 0.79 ns
BLVDS_25 0.79 0.79 ns
MINI_LVDS_25 0.78 0.78 ns
MINI_LVDS_33 0.79 0.79 ns
LVPECL_25 0.78 0.78 ns
LVPECL_33 0.79 0.79 ns
RSDS_25 0.79 0.79 ns
RSDS_33 0.77 0.77 ns
TMDS_33 0.79 0.79 ns
PPDS_25 0.79 0.79 ns
PPDS_33 0.79 0.79 ns
DIFF_HSTL_I_18 0.74 0.74 ns
DIFF_HSTL_II_18 0.72 0.72 ns
DIFF_HSTL_III_18 1.05 1.05 ns
DIFF_HSTL_I 0.72 0.72 ns
DIFF_HSTL_III 1.05 1.05 ns
DIFF_SSTL18_I 0.71 0.71 ns
DIFF_SSTL18_II 0.71 0.71 ns
DIFF_SSTL2_I 0.74 0.74 ns
DIFF_SSTL2_II 0.75 0.75 ns
DIFF_SSTL3_I 1.06 1.06 ns
DIFF_SSTL3_II 1.06 1.06 ns
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 27 and are based on the operating conditions
set forth in Table 8, Table 11, and Table 13.
2. These adjustments are used to convert input path times originally
specified for the LVCMOS25 standard to times that correspond to
other signal standards.
Table 23: Input Timing Adjustments by IOSTANDARD(Continued)
Convert Input Time from
LVCMOS25 to the Following
Signal Standard
(IOSTANDARD)
Add the
Adjustment Below
Units
Speed Grade
-5 -4
DC and Switching Characteristics
32 www.xilinx.com DS529 (v2.1) December 18, 2018
Output Propagation Times
Three-State Output Propagation Times
Table 24: Timing for the IOB Output Path
Symbol Description Conditions Device
Speed Grade
Units
-5 -4
Max Max
Clock-to-Output Times
TIOCKP When reading from the Output Flip-Flop (OFF),
the time from the active transition at the OCLK
input to data appearing at the Output pin
LVCMOS25(2), 12 mA output
drive, Fast slew rate
All 2.87 3.13 ns
Propagation Times
TIOOP The time it takes for data to travel from the IOB’s
O input to the Output pin
LVCMOS25(2), 12 mA output
drive, Fast slew rate
All 2.78 2.91 ns
Set/Reset Times
TIOSRP Time from asserting the OFF’s SR input to
setting/resetting data at the Output pin
LVCMOS25(2), 12 mA output
drive, Fast slew rate
All 3.63 3.89 ns
TIOGSRQ Time from asserting the Global Set Reset (GSR)
input on the STARTUP_SPARTAN3A primitive to
setting/resetting data at the Output pin
8.62 9.65 ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 26.
Table 25: Timing for the IOB Three-State Path
Symbol Description Conditions Device
Speed Grade
Units
-5 -4
Max Max
Synchronous Output Enable/Disable Times
TIOCKHZ Time from the active transition at the OTCLK input of
the Three-state Flip-Flop (TFF) to when the Output
pin enters the high-impedance state
LVCMOS25, 12 mA
output drive, Fast slew
rate
All 0.63 0.76 ns
TIOCKON(2) Time from the active transition at TFF’s OTCLK input
to when the Output pin drives valid data
All 2.80 3.06 ns
Asynchronous Output Enable/Disable Times
TGTS Time from asserting the Global Three State (GTS)
input on the STARTUP_SPARTAN3A primitive to
when the Output pin enters the high-impedance
state
LVCMOS25, 12 mA
output drive, Fast slew
rate
All 9.47 10.36 ns
Set/Reset Times
TIOSRHZ Time from asserting TFF’s SR input to when the
Output pin enters a high-impedance state
LVCMOS25, 12 mA
output drive, Fast slew
rate
All 1.61 1.86 ns
TIOSRON(2) Time from asserting TFF’s SR input at TFF to when
the Output pin drives valid data
All 3.57 3.82 ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 26.
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 33
Output Timing Adjustments
Table 26: Output Timing Adjustments for IOB
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
Units
Speed Grade
-5 -4
Single-Ended Standards
LVTTL Slow 2 mA 5.58 5.58 ns
4 mA 3.16 3.16 ns
6 mA 3.17 3.17 ns
8 mA 2.09 2.09 ns
12 mA 1.62 1.62 ns
16 mA 1.24 1.24 ns
24 mA 2.74(3) 2.74(3) ns
Fast 2 mA 3.03 3.03 ns
4 mA 1.71 1.71 ns
6 mA 1.71 1.71 ns
8 mA 0.53 0.53 ns
12 mA 0.53 0.53 ns
16 mA 0.59 0.59 ns
24 mA 0.60 0.60 ns
QuietIO 2 mA 27.67 27.67 ns
4 mA 27.67 27.67 ns
6 mA 27.67 27.67 ns
8 mA 16.71 16.71 ns
12 mA 16.67 16.67 ns
16 mA 16.22 16.22 ns
24 mA 12.11 12.11 ns
LVCMOS33 Slow 2 mA 5.58 5.58 ns
4 mA 3.17 3.17 ns
6 mA 3.17 3.17 ns
8 mA 2.09 2.09 ns
12 mA 1.24 1.24 ns
16 mA 1.15 1.15 ns
24 mA 2.55(3) 2.55(3) ns
Fast 2 mA 3.02 3.02 ns
4 mA 1.71 1.71 ns
6 mA 1.72 1.72 ns
8 mA 0.53 0.53 ns
12 mA 0.59 0.59 ns
16 mA 0.59 0.59 ns
24 mA 0.51 0.51 ns
QuietIO 2 mA 27.67 27.67 ns
4 mA 27.67 27.67 ns
6 mA 27.67 27.67 ns
8 mA 16.71 16.71 ns
12 mA 16.29 16.29 ns
16 mA 16.18 16.18 ns
24 mA 12.11 12.11 ns
Table 26: Output Timing Adjustments for IOB(Continued)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
Units
Speed Grade
-5 -4
DC and Switching Characteristics
34 www.xilinx.com DS529 (v2.1) December 18, 2018
LVCMOS25 Slow 2 mA 5.33 5.33 ns
4 mA 2.81 2.81 ns
6 mA 2.82 2.82 ns
8 mA 1.14 1.14 ns
12 mA 1.10 1.10 ns
16 mA 0.83 0.83 ns
24 mA 2.26(3) 2.26(3) ns
Fast 2 mA 4.36 4.36 ns
4 mA 1.76 1.76 ns
6 mA 1.25 1.25 ns
8 mA 0.38 0.38 ns
12 mA 0 0 ns
16 mA 0.01 0.01 ns
24 mA 0.01 0.01 ns
QuietIO 2 mA 25.92 25.92 ns
4 mA 25.92 25.92 ns
6 mA 25.92 25.92 ns
8 mA 15.57 15.57 ns
12 mA 15.59 15.59 ns
16 mA 14.27 14.27 ns
24 mA 11.37 11.37 ns
LVCMOS18 Slow 2 mA 4.48 4.48 ns
4 mA 3.69 3.69 ns
6 mA 2.91 2.91 ns
8 mA 1.99 1.99 ns
12 mA 1.57 1.57 ns
16 mA 1.19 1.19 ns
Fast 2 mA 3.96 3.96 ns
4 mA 2.57 2.57 ns
6 mA 1.90 1.90 ns
8 mA 1.06 1.06 ns
12 mA 0.83 0.83 ns
16 mA 0.63 0.63 ns
QuietIO 2 mA 24.97 24.97 ns
4 mA 24.97 24.97 ns
6 mA 24.08 24.08 ns
8 mA 16.43 16.43 ns
12 mA 14.52 14.52 ns
16 mA 13.41 13.41 ns
Table 26: Output Timing Adjustments for IOB(Continued)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
Units
Speed Grade
-5 -4
LVCMOS15 Slow 2 mA 5.82 5.82 ns
4 mA 3.97 3.97 ns
6 mA 3.21 3.21 ns
8 mA 2.53 2.53 ns
12 mA 2.06 2.06 ns
Fast 2 mA 5.23 5.23 ns
4 mA 3.05 3.05 ns
6 mA 1.95 1.95 ns
8 mA 1.60 1.60 ns
12 mA 1.30 1.30 ns
QuietIO 2 mA 34.11 34.11 ns
4 mA 25.66 25.66 ns
6 mA 24.64 24.64 ns
8 mA 22.06 22.06 ns
12 mA 20.64 20.64 ns
LVCMOS12 Slow 2 mA 7.14 7.14 ns
4 mA 4.87 4.87 ns
6 mA 5.67 5.67 ns
Fast 2 mA 6.77 6.77 ns
4 mA 5.02 5.02 ns
6 mA 4.09 4.09 ns
QuietIO 2 mA 50.76 50.76 ns
4 mA 43.17 43.17 ns
6 mA 37.31 37.31 ns
PCI33_3 0.34 0.34 ns
PCI66_3 0.34 0.34 ns
HSTL_I 0.78 0.78 ns
HSTL_III 1.16 1.16 ns
HSTL_I_18 0.35 0.35 ns
HSTL_II_18 0.30 0.30 ns
HSTL_III_18 0.47 0.47 ns
SSTL18_I 0.40 0.40 ns
SSTL18_II 0.30 0.30 ns
SSTL2_I 0 0 ns
SSTL2_II 0.05 0.05 ns
SSTL3_I 0 0 ns
SSTL3_II 0.17 0.17 ns
Table 26: Output Timing Adjustments for IOB(Continued)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
Units
Speed Grade
-5 -4
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 35
Differential Standards
LVDS_25 1.16 1.16 ns
LVDS_33 0.46 0.46 ns
BLVDS_25 0.11 0.11 ns
MINI_LVDS_25 0.75 0.75 ns
MINI_LVDS_33 0.40 0.40 ns
LVPECL_25 Input Only
LVPECL_33
RSDS_25 1.42 1.42 ns
RSDS_33 0.58 0.58 ns
TMDS_33 0.46 0.46 ns
PPDS_25 1.07 1.07 ns
PPDS_33 0.63 0.63 ns
DIFF_HSTL_I_18 0.43 0.43 ns
DIFF_HSTL_II_18 0.41 0.41 ns
DIFF_HSTL_III_18 0.36 0.36 ns
DIFF_HSTL_I 1.01 1.01 ns
DIFF_HSTL_III 0.54 0.54 ns
DIFF_SSTL18_I 0.49 0.49 ns
DIFF_SSTL18_II 0.41 0.41 ns
DIFF_SSTL2_I 0.82 0.82 ns
DIFF_SSTL2_II 0.09 0.09 ns
DIFF_SSTL3_I 1.16 1.16 ns
DIFF_SSTL3_II 0.28 0.28 ns
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 27 and are based on the operating conditions
set forth in Table 8, Table 11, and Table 13.
2. These adjustments are used to convert output- and
three-state-path times originally specified for the LVCMOS25
standard with 12 mA drive and Fast slew rate to times that
correspond to other signal standards. Do not adjust times that
measure when outputs go into a high-impedance state.
3. Note that 16 mA drive is faster than 24 mA drive for the Slow
slew rate.
Table 26: Output Timing Adjustments for IOB(Continued)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
Units
Speed Grade
-5 -4
DC and Switching Characteristics
36 www.xilinx.com DS529 (v2.1) December 18, 2018
Timing Measurement Methodology
When measuring timing parameters at the programmable
I/Os, different signal standards call for different test
conditions. Table 27 lists the conditions to use for each
standard.
The method for measuring Input timing is as follows: A
signal that swings between a Low logic level of VL and a
High logic level of VH is applied to the Input under test.
Some standards also require the application of a bias
voltage to the VREF pins of a given bank to properly set the
input-switching threshold. The measurement point of the
Input signal (VM) is commonly located halfway between VL
and VH.
The Output test setup is shown in Figure 9. A termination
voltage VT is applied to the termination resistor RT, the other
end of which is connected to the Output. For each standard,
RT and VT generally take on the standard values
recommended for minimizing signal reflections. If the
standard does not ordinarily use terminations (for example,
LVCMOS, LVTTL), then RT is set to 1MΩ to indicate an open
connection, and VT is set to zero. The same measurement
point (VM) that was used at the Input is also used at the
Output.
Figure 9: Output Test Setup
FPGA Output
V
T
(V
REF
)
R
T
(R
REF
)
V
M
(V
MEAS
)
C
L
(C
REF
)
DS312-3_04_102406
Notes:
1. The names shown in parentheses are
used in the IBIS file.
Table 27: Test Methods for Timing Measurement at I/Os
Signal Standard
(IOSTANDARD)
Inputs Outputs
Inputs and
Outputs
VREF (V) VL (V) VH (V) RT (Ω)V
T (V) VM (V)
Single-Ended
LVTTL - 0 3.3 1M 0 1.4
LVCMOS33 - 0 3.3 1M 0 1.65
LVCMOS25 - 0 2.5 1M 0 1.25
LVCMOS18 - 0 1.8 1M 0 0.9
LVCMOS15 - 0 1.5 1M 0 0.75
LVCMOS12 - 0 1.2 1M 0 0.6
PCI33_3 Rising - Note 3 Note 3 25 0 0.94
Falling 25 3.3 2.03
PCI66_3 Rising - Note 3 Note 3 25 0 0.94
Falling 25 3.3 2.03
HSTL_I 0.75 VREF – 0.5 VREF + 0.5 50 0.75 VREF
HSTL_III 0.9 VREF – 0.5 VREF + 0.5 50 1.5 VREF
HSTL_I_18 0.9 VREF – 0.5 VREF + 0.5 50 0.9 VREF
HSTL_II_18 0.9 VREF – 0.5 VREF + 0.5 25 0.9 VREF
HSTL_III_18 1.1 VREF – 0.5 VREF + 0.5 50 1.8 VREF
SSTL18_I 0.9 VREF – 0.5 VREF + 0.5 50 0.9 VREF
SSTL18_II 0.9 VREF – 0.5 VREF + 0.5 25 0.9 VREF
SSTL2_I 1.25 VREF – 0.75 VREF + 0.75 50 1.25 VREF
SSTL2_II 1.25 VREF – 0.75 VREF + 0.75 25 1.25 VREF
SSTL3_I 1.5 VREF – 0.75 VREF + 0.75 50 1.5 VREF
SSTL3_II 1.5 VREF – 0.75 VREF + 0.75 25 1.5 VREF
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 37
The capacitive load (CL) is connected between the output and GND. The Output timing for all standards, as published in the
speed files and the data sheet, is always based on a CL value of zero. High-impedance probes (less than 1 pF) are used for
all measurements. Any delay that the test fixture might contribute to test measurements is subtracted from those
measurements to produce the final timing numbers as published in the speed files and data sheet.
Differential
LVDS_25 -V
ICM – 0.125 VICM + 0.125 50 1.2 VICM
LVDS_33 -V
ICM – 0.125 VICM + 0.125 50 1.2 VICM
BLVDS_25 -V
ICM – 0.125 VICM + 0.125 1M 0 VICM
MINI_LVDS_25 -V
ICM – 0.125 VICM + 0.125 50 1.2 VICM
MINI_LVDS_33 -V
ICM – 0.125 VICM + 0.125 50 1.2 VICM
LVPECL_25 -V
ICM – 0.3 VICM + 0.3 N/A N/A VICM
LVPECL_33 -V
ICM – 0.3 VICM + 0.3 N/A N/A VICM
RSDS_25 -V
ICM – 0.1 VICM + 0.1 50 1.2 VICM
RSDS_33 -V
ICM – 0.1 VICM + 0.1 50 1.2 VICM
TMDS_33 -V
ICM – 0.1 VICM + 0.1 50 3.3 VICM
PPDS_25 -V
ICM – 0.1 VICM + 0.1 50 0.8 VICM
PPDS_33 -V
ICM – 0.1 VICM + 0.1 50 0.8 VICM
DIFF_HSTL_I -V
ICM – 0.5 VICM + 0.5 50 0.75 VICM
DIFF_HSTL_III -V
ICM – 0.5 VICM + 0.5 50 1.5 VICM
DIFF_HSTL_I_18 -V
ICM – 0.5 VICM + 0.5 50 0.9 VICM
DIFF_HSTL_II_18 -V
ICM – 0.5 VICM + 0.5 50 0.9 VICM
DIFF_HSTL_III_18 -V
ICM – 0.5 VICM + 0.5 50 1.8 VICM
DIFF_SSTL18_I -V
ICM – 0.5 VICM + 0.5 50 0.9 VICM
DIFF_SSTL18_II -V
ICM – 0.5 VICM + 0.5 50 0.9 VICM
DIFF_SSTL2_I -V
ICM – 0.5 VICM + 0.5 50 1.25 VICM
DIFF_SSTL2_II -V
ICM – 0.5 VICM + 0.5 50 1.25 VICM
DIFF_SSTL3_I -V
ICM – 0.5 VICM + 0.5 50 1.5 VICM
DIFF_SSTL3_II -V
ICM – 0.5 VICM + 0.5 50 1.5 VICM
Notes:
1. Descriptions of the relevant symbols are as follows:
VREF – The reference voltage for setting the input switching threshold
VICM – The common mode input voltage
VM – Voltage of measurement point on signal transition
VL – Low-level test voltage at Input pin
VH – High-level test voltage at Input pin
RT – Effective termination resistance, which takes on a value of 1 MΩ when no parallel termination is required
VT – Termination voltage
2. The load capacitance (CL) at the Output pin is 0 pF for all signal standards.
3. According to the PCI specification.
Table 27: Test Methods for Timing Measurement at I/Os(Continued)
Signal Standard
(IOSTANDARD)
Inputs Outputs
Inputs and
Outputs
VREF (V) VL (V) VH (V) RT (Ω)V
T (V) VM (V)
DC and Switching Characteristics
38 www.xilinx.com DS529 (v2.1) December 18, 2018
Using IBIS Models to Simulate Load Conditions in Application
IBIS models permit the most accurate prediction of timing
delays for a given application. The parameters found in the
IBIS model (VREF, RREF, and VMEAS) correspond directly
with the parameters used in Table 27 (VT, RT, and VM). Do
not confuse VREF (the termination voltage) from the IBIS
model with VREF (the input-switching threshold) from the
table. A fourth parameter, CREF, is always zero. The four
parameters describe all relevant output test conditions. IBIS
models are found in the Xilinx development software as well
as at the following link:
www.xilinx.com/support/download/index.htm
Delays for a given application are simulated according to its
specific load conditions as follows:
1. Simulate the desired signal standard with the output
driver connected to the test setup shown in Figure 9.
Use parameter values VT, RT, and VM from Table 27.
CREF is zero.
2. Record the time to VM.
3. Simulate the same signal standard with the output driver
connected to the PCB trace with load. Use the
appropriate IBIS model (including VREF, RREF, CREF,
and VMEAS values) or capacitive value to represent the
load.
4. Record the time to VMEAS.
5. Compare the results of steps 2 and 4. Add (or subtract)
the increase (or decrease) in delay to (or from) the
appropriate Output standard adjustment (Table 26) to
yield the worst-case delay of the PCB trace.
Simultaneously Switching Output Guidelines
This section provides guidelines for the recommended
maximum allowable number of Simultaneous Switching
Outputs (SSOs). These guidelines describe the maximum
number of user I/O pins of a given output signal standard
that should simultaneously switch in the same direction,
while maintaining a safe level of switching noise. Meeting
these guidelines for the stated test conditions ensures that
the FPGA operates free from the adverse effects of ground
and power bounce.
Ground or power bounce occurs when a large number of
outputs simultaneously switch in the same direction. The
output drive transistors all conduct current to a common
voltage rail. Low-to-High transitions conduct to the VCCO
rail; High-to-Low transitions conduct to the GND rail. The
resulting cumulative current transient induces a voltage
difference across the inductance that exists between the die
pad and the power supply or ground return. The inductance
is associated with bonding wires, the package lead frame,
and any other signal routing inside the package. Other
variables contribute to SSO noise levels, including stray
inductance on the PCB as well as capacitive loading at
receivers. Any SSO-induced voltage consequently affects
internal switching noise margins and ultimately signal
quality.
Table 28 and Table 29 provide the essential SSO guidelines.
For each device/package combination, Table 28 provides
the number of equivalent VCCO/GND pairs. The equivalent
number of pairs is based on characterization and may not
match the physical number of pairs. For each output signal
standard and drive strength, Table 29 recommends the
maximum number of SSOs, switching in the same direction,
allowed per VCCO/GND pair within an I/O bank. The
guidelines in Table 29 are categorized by package style,
slew rate, and output drive current. Furthermore, the
number of SSOs is specified by I/O bank. Generally, the left
and right I/O banks (Banks 1 and 3) support higher output
drive current.
Multiply the appropriate numbers from Table 28 and
Table 29 to calculate the maximum number of SSOs allowed
within an I/O bank. Exceeding these SSO guidelines might
result in increased power or ground bounce, degraded
signal integrity, or increased system jitter.
SSOMAX/IO Bank = Table 28 x Table 29
The recommended maximum SSO values assume that the
FPGA is soldered on the printed circuit board and that the
board uses sound design practices. The SSO values do not
apply for FPGAs mounted in sockets, due to the lead
inductance introduced by the socket.
The SSO values assume that the VCCAUX is powered at
3.3V. Setting VCCAUX to 2.5V provides better SSO
characteristics.
The number of SSOs allowed for quad-flat packages
(VQ/TQ) is lower than for ball grid array packages (FG) due
to the larger lead inductance of the quad-flat packages. Ball
grid array packages are recommended for applications with
a large number of simultaneously switching outputs.
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 39
Table 28: Equivalent VCCO/GND Pairs per Bank
Device
Package Style (including Pb-free)
VQ100 TQ144 FT256 FG320 FG400 FG484 FG676
XC3S50A 1 2 3 – – – –
XC3S200A 1 –44– – –
XC3S400A –445– –
XC3S700A –4–55
XC3S1400A –4–69
Table 29: Recommended Number of Simultaneously Switching
Outputs per VCCO-GND Pair (VCCAUX=3.3V)
Signal Standard
(IOSTANDARD)
Package Type
VQ100, TQ144
FT256, FG320,
FG400, FG484,
FG676
Top,
Bottom
(Banks
0,2)
Left,
Right
(Banks
1,3)
Top,
Bottom
(Banks
0,2)
Left,
Right
(Banks
1,3)
Single-Ended Standards
LVTTL Slow 2 20 20 60 60
410 10 41 41
610 10 29 29
86 6 22 22
12 6 6 13 13
16 5 5 11 11
24 4 4 9 9
Fast 2 10 10 10 10
46 6 6 6
65 5 5 5
83 3 3 3
12 3 3 3 3
16 3 3 3 3
24 2 2 2 2
QuietIO 2 40 40 80 80
424 24 48 48
620 20 36 36
816 16 27 27
12 12 12 16 16
16 9 9 13 13
24 9 9 12 12
LVCMOS33 Slow 2 24 24 76 76
414 14 46 46
611 11 27 27
810 10 20 20
12 9 9 13 13
16 8 8 10 10
24 –8–9
Fast 2 10 10 10 10
48 8 8 8
65 5 5 5
84 4 4 4
12 4 4 4 4
16 2 2 2 2
24 –2–2
QuietIO 2 36 36 76 76
432 32 46 46
624 24 32 32
816 16 26 26
12 16 16 18 18
16 12 12 14 14
24 –10–10
Table 29: Recommended Number of Simultaneously Switching
Outputs per VCCO-GND Pair (VCCAUX=3.3V)(Continued)
Signal Standard
(IOSTANDARD)
Package Type
VQ100, TQ144
FT256, FG320,
FG400, FG484,
FG676
Top,
Bottom
(Banks
0,2)
Left,
Right
(Banks
1,3)
Top,
Bottom
(Banks
0,2)
Left,
Right
(Banks
1,3)
DC and Switching Characteristics
40 www.xilinx.com DS529 (v2.1) December 18, 2018
LVCMOS25 Slow 2 16 16 76 76
410 10 46 46
68 8 33 33
87 7 24 24
12 6 6 18 18
16 –6–11
24 –5–7
Fast 2 12 12 18 18
410 10 14 14
68 8 6 6
86 6 6 6
12 3 3 3 3
16 –3–3
24 –2–2
QuietIO 2 36 36 76 76
430 30 60 60
624 24 48 48
820 20 36 36
12 12 12 36 36
16 –12–36
24 –8–8
LVCMOS18 Slow 2 13 13 64 64
48 8 34 34
68 8 22 22
87 7 18 18
12 –5–13
16 –5–10
Fast 2 13 13 18 18
48 8 9 9
67 7 7 7
84 4 4 4
12 –4–4
16 –3–3
QuietIO 2 30 30 64 64
424 24 64 64
620 20 48 48
816 16 36 36
12 –12–36
16 –12–24
Table 29: Recommended Number of Simultaneously Switching
Outputs per VCCO-GND Pair (VCCAUX=3.3V)(Continued)
Signal Standard
(IOSTANDARD)
Package Type
VQ100, TQ144
FT256, FG320,
FG400, FG484,
FG676
Top,
Bottom
(Banks
0,2)
Left,
Right
(Banks
1,3)
Top,
Bottom
(Banks
0,2)
Left,
Right
(Banks
1,3)
LVCMOS15 Slow 2 12 12 55 55
47 7 31 31
67 7 18 18
8–6–15
12 –5–10
Fast 2 10 10 25 25
47 7 10 10
66 6 6 6
8–4–4
12 –3–3
QuietIO 2 30 30 70 70
421 21 40 40
618 18 31 31
8–12–31
12 –12–20
LVCMOS12 Slow 2 17 17 40 40
4–13–25
6–10–18
Fast 2 12 9 31 31
4–9–13
6–9–9
QuietIO 2 36 36 55 55
4–33–36
6–27–36
PCI33_3 9 9 16 16
PCI66_3 –9–13
HSTL_I –11–20
HSTL_III –7–8
HSTL_I_18 13 13 17 17
HSTL_II_18 –5–5
HSTL_III_18 8 8 10 8
SSTL18_I 7 13 7 15
SSTL18_II –9–9
SSTL2_I 10 10 18 18
SSTL2_II –6–9
SSTL3_I 7 8 8 10
SSTL3_II 5 6 6 7
Table 29: Recommended Number of Simultaneously Switching
Outputs per VCCO-GND Pair (VCCAUX=3.3V)(Continued)
Signal Standard
(IOSTANDARD)
Package Type
VQ100, TQ144
FT256, FG320,
FG400, FG484,
FG676
Top,
Bottom
(Banks
0,2)
Left,
Right
(Banks
1,3)
Top,
Bottom
(Banks
0,2)
Left,
Right
(Banks
1,3)
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 41
Differential Standards (Number of I/O Pairs or Channels)
LVDS_25 8 –22
LVDS_33 8 –27
BLVDS_25 1 1 4 4
MINI_LVDS_25 8 –22
MINI_LVDS_33 8 –27
LVPECL_25 Input Only
LVPECL_33 Input Only
RSDS_25 8 –22
RSDS_33 8 –27
TMDS_33 8 –27
PPDS_25 8 –22
PPDS_33 8 –27
DIFF_HSTL_I –5–10
DIFF_HSTL_III –3–4
DIFF_HSTL_I_18 6 6 8 8
DIFF_HSTL_II_18 –2–2
DIFF_HSTL_III_18 4 4 5 4
DIFF_SSTL18_I 3 6 3 7
DIFF_SSTL18_II –4–4
DIFF_SSTL2_I 5 5 9 9
DIFF_SSTL2_II –3–4
DIFF_SSTL3_I 3 4 4 5
DIFF_SSTL3_II 2 3 3 3
Notes:
1. Not all I/O standards are supported on all I/O banks. The left and
right banks (I/O banks 1 and 3) support higher output drive
current than the top and bottom banks (I/O banks 0 and 2).
Similarly, true differential output standards, such as LVDS,
RSDS, PPDS, miniLVDS, and TMDS, are only supported in top
or bottom banks (I/O banks 0 and 2). Refer to UG331: Spartan-3
Generation FPGA User Guide for additional information.
2. The numbers in this table are recommendations that assume
sound board lay out practice. Test limits are the VIL/VIH voltage
limits for the respective I/O standard.
3. If more than one signal standard is assigned to the I/Os of a given
bank, refer to XAPP689: Managing Ground Bounce in Large
FPGAs for information on how to perform weighted average SSO
calculations.
Table 29: Recommended Number of Simultaneously Switching
Outputs per VCCO-GND Pair (VCCAUX=3.3V)(Continued)
Signal Standard
(IOSTANDARD)
Package Type
VQ100, TQ144
FT256, FG320,
FG400, FG484,
FG676
Top,
Bottom
(Banks
0,2)
Left,
Right
(Banks
1,3)
Top,
Bottom
(Banks
0,2)
Left,
Right
(Banks
1,3)
DC and Switching Characteristics
42 www.xilinx.com DS529 (v2.1) December 18, 2018
Configurable Logic Block (CLB) Timing
Table 30: CLB (SLICEM) Timing
Symbol Description
Speed Grade
Units
-5 -4
Min Max Min Max
Clock-to-Output Times
TCKO When reading from the FFX (FFY) Flip-Flop, the time
from the active transition at the CLK input to data
appearing at the XQ (YQ) output
–0.60–0.68ns
Setup Times
TAS Time from the setup of data at the F or G input to the
active transition at the CLK input of the CLB 0.18 –0.36–ns
TDICK Time from the setup of data at the BX or BY input to
the active transition at the CLK input of the CLB 1.58 –1.88–ns
Hold Times
TAH Time from the active transition at the CLK input to the
point where data is last held at the F or G input 0–0–ns
TCKDI Time from the active transition at the CLK input to the
point where data is last held at the BX or BY input 0–0–ns
Clock Timing
TCH The High pulse width of the CLB’s CLK signal 0.63 –0.75–ns
TCL The Low pulse width of the CLK signal 0.63 –0.75–ns
FTOG Toggle frequency (for export control) 0 770 0 667 MHz
Propagation Times
TILO The time it takes for data to travel from the CLB’s F
(G) input to the X (Y) output –0.62–0.71ns
Set/Reset Pulse Width
TRPW_CLB The minimum allowable pulse width, High or Low, to
the CLB’s SR input 1.33 –1.61–ns
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 43
Table 31: CLB Distributed RAM Switching Characteristics
Symbol Description
-5 -4
UnitsMin Max Min Max
Clock-to-Output Times
TSHCKO Time from the active edge at the CLK input to data appearing on
the distributed RAM output –1.69–2.01ns
Setup Times
TDS Setup time of data at the BX or BY input before the active
transition at the CLK input of the distributed RAM 0.07 0.02 –ns
TAS Setup time of the F/G address inputs before the active transition
at the CLK input of the distributed RAM 0.18 –0.36–ns
TWS Setup time of the write enable input before the active transition at
the CLK input of the distributed RAM 0.30 –0.59–ns
Hold Times
TDH Hold time of the BX and BY data inputs after the active transition
at the CLK input of the distributed RAM 0.13 –0.13–ns
TAH, TWH Hold time of the F/G address inputs or the write enable input after
the active transition at the CLK input of the distributed RAM 0.01 –0.01–ns
Clock Pulse Width
TWPH, TWPL Minimum High or Low pulse width at CLK input 0.88 –1.01–ns
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
Table 32: CLB Shift Register Switching Characteristics
Symbol Description
-5 -4
UnitsMin Max Min Max
Clock-to-Output Times
TREG Time from the active edge at the CLK input to data appearing on
the shift register output –4.11–4.82ns
Setup Times
TSRLDS Setup time of data at the BX or BY input before the active
transition at the CLK input of the shift register 0.13 –0.18–ns
Hold Times
TSRLDH Hold time of the BX or BY data input after the active transition at
the CLK input of the shift register 0.16 –0.16–ns
Clock Pulse Width
TWPH, TWPL Minimum High or Low pulse width at CLK input 0.90 –1.01–ns
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
DC and Switching Characteristics
44 www.xilinx.com DS529 (v2.1) December 18, 2018
Clock Buffer/Multiplexer Switching Characteristics
Table 33: Clock Distribution Switching Characteristics
Description Symbol Minimum
Maximum
Units
Speed Grade
-5 -4
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to
O-output delay TGIO –0.220.23ns
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and
I1 inputs. Same as BUFGCE enable CE-input TGSI –0.560.63ns
Frequency of signals distributed on global buffers (all sides) FBUFG 0350334MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 45
18 x 18 Embedded Multiplier Timing
Table 34: 18 x 18 Embedded Multiplier Timing
Symbol Description
Speed Grade
Units
-5 -4
Min Max Min Max
Combinatorial Delay
TMULT Combinational multiplier propagation delay from the A and B inputs
to the P outputs, assuming 18-bit inputs and a 36-bit product
(AREG, BREG, and PREG registers unused)
–4.36–4.88ns
Clock-to-Output Times
TMSCKP_P Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using the PREG
register(2,3) –0.84–1.30ns
TMSCKP_A
TMSCKP_B
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using either the AREG
or BREG register(2,4) –4.44–4.97ns
Setup Times
TMSDCK_P Data setup time at the A or B input before the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)(3) 3.56 –3.98–ns
TMSDCK_A Data setup time at the A input before the active transition at the CLK
when using the AREG input register(4) 0.00 –0.00–ns
TMSDCK_B Data setup time at the B input before the active transition at the CLK
when using the BREG input register(4) 0.00 –0.00–ns
Hold Times
TMSCKD_P Data hold time at the A or B input after the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)(3) 0.00 –0.00–ns
TMSCKD_A Data hold time at the A input after the active transition at the CLK
when using the AREG input register(4) 0.35 –0.45–ns
TMSCKD_B Data hold time at the B input after the active transition at the CLK
when using the BREG input register(4) 0.35 –0.45–ns
Clock Frequency
FMULT Internal operating frequency for a two-stage 18x18 multiplier using
the AREG and BREG input registers and the PREG output
register(1) 0 280 0 250 MHz
Notes:
1. Combinational delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
2. The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
3. The PREG register is typically used when inferring a single-stage multiplier.
4. Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
5. The numbers in this table are based on the operating conditions set forth in Table 8.
DC and Switching Characteristics
46 www.xilinx.com DS529 (v2.1) December 18, 2018
Block RAM Timing
Table 35: Block RAM Timing
Symbol Description
Speed Grade
Units
-5 -4
MinMaxMinMax
Clock-to-Output Times
TRCKO When reading from block RAM, the delay from the active
transition at the CLK input to data appearing at the DOUT
output
–2.06–2.49ns
Setup Times
TRCCK_ADDR Setup time for the ADDR inputs before the active transition at
the CLK input of the block RAM 0.32 –0.36–ns
TRDCK_DIB Setup time for data at the DIN inputs before the active
transition at the CLK input of the block RAM 0.28 –0.31–ns
TRCCK_ENB Setup time for the EN input before the active transition at the
CLK input of the block RAM 0.69 –0.77–ns
TRCCK_WEB Setup time for the WE input before the active transition at the
CLK input of the block RAM 1.12 –1.26–ns
Hold Times
TRCKC_ADDR Hold time on the ADDR inputs after the active transition at the
CLK input 0–0–ns
TRCKD_DIB Hold time on the DIN inputs after the active transition at the
CLK input 0–0–ns
TRCKC_ENB Hold time on the EN input after the active transition at the CLK
input 0–0–ns
TRCKC_WEB Hold time on the WE input after the active transition at the CLK
input 0–0–ns
Clock Timing
TBPWH High pulse width of the CLK signal 1.56 –1.79–ns
TBPWL Low pulse width of the CLK signal 1.56 –1.79–ns
Clock Frequency
FBRAM Block RAM clock frequency 0 320 0 280 MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 47
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key
components: the Delay-Locked Loop (DLL), the Digital
Frequency Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM applications.
All such applications inevitably use the CLKIN and the
CLKFB inputs connected to either the CLK0 or the CLK2X
feedback, respectively. Thus, specifications in the DLL
tables (Table 36 and Table 37) apply to any application that
only employs the DLL component. When the DFS and/or the
PS components are used together with the DLL, then the
specifications listed in the DFS and PS tables (Table 38
through Table 41) supersede any corresponding ones in the
DLL tables. DLL specifications that do not change with the
addition of DFS or PS functions are presented in Table 36
and Table 37.
Period jitter and cycle-cycle jitter are two of many different
ways of specifying clock jitter. Both specifications describe
statistical variation from a mean value.
Period jitter is the worst-case deviation from the ideal clock
period over a collection of millions of samples. In a
histogram of period jitter, the mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period
between adjacent clock cycles in the collection of clock
periods sampled. In a histogram of cycle-cycle jitter, the
mean value is zero.
Spread Spectrum
DCMs accept typical spread spectrum clocks as long as
they meet the input requirements. The DLL will track the
frequency changes created by the spread spectrum clock to
drive the global clocks to the FPGA logic. See XAPP469,
Spread-Spectrum Clocking Reception for Displays for
details.
Delay-Locked Loop (DLL)
Table 36: Recommended Operating Conditions for the DLL
Symbol Description
Speed Grade
Units
-5 -4
Min Max Min Max
Input Frequency Ranges
FCLKIN CLKIN_FREQ_DLL Frequency of the CLKIN clock input 5(2) 280(3) 5(2) 250(3) MHz
Input Pulse Requirements
CLKIN_PULSE CLKIN pulse width as a
percentage of the CLKIN
period
FCLKIN < 150 MHz 40% 60% 40% 60%
FCLKIN > 150 MHz 45% 55% 45% 55%
Input Clock Jitter Tolerance and Delay Path Variation(4)
CLKIN_CYC_JITT_DLL_LF Cycle-to-cycle jitter at the
CLKIN input
FCLKIN < 150 MHz –±300–±300ps
CLKIN_CYC_JITT_DLL_HF FCLKIN > 150 MHz –±150–±150ps
CLKIN_PER_JITT_DLL Period jitter at the CLKIN input –±1–±1ns
CLKFB_DELAY_VAR_EXT Allowable variation of off-chip feedback delay
from the DCM output to the CLKFB input ±1 ±1 ns
Notes:
1. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2. The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 38.
3. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input.
4. CLKIN input jitter beyond these limits might cause the DCM to lose lock.
5. The DCM specifications are guaranteed when both adjacent DCMs are locked.
DC and Switching Characteristics
48 www.xilinx.com DS529 (v2.1) December 18, 2018
Table 37: Switching Characteristics for the DLL
Symbol Description Device
Speed Grade
Units
-5 -4
Min Max Min Max
Output Frequency Ranges
CLKOUT_FREQ_CLK0 Frequency for the CLK0 and CLK180 outputs All 5 280 5 250 MHz
CLKOUT_FREQ_CLK90 Frequency for the CLK90 and CLK270 outputs 5 200 5 200 MHz
CLKOUT_FREQ_2X Frequency for the CLK2X and CLK2X180 outputs 10 334 10 334 MHz
CLKOUT_FREQ_DV Frequency for the CLKDV output 0.3125 186 0.3125 166 MHz
Output Clock Jitter(2,3,4)
CLKOUT_PER_JITT_0 Period jitter at the CLK0 output All ±100 ±100 ps
CLKOUT_PER_JITT_90 Period jitter at the CLK90 output ±150 ±150 ps
CLKOUT_PER_JITT_180 Period jitter at the CLK180 output ±150 ±150 ps
CLKOUT_PER_JITT_270 Period jitter at the CLK270 output ±150 ±150 ps
CLKOUT_PER_JITT_2X Period jitter at the CLK2X and CLK2X180 outputs
±[0.5%
of CLKIN
period
+ 100]
±[0.5%
of CLKIN
period
+ 100]
ps
CLKOUT_PER_JITT_DV1 Period jitter at the CLKDV output when performing integer
division ±150 ±150 ps
CLKOUT_PER_JITT_DV2 Period jitter at the CLKDV output when performing non-integer
division
±[0.5%
of CLKIN
period
+ 100]
±[0.5%
of CLKIN
period
+ 100]
ps
Duty Cycle(4)
CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0, CLK90, CLK180, CLK270,
CLK2X, CLK2X180, and CLKDV outputs, including the
BUFGMUX and clock tree duty-cycle distortion
All
±[1% of
CLKIN
period
+ 350]
±[1% of
CLKIN
period
+ 350]
ps
Phase Alignment(4)
CLKIN_CLKFB_PHASE Phase offset between the CLKIN and CLKFB inputs All ±150 ±150 ps
CLKOUT_PHASE_DLL Phase offset between DLL outputs CLK0 to CLK2X
(not CLK2X180)
±[1% of
CLKIN
period
+ 100]
±[1% of
CLKIN
period
+ 100]
ps
All others
±[1% of
CLKIN
period
+ 150]
±[1% of
CLKIN
period
+ 150]
ps
Lock Time
LOCK_DLL(3) When using the DLL alone: The
time from deassertion at the DCM’s
Reset input to the rising transition
at its LOCKED output. When the
DCM is locked, the CLKIN and
CLKFB signals are in phase
5 MHz < FCLKIN < 15 MHz All 55ms
FCLKIN > 15 MHz 600 600 µs
Delay Lines
DCM_DELAY_STEP(5) Finest delay resolution, averaged over all steps All 15 35 15 35 ps
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 36.
2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum jitter of
“±[1% of CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps.
According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250ps.
5. The typical delay step size is 23 ps.
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 49
Digital Frequency Synthesizer (DFS)
Table 38: Recommended Operating Conditions for the DFS
Symbol Description
Speed Grade
Units
-5 -4
Min Max Min Max
Input Frequency Ranges(2)
FCLKIN CLKIN_FREQ_FX Frequency for the CLKIN input 0.200 333(4) 0.200 333(4) MHz
Input Clock Jitter Tolerance(3)
CLKIN_CYC_JITT_FX_LF Cycle-to-cycle jitter at the CLKIN
input, based on CLKFX output
frequency
FCLKFX < 150 MHz ±300 ±300 ps
CLKIN_CYC_JITT_FX_HF FCLKFX > 150 MHz ±150 ±150 ps
CLKIN_PER_JITT_FX Period jitter at the CLKIN input ±1 ±1 ns
Notes:
1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 36.
3. CLKIN input jitter beyond these limits may cause the DCM to lose lock.
4. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM.
Table 39: Switching Characteristics for the DFS
Symbol Description Device
Speed Grade
Units
-5 -4
Min Max Min Max
Output Frequency Ranges
CLKOUT_FREQ_FX(2) Frequency for the CLKFX and CLKFX180 outputs All 5 350 5 320 MHz
Output Clock Jitter(3,4)
CLKOUT_PER_JITT_FX Period jitter at the CLKFX and CLKFX180
outputs.
All Typ Max Typ Max
CLKIN
20 MHz
Use the Spartan-3A Jitter Calculator:
www.xilinx.com/support/documentatio
n/data_sheets/s3a_jitter_calc.zip
ps
CLKIN
> 20 MHz
±[1% of
CLKFX
period
+ 100]
±[1% of
CLKFX
period
+ 200]
±[1% of
CLKFX
period
+ 100]
±[1% of
CLKFX
period
+ 200]
ps
Duty Cycle(5,6)
CLKOUT_DUTY_CYCLE_FX Duty cycle precision for the CLKFX and CLKFX180 outputs,
including the BUFGMUX and clock tree duty-cycle distortion
All
±[1% of
CLKFX
period
+ 350]
±[1% of
CLKFX
period
+ 350]
ps
Phase Alignment(6)
CLKOUT_PHASE_FX Phase offset between the DFS CLKFX output and the DLL
CLK0 output when both the DFS and DLL are used
All ±200 ±200 ps
CLKOUT_PHASE_FX180 Phase offset between the DFS CLKFX180 output and the DLL
CLK0 output when both the DFS and DLL are used
All
±[1% of
CLKFX
period
+ 200]
±[1% of
CLKFX
period
+ 200]
ps
DC and Switching Characteristics
50 www.xilinx.com DS529 (v2.1) December 18, 2018
Lock Time
LOCK_FX(2, 3) The time from deassertion at the DCM’s
Reset input to the rising transition at its
LOCKED output. The DFS asserts
LOCKED when the CLKFX and CLKFX180
signals are valid. If using both the DLL and
the DFS, use the longer locking time.
5 MHz < FCLKIN
< 15 MHz
All 55ms
FCLKIN >
15 MHz
450
450 µs
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 38.
2. DFS performance requires the additional logic automatically added by ISE 9.1i and later software revisions.
3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
4. Maximum output jitter is characterized within a reasonable noise environment (150 ps input period jitter, 40 SSOs and 25% CLB switching)
on an XC3S1400A FPGA. Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB
utilization, CLB switching activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the
system application.
5. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
6. Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a
maximum CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period
is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 200 ps] = ±300 ps.
Table 39: Switching Characteristics for the DFS(Continued)
Symbol Description Device
Speed Grade
Units
-5 -4
Min Max Min Max
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 51
Phase Shifter (PS)
Table 40: Recommended Operating Conditions for the PS in Variable Phase Mode
Symbol Description
Speed Grade
Units
-5 -4
Min Max Min Max
Operating Frequency Ranges
PSCLK_FREQ
(FPSCLK)
Frequency for the PSCLK input 1 167 1 167 MHz
Input Pulse Requirements
PSCLK_PULSE PSCLK pulse width as a percentage of the PSCLK period 40% 60% 40% 60% -
Table 41: Switching Characteristics for the PS in Variable Phase Mode
Symbol Description Phase Shift Amount Units
Phase Shifting Range
MAX_STEPS(2) Maximum allowed number of
DCM_DELAY_STEP steps for a
given CLKIN clock period, where
T = CLKIN clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE,
double the clock effective clock
period.
CLKIN < 60
MHz
±[INTEGER(10 (TCLKIN – 3 ns))] steps
CLKIN 60
MHz
±[INTEGER(15 (TCLKIN – 3 ns))]
FINE_SHIFT_RANGE_MIN Minimum guaranteed delay for variable phase shifting ±[MAX_STEPS
DCM_DELAY_STEP_MIN]
ns
FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting ±[MAX_STEPS
DCM_DELAY_STEP_MAX]
ns
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 40.
2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
3. The DCM_DELAY_STEP values are provided at the bottom of Table 37.
DC and Switching Characteristics
52 www.xilinx.com DS529 (v2.1) December 18, 2018
Miscellaneous DCM Timing
DNA Port Timing
Table 42: Miscellaneous DCM Timing
Symbol Description Min Max Units
DCM_RST_PW_MIN Minimum duration of a RST pulse width 3 CLKIN
cycles
DCM_RST_PW_MAX(2) Maximum duration of a RST pulse width N/A N/A seconds
N/A N/A seconds
DCM_CONFIG_LAG_TIME(3) Maximum duration from VCCINT applied to FPGA configuration
successfully completed (DONE pin goes High) and clocks
applied to DCM DLL
N/A N/A minutes
N/A N/A minutes
Notes:
1. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
2. This specification is equivalent to the Virtex®-4 DCM_RESET specification. This specification does not apply for Spartan-3A FPGAs.
3. This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3A FPGAs.
Table 43: DNA_PORT Interface Timing
Symbol Description Min Max Units
TDNASSU Setup time on SHIFT before the rising edge of CLK 1.0 –ns
TDNASH Hold time on SHIFT after the rising edge of CLK 0.5 –ns
TDNADSU Setup time on DIN before the rising edge of CLK 1.0 –ns
TDNADH Hold time on DIN after the rising edge of CLK 0.5 –ns
TDNARSU Setup time on READ before the rising edge of CLK 5.0 10,000 ns
TDNARH Hold time on READ after the rising edge of CLK 0 –ns
TDNADCKO Clock-to-output delay on DOUT after rising edge of CLK 0.5 1.5 ns
TDNACLKF CLK frequency 0 100 MHz
TDNACLKH CLK High time 1.0 ns
TDNACLKL CLK Low time 1.0 ns
Notes:
1. The minimum READ pulse width is 5 ns, the maximum READ pulse width is 10 µs.
2. The numbers in this table are based on the operating conditions set forth in Table 8.
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 53
Suspend Mode Timing
Figure 10: Suspend Mode Timing
Table 44: Suspend Mode Timing Parameters
Symbol Description Min Typ Max Units
Entering Suspend Mode
TSUSPENDHIGH_AWAKE Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter
(suspend_filter:No)
–7–ns
TSUSPENDFILTER Adjustment to SUSPEND pin rising edge parameters when glitch filter
enabled (suspend_filter:Yes)
+160 +300 +600 ns
TSUSPEND_GTS Rising edge of SUSPEND pin until FPGA output pins drive their defined
SUSPEND constraint behavior
–10–ns
TSUSPEND_GWE Rising edge of SUSPEND pin to write-protect lock on all writable clocked
elements
–<5–ns
TSUSPEND_DISABLE Rising edge of the SUSPEND pin to FPGA input pins and interconnect
disabled
– 340 –ns
Exiting Suspend Mode
TSUSPENDLOW_AWAKE Falling edge of the SUSPEND pin to rising edge of the AWAKE pin. Does not
include DCM lock time.
4 to 108 –µs
TSUSPEND_ENABLE Falling edge of the SUSPEND pin to FPGA input pins and interconnect
re-enabled
3.7 to 109 –µs
TAWAKE_GWE1 Rising edge of the AWAKE pin until write-protect lock released on all writable
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1.
–67–ns
TAWAKE_GWE512 Rising edge of the AWAKE pin until write-protect lock released on all writable
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512.
–14–µs
TAWAKE_GTS1 Rising edge of the AWAKE pin until outputs return to the behavior described
in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1.
–57–ns
TAWAKE_GTS512 Rising edge of the AWAKE pin until outputs return to the behavior described
in the FPGA application, using sw_clk:InternalClock and
sw_gts_cycle:512.
–14–µs
Notes:
1. These parameters based on characterization.
2. For information on using the Spartan-3A Suspend feature, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs.
DS610-3_08_061207
Blocked
tSUSPEND_DISABLE
tSUSPEND_GWE
tSUSPENDHIGH_AWAKE
tAWAKE_GWE
tAWAKE_GTS
tSUSPEND_GTS
SUSPEND Input
AWAKE Output
Flip-Flops, Block RAM,
Distributed RAM
FPGA Outputs
FPGA Inputs,
Interconnect
Write Protected
Defined by SUSPEND constraint
Entering Suspend Mode Exiting Suspend Mode
sw_gts_cycle
sw_gwe_cycle
tSUSPEND_ENABLE
tSUSPENDLOW_AWAKE
DC and Switching Characteristics
54 www.xilinx.com DS529 (v2.1) December 18, 2018
Configuration and JTAG Timing
General Configuration Power-On/Reconfigure Timing
Figure 11: Waveforms for Power-On and the Beginning of Configuration
Table 45: Power-On Timing and the Beginning of Configuration
Symbol Description Device
All Speed Grades
UnitsMin Max
TPOR(2) The time from the application of VCCINT, VCCAUX, and VCCO
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
All –18ms
TPROG The width of the low-going pulse on the PROG_B pin All 0.5 s
TPL(2) The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
XC3S50A –0.5ms
XC3S200A –0.5ms
XC3S400A –1ms
XC3S700A –2ms
XC3S1400A –2ms
TINIT Minimum Low pulse width on INIT_B output All 250 –ns
TICCK(3) The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
All 0.5 4 µs
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8. This means power must be applied to all VCCINT, VCCO,
and VCCAUX lines.
2. Power-on reset and the clearing of configuration memory occurs during this period.
3. This specification applies only to the Master Serial, SPI, and BPI modes.
4. For details on configuration, see UG332 Spartan-3 Generation Configuration User Guide.
VCCINT
(Supply)
(Supply)
(Supply)
VCCAUX
VCCO Bank 2
PROG_B
(Output)
(Open-Drain)
(Input)
INIT_B
CCLK
DS529-3_01_052708
1.2V
2.5V
TICCK
TPROG TPL
TPOR
1.0V
2.0V
2.0V 3.3V
or
2.5V
3.3V
or
Notes:
1. The VCCINT, VCCAUX, and VCCO supplies can be applied in any order.
2. The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
3. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 55
Configuration Clock (CCLK) Characteristics
Table 46: Master Mode CCLK Output Period by ConfigRate Opti0on Setting
Symbol Description
ConfigRate
Setting
Temperature
Range Minimum Maximum Units
TCCLK1
CCLK clock period by
ConfigRate setting 1
(power-on value)
Commercial 1,254 2,500 ns
Industrial 1,180 ns
TCCLK3 3Commercial 413 833 ns
Industrial 390 ns
TCCLK6 6 (default) Commercial 207 417 ns
Industrial 195 ns
TCCLK7 7Commercial 178 357 ns
Industrial 168 ns
TCCLK8 8Commercial 156 313 ns
Industrial 147 ns
TCCLK10 10 Commercial 123 250 ns
Industrial 116 ns
TCCLK12 12 Commercial 103 208 ns
Industrial 97 ns
TCCLK13 13 Commercial 93 192 ns
Industrial 88 ns
TCCLK17 17 Commercial 72 147 ns
Industrial 68 ns
TCCLK22 22 Commercial 54 114 ns
Industrial 51 ns
TCCLK25 25 Commercial 47 100 ns
Industrial 45 ns
TCCLK27 27 Commercial 44 93 ns
Industrial 42 ns
TCCLK33 33 Commercial 36 76 ns
Industrial 34 ns
TCCLK44 44 Commercial 26 57 ns
Industrial 25 ns
TCCLK50 50 Commercial 22 50 ns
Industrial 21 ns
TCCLK100 100 Commercial 11.2 25 ns
Industrial 10.6 ns
Notes:
1. Set the ConfigRate option value when generating a configuration bitstream.
DC and Switching Characteristics
56 www.xilinx.com DS529 (v2.1) December 18, 2018
Table 47: Master Mode CCLK Output Frequency by ConfigRate Option Setting
Symbol Description
ConfigRate
Setting
Temperature
Range Minimum Maximum Units
FCCLK1
Equivalent CCLK clock frequency
by ConfigRate setting 1
(power-on value)
Commercial 0.400 0.797 MHz
Industrial 0.847 MHz
FCCLK3 3Commercial 1.20 2.42 MHz
Industrial 2.57 MHz
FCCLK6 6
(default)
Commercial 2.40 4.83 MHz
Industrial 5.13 MHz
FCCLK7 7Commercial 2.80 5.61 MHz
Industrial 5.96 MHz
FCCLK8 8Commercial 3.20 6.41 MHz
Industrial 6.81 MHz
FCCLK10 10 Commercial 4.00 8.12 MHz
Industrial 8.63 MHz
FCCLK12 12 Commercial 4.80 9.70 MHz
Industrial 10.31 MHz
FCCLK13 13 Commercial 5.20 10.69 MHz
Industrial 11.37 MHz
FCCLK17 17 Commercial 6.80 13.74 MHz
Industrial 14.61 MHz
FCCLK22 22 Commercial 8.80 18.44 MHz
Industrial 19.61 MHz
FCCLK25 25 Commercial 10.00 20.90 MHz
Industrial 22.23 MHz
FCCLK27 27 Commercial 10.80 22.39 MHz
Industrial 23.81 MHz
FCCLK33 33 Commercial 13.20 27.48 MHz
Industrial 29.23 MHz
FCCLK44 44 Commercial 17.60 37.60 MHz
Industrial 40.00 MHz
FCCLK50 50 Commercial 20.00 44.80 MHz
Industrial 47.66 MHz
FCCLK100 100 Commercial 40.00 88.68 MHz
Industrial 94.34 MHz
Table 48: Master Mode CCLK Output Minimum Low and High Time
Symbol Description
ConfigRate Setting
Units1 3 6 7 8 10 12 13 17 22 25 27 33 44 50 100
TMCCL,
TMCCH
Master Mode
CCLK
Minimum Low
and High Time
Commercial 595 196 98.3 84.5 74.1 58.4 48.9 44.1 34.2 25.6 22.3 20.9 17.1 12.3 10.4 5.3 ns
Industrial 560 185 92.6 79.8 69.8 55.0 46.0 41.8 32.3 24.2 21.4 20.0 16.2 11.9 10.0 5.0 ns
Table 49: Slave Mode CCLK Input Low and High Time
Symbol Description Min Max Units
TSCCL,
TSCCH
CCLK Low and High time 5 ns
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 57
Master Serial and Slave Serial Mode Timing
Figure 12: Waveforms for Master Serial and Slave Serial Configuration
Table 50: Timing for the Master Serial and Slave Serial Configuration Modes
Symbol Description
Slave/
Master
All Speed Grades
UnitsMin Max
Clock-to-Output Times
TCCO The time from the falling transition on the CCLK pin to data appearing at the
DOUT pin
Both 1.5 10 ns
Setup Times
TDCC The time from the setup of data at the DIN pin to the rising transition at the
CCLK pin
Both 7 –ns
Hold Times
TCCD The time from the rising transition at the CCLK pin to the point when data is
last held at the DIN pin
Master 0 ns
Slave 1.0
Clock Timing
TCCH High pulse width at the CCLK input pin Master See Table 48
Slave See Table 49
TCCL Low pulse width at the CCLK input pin Master See Table 48
Slave See Table 49
FCCSER Frequency of the clock signal at the
CCLK input pin
No bitstream compression Slave 0 100 MHz
With bitstream compression 0 100 MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
DS312-3_05_103105
Bit 0 Bit 1 Bit n Bit n+1
Bit n-64 Bit n-63
1/FCCSER
TSCCL
TDCC
TCCD
TSCCH
TCCO
PROG_B
(Input)
DIN
(Input)
DOUT
(Output)
(Open-Drain)
INIT_B
(Input/Output)
CCLK
TMCCL TMCCH
DC and Switching Characteristics
58 www.xilinx.com DS529 (v2.1) December 18, 2018
Slave Parallel Mode Timing
Figure 13: Waveforms for Slave Parallel Configuration
Table 51: Timing for the Slave Parallel Configuration Mode
Symbol Description
All Speed Grades
UnitsMin Max
Setup Times
TSMDCC(2) The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin 7 –ns
TSMCSCC Setup time on the CSI_B pin before the rising transition at the CCLK pin 7 –ns
TSMCCW Setup time on the RDWR_B pin before the rising transition at the CCLK pin 15 –ns
Hold Times
TSMCCD The time from the rising transition at the CCLK pin to the point when data is last held at
the D0-D7 pins
1.0 –ns
TSMCCCS The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the CSO_B pin
0–ns
TSMWCC The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the RDWR_B pin
0–ns
Clock Timing
TCCH The High pulse width at the CCLK input pin 5 –ns
TCCL The Low pulse width at the CCLK input pin 5 –ns
FCCPAR Frequency of the clock signal
at the CCLK input pin
No bitstream compression 0 80 MHz
With bitstream compression 0 80 MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
2. Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.
DS529-3_02_051607
Byte 0 Byte 1 Byte n Byte n+1
TSMWCC
1/F
CCPAR
TSMCCCS
TSCCH
TSMCCW
T
SMCCD
TSMCSCC
T
SMDCC
PROG_B
(Input)
(Open-Drain)
INIT_B
(Input)
CSI_B
RDWR_B
(Input)
(Input)
CCLK
(Inputs)
D0 - D7
TMCCH TSCCL
TMCCL
Notes:
1. It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0 - D7 bus.
2. To pause configuration, pause CCLK instead of de-asserting CSI_B. See UG332 Chapter 7 section “Non-Continuous SelectMAP Data
Loading” for more details.
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 59
Serial Peripheral Interface (SPI) Configuration Timing
Figure 14: Waveforms for Serial Peripheral Interface (SPI) Configuration
Table 52: Timing for Serial Peripheral Interface (SPI) Configuration Mode
Symbol Description Minimum Maximum Units
TCCLK1 Initial CCLK clock period See Table 46
TCCLKnCCLK clock period after FPGA loads ConfigRate bitstream option setting See Table 46
TMINIT Setup time on VS[2:0] variant-select pins and M[2:0] mode pins before the
rising edge of INIT_B
50 –ns
TINITM Hold time on VS[2:0] variant-select pins and M[2:0] mode pins after the
rising edge of INIT_B
0–ns
TCCO MOSI output valid delay after CCLK falling clock edge See Table 50
TDCC Setup time on the DIN data input before CCLK rising clock edge See Table 50
TCCD Hold time on the DIN data input after CCLK rising clock edge See Table 50
T
DH
T
DSU
Command
(msb)
T
V
T
CSS
<1:1:1>
INIT_B
M[2:0]
T
MINIT
T
INITM
DIN
CCLK
(Input)
T
CCLKn
T
CCLK1
VS[2:0]
(Input)
New ConfigRate active
Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B
goes High. After this point, input values do not matter until DONE goes High, at which
point these pins become user-I/O pins.
<0:0:1>
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High. External pull-up resistor required on CSO_B.
T
CCLK1
T
MCCLn
T
MCCHn
(Input)
Data Data Data Data
CSO_B
MOSI
T
CCO
T
MCCL1
T
MCCH1
T
DCC
T
CCD
(Input)
PROG_B
PUDC_B
(Input)
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
DS529-3_06_102506
(Open-Drain)
Shaded values indicate specifications on attached SPI Flash PROM.
Command
(msb-1)
DC and Switching Characteristics
60 www.xilinx.com DS529 (v2.1) December 18, 2018
Table 53: Configuration Timing Requirements for Attached SPI Serial Flash
Symbol Description Requirement Units
TCCS SPI serial Flash PROM chip-select time ns
TDSU SPI serial Flash PROM data input setup time ns
TDH SPI serial Flash PROM data input hold time ns
TVSPI serial Flash PROM data clock-to-output time ns
fC or fRMaximum SPI serial Flash PROM clock frequency (also depends on
specific read command used)
MHz
Notes:
1. These requirements are for successful FPGA configuration in SPI mode, where the FPGA generates the CCLK signal. The
post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.
2. Subtract additional printed circuit board routing delay as required by the application.
TCCS TMCCL1TCCO
TDSU TMCCL1TCCO
TDH TMCCH1
TVTMCCLn TDCC
fC
1
TCCLKn min()
---------------------------------
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 61
Byte Peripheral Interface (BPI) Configuration Timing
Figure 15: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration
Table 54: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode
Symbol Description Minimum Maximum Units
TCCLK1 Initial CCLK clock period See Table 46
TCCLKnCCLK clock period after FPGA loads ConfigRate setting See Table 46
TMINIT Setup time on M[2:0] mode pins before the rising edge of INIT_B 50 –ns
TINITM Hold time on M[2:0] mode pins after the rising edge of INIT_B 0 –ns
TINITADDR Minimum period of initial A[25:0] address cycle; LDC[2:0] and HDC are asserted
and valid
55T
CCLK1
cycles
TCCO Address A[25:0] outputs valid after CCLK falling edge See Table 50
TDCC Setup time on D[7:0] data inputs before CCLK rising edge See TSMDCC in Table 51
TCCD Hold time on D[7:0] data inputs after CCLK rising edge 0 –ns
(Input) PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
Data DataData
AddressAddress
Data
Address
Byte 0
000_0000
INIT_B
<0:1:0>
M[2:0]
T
MINIT
T
INITM
LDC[2:0]
HDC
CSO_B
Byte 1
000_0001
CCLK
A[25:0]
D[7:0]
T
DCC
T
CCD
T
AVQV
TCCLK1
(Input)
TINITADDR
T
CCLKn
T
CCLK1
T
CCO
PUDC_B
New ConfigRate active
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High.
Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
(Input)
PROG_B
(Input)
DS529-3_05_021009
Open-Drain)
Shaded values indicate specifications on attached parallel NOR Flash PROM.
DC and Switching Characteristics
62 www.xilinx.com DS529 (v2.1) December 18, 2018
Table 55: Configuration Timing Requirements for Attached Parallel NOR BPI Flash
Symbol Description Requirement Units
TCE
(tELQV)
Parallel NOR Flash PROM chip-select time ns
TOE
(tGLQV)
Parallel NOR Flash PROM output-enable time ns
TACC
(tAVQV)
Parallel NOR Flash PROM read access time ns
TBYTE
(tFLQV,
tFHQV)
For x8/x16 PROMs only: BYTE# to output valid time(3) ns
Notes:
1. These requirements are for successful FPGA configuration in BPI mode, where the FPGA generates the CCLK signal. The
post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.
2. Subtract additional printed circuit board routing delay as required by the application.
3. The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor
value also depends on whether the FPGA’s PUDC_B pin is High or Low.
TCE TINITADDR
TOE TINITADDR
TACC 50%TCCLKn min()
TCCO TDCC PCB
TBYTE TINITADDR
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 www.xilinx.com 63
IEEE 1149.1/1532 JTAG Test Access Port Timing
Figure 16: JTAG Waveforms
Table 56: Timing for the JTAG Test Access Port
Symbol Description
All Speed
Grades
UnitsMin Max
Clock-to-Output Times
TTCKTDO The time from the falling transition on the TCK pin to data appearing at the TDO pin 1.0 11.0 ns
Setup Times
TTDITCK The time from the setup of data at the
TDI pin to the rising transition at the
TCK pin
All devices and functions except those shown below 7.0 –ns
Boundary scan commands (INTEST, EXTEST,
SAMPLE) on XC3S700A and XC3S1400A FPGAs
11.0
TTMSTCK The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin 7.0 –ns
Hold Times
TTCKTDI The time from the rising transition at
the TCK pin to the point when data is
last held at the TDI pin
All functions except those shown below 0 –ns
Configuration commands (CFG_IN, ISC_PROGRAM) 2.0
TTCKTMS The time from the rising transition at the TCK pin to the point when a logic level is last held at the
TMS pin
0–ns
Clock Timing
TCCH The High pulse width at the TCK pin All functions except ISC_DNA command 5 –ns
TCCL The Low pulse width at the TCK pin 5 –ns
TCCHDNA The High pulse width at the TCK pin During ISC_DNA command 10 10,000 ns
TCCLDNA The Low pulse width at the TCK pin 10 10,000 ns
FTCK Frequency of the TCK signal All operations on XC3S50A, XC3S200A, and
XC3S400A FPGAs and for BYPASS or HIGHZ
instructions on all FPGAs
033MHz
All operations on XC3S700A and XC3S1400A FPGAs,
except for BYPASS or HIGHZ instructions
20
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
2. For details on JTAG see Chapter 9 “JTAG Configuration Mode and Boundary-Scan” in UG332 Spartan-3 Generation Configuration User
Guide.
TCK
T
TMSTCK
TMS
TDI
TDO
(Input)
(Input)
(Input)
(Output)
T
TCKTMS
T
TCKTDI
T
TCKTDO
T
TDITCK
DS099_06_020709
T
CCH
T
CCL
1/F
TCK
DC and Switching Characteristics
64 www.xilinx.com DS529 (v2.1) December 18, 2018
Revision History
The following table shows the revision history for this document.
Date Version Revision
12/05/06 1.0 Initial release.
02/02/07 1.1 Promoted to Preliminary status. Moved Table 15 to under "DC Electrical Characteristics" section. Updated all
timing specifications for the v1.32 speed files. Added recommended Simultaneous Switching Output (SSO)
limits in Table 29. Set a 10 µs maximum pulse width for the DNA_PORT READ signal and the JTAG clock
input during the ISC_DNA command, affecting both Table 43 and Table 56. Described "External Termination
Requirements for Differential I/O." Added separate DIN hold time for Slave mode in Table 50. Corrected
wording in Table 52 and Table 54; no specifications affected.
03/16/07 1.2 Updated all AC timing specifications to the v1.34 speeds file. Promoted the XC3S700A and XC3S1400A
FPGAs offered in the -4 speed grade to Production status, as shown in Table 16. Added Note 2 to Table 39
regarding the extra logic (one LUT) automatically added by ISE 9.1i and later software revisions for any DCM
application that leverages the Digital Frequency Synthesizer (DFS). Separated some JTAG specifications by
array size or function, as shown in Table 56. Updated quiescent current limits in Table 10.
04/23/07 1.3 Updated all AC timing specifications to the v1.35 speeds file. Promoted all devices except the XC3S400A to
Production status, as shown in Table 16.
05/08/07 1.4 Updated XC3S400A to Production and v1.36 speeds file. Added banking rules and other explanatory
footnotes to Table 12 and Table 13. Corrected DIFF_SSTL3_II VOL Max in Table 14. Improved XC3S400A
Pin-to-Pin Clock-to-Output times in Table 18. Updated XC3S400A Pin-to-Pin Setup Times in Table 19.
Updated TIOICKPD for -5 in Table 20. Added SSO numbers to Table 28 and Table 29. Removed invalid
Embedded Multiplier Hold Times in Table 34. Improved CLKOUT_FREQ_CLK90 in Table 37. Improved
TTDITCK and FTCK performance for XC3S400A in Table 56.
07/10/07 1.5 Added DIFF_HSTL_I and DIFF_HSTL_III to Table 13, Table 14, Table 27, and Table 29. Updated TMDS DC
characteristics in Table 14. Updated for speed file v1.37 in ISE 9.2.01i as shown in Table 17. Updated
pin-to-pin setup and hold times in Table 19. Updated TMDS output adjustment in Table 26. Updated I/O Test
Method values in Table 27. Added BLVDS SSO numbers inTable 29. For Multiplier block, updated setup times
and added hold times to Table 34. Updated block RAM clock width in Table 35. Updated
CLKOUT_PER_JITT_2X and CLKOUT_PER_JITT_DV2 in Table 37. Added CCLK specifications for
Commercial in Table 46 through Table 48.
04/15/08 1.6 Added VIN to Recommended Operating Conditions in Table 8 and added reference to XAPP459, “Eliminating
I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins.” Reduced typical
ICCINTQ and ICCAUXQ quiescent current values by 12%-58% in Table 10. Increased VIL max to 0.4V for
LVCMOS12/15/18 and improved VIH min to 0.7V for LVCMOS12 in Table 11. Changed VOL max to 0.4V and
VOH min to VCCO-0.4V for LVCMOS15/18 in Table 12. Noted latest speed file v1.39 in ISE 10.1 software in
Table 16. Added new packages to SSO limits in Table 28 and Table 29. Improved SSTL18_II SSO limit for
FG packages in Table 29. Improved FBUFG for -4 to 334 MHz in Table 33. Added references to 375 MHz
performance via SCD 4103 in Table 33,Table 38, Table 39, and Table 40. Restored Units column to Table 44.
Updated CCLK output maximum period in Table 46 to match minimum frequency in Table 47. Corrected BPI
active clock edge in Figure 15 and Table 54.
05/28/08 1.7 Improved VCCAUXT and VCCO2T POR minimum in Table 5 and updated VCCO POR levels in Figure 11.
Clarified recommended VIN in Table 8. Added reference to VCCAUX in "Simultaneously Switching Output
Guidelines". Added reference to Sample Window in Table 21. Removed DNA_RETENTION limit of 10 years
in Table 15 since number of Read cycles is the only unique limit. Added references to UG332.
03/06/09 1.8 Changed typical quiescent current temperature from ambient to junction. Updated BPI configuration
waveforms in Figure 15 and updated Table 55. Updated selected I/O standard DC characteristics. Added
TIOPI and TIOPID in Table 22.
Removed references to SCD 4103.
08/19/10 2.0 Added IIK to Table 4. Updated VIN in Table 8 and footnoted IL in Table 9 to note potential leakage between
pins of a differential pair. Clarified LVPECL notes to Table 13. Corrected symbols for TSUSPEND_GTS and
TSUSPEND_GWE in Table 44.
12/18/18 2.1 Updated for Lead-Frame Plating Composition Change For Legacy Eutectic Products (XCN18024).
DS529 (v2.1) December 18, 2018 www.xilinx.com 65
© Copyright 2006–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.
Introduction
This section describes how the various pins on a
Spartan®-3A FPGA connect within the supported
component packages, and provides device-specific thermal
characteristics. For general information on the pin functions
and the package characteristics, see the Packaging section
of UG331: Spartan-3 Generation FPGA User Guide.
UG331: Spartan-3 Generation FPGA User Guide
www.xilinx.com/support/documentation
/user_guides/ug331.pdf
Spartan-3A FPGAs are available in both standard and
Pb-free, RoHS versions of each package, with the Pb-free
version adding a “G” to the middle of the package code.
Except for the thermal characteristics, all information for the
standard package applies equally to the Pb-free package.
Pin Types
Most pins on a Spartan-3A FPGA are general-purpose,
user-defined I/O pins. There are, however, up to 12 different
functional types of pins on Spartan-3A FPGA packages, as
outlined in Table 57. In the package footprint drawings that
follow, the individual pins are color-coded according to pin
type as in the table.
132 Spartan-3A FPGA Family:
Pinout Descriptions
DS529 (v2.1) December 18, 2018 0Product Specification
Table 57: Types of Pins on Spartan-3A FPGAs
Type / Color
Code Description Pin Name(s) in Type
I/O Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form
differential I/Os.
IO_#
IO_Lxxy_#
INPUT Unrestricted, general-purpose input-only pin. This pin does not have an output structure,
differential termination resistor, or PCI clamp diode.
IP_#
IP_Lxxy_#
DUAL
Dual-purpose pin used in some configuration modes during the configuration process and
then usually available as a user I/O after configuration. If the pin is not used during
configuration, this pin behaves as an I/O-type pin. See UG332: Spartan-3 Generation
Configuration User Guide for additional information on these signals.
M[2:0]
PUDC_B
CCLK
MOSI/CSI_B
D[7:1]
D0/DIN
DOUT
CSO_B
RDWR_B
INIT_B
A[25:0]
VS[2:0]
LDC[2:0]
HDC
VREF
Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along with all other
VREF pins in the same bank, provides a reference voltage input for certain I/O standards.
If used for a reference voltage within a bank, all VREF pins within the bank must be
connected.
IP/VREF_#
IP_Lxxy_#/VREF_#
IO/VREF_#
IO_Lxxy_#/VREF_#
CLK
Either a user-I/O pin or an input to a specific clock buffer driver. Most packages have 16
global clock inputs that optionally clock the entire device. The exceptions are the TQ144
and the XC3S50A in the FT256 package). The RHCLK inputs optionally clock the right half
of the device. The LHCLK inputs optionally clock the left half of the device. See the Using
Global Clock Resources chapter in UG331: Spartan-3 Generation FPGA User Guide for
additional information on these signals.
IO_Lxxy_#/GCLK[15:0],
IO_Lxxy_#/LHCLK[7:0],
IO_Lxxy_#/RHCLK[7:0]
CONFIG
Dedicated configuration pin, two per device. Not available as a user-I/O pin. Every
package has two dedicated configuration pins. These pins are powered by VCCAUX. See
the UG332: Spartan-3 Generation Configuration User Guide for additional information on
the DONE and PROG_B signals.
DONE, PROG_B
Pinout Descriptions
66 www.xilinx.com DS529 (v2.1) December 18, 2018
Package Pins by Type
Each package has three separate voltage supply inputs—
VCCINT, VCCAUX, and VCCO—and a common ground
return, GND. The numbers of pins dedicated to these
functions vary by package, as shown in Table 58.
A majority of package pins are user-defined I/O or input
pins. However, the numbers and characteristics of these I/O
depend on the device type and the package in which it is
available, as shown in Table 59. The table shows the
maximum number of single-ended I/O pins available,
assuming that all I/O-, INPUT-, DUAL-, VREF-, and
CLK-type pins are used as general-purpose I/O. AWAKE is
counted here as a dual-purpose I/O pin. Likewise, the table
shows the maximum number of differential pin-pairs
available on the package. Finally, the table shows how the
total maximum user-I/Os are distributed by pin type,
including the number of unconnected—N.C.—pins on the
device.
Not all I/O standards are supported on all I/O banks. The left
and right banks (I/O banks 1 and 3) support higher output
drive current than the top and bottom banks (I/O banks 0
and 2). Similarly, true differential output standards, such as
LVDS, RSDS, PPDS, miniLVDS, and TMDS, are only
supported in the top or bottom banks (I/O banks 0 and 2).
Inputs are unrestricted. For more details, see the chapter
Using I/O Resources” in UG331.
PWR
MGMT
Control and status pins for the power-saving Suspend mode. SUSPEND is a dedicated
pin and is powered by VCCAUX. AWAKE is a dual-purpose pin. Unless Suspend mode is
enabled in the application, AWAKE is available as a user-I/O pin.
SUSPEND, AWAKE
JTAG Dedicated JTAG pin - 4 per device. Not available as a user-I/O pin. Every package has
four dedicated JTAG pins. These pins are powered by VCCAUX.
TDI, TMS, TCK, TDO
GND Dedicated ground pin. The number of GND pins depends on the package used. All must
be connected.
GND
VCCAUX
Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on the
package used. All must be connected. VCCAUX can be either 2.5V or 3.3V. Set on board
and using CONFIG VCCAUX constraint.
VCCAUX
VCCINT Dedicated internal core logic power supply pin. The number of VCCINT pins depends on
the package used. All must be connected to +1.2V.
VCCINT
VCCO
Along with all the other VCCO pins in the same bank, this pin supplies power to the output
buffers within the I/O bank and sets the input threshold voltage for some I/O standards. All
must be connected.
VCCO_#
N.C. This package pin is not connected in this specific device/package combination but may be
connected in larger devices in the same package.
N.C.
Notes:
1. # = I/O bank number, an integer between 0 and 3.
Table 57: Types of Pins on Spartan-3A FPGAs(Continued)
Type / Color
Code Description Pin Name(s) in Type
Table 58: Power and Ground Supply Pins by Package
Package VCCINT VCCAUX VCCO GND
VQ100 4 3 6 13
TQ144 4 4 8 13
FT256 (50A/200A/400A) 6 4 16 28
FT256 (700A/1400A) 15 10 13 50
FG320 6 8 16 32
FG400 9 8 22 43
FG484 15 10 24 53
FG676 23 14 36 77
Pinout Descriptions
DS529 (v2.1) December 18, 2018 www.xilinx.com 67
.
Electronic versions of the package pinout tables and foot-
prints are available for download from the Xilinx website.
Using a spreadsheet program, the data can be sorted and
reformatted according to any specific needs. Similarly, the
ASCII-text file is easily parsed by most scripting programs.
http://www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip
Table 59: Maximum User I/O by Package
Device Package
Maximum
User I/Os
and
Input-Only
Maximum
Input-
Only
Maximum
Differential
Pairs
All Possible I/Os by Type
I/O INPUT DUAL VREF CLK N.C.
XC3S50A VQ100 68 660 17 220 623 0
XC3S200A 68 660 17 220 623 0
XC3S50A TQ144 108 750 42 226 830 0
XC3S50A
FT256
144 32 64 53 20 26 15 30 51
XC3S200A 195 35 90 69 21 52 21 32 0
XC3S400A 195 35 90 69 21 52 21 32 0
XC3S700A 161 13 60 59 252 18 30 0
XC3S1400A 161 13 60 59 252 18 30 0
XC3S200A FG320 248 56 112 101 40 52 23 32 3
XC3S400A 251 59 112 101 42 52 24 32 0
XC3S400A FG400 311 63 142 155 46 52 26 32 0
XC3S700A 311 63 142 155 46 52 26 32 0
XC3S700A FG484 372 84 165 194 61 52 33 32 3
XC3S1400A 375 87 165 195 62 52 34 32 0
XC3S1400A FG676 502 94 227 313 67 52 38 32 17
Notes:
1. Some VREFs are on INPUT pins. See pinout tables for details.
Pinout Descriptions
68 www.xilinx.com DS529 (v2.1) December 18, 2018
Package Overview
Table 60 shows the six low-cost, space-saving production package styles for the Spartan-3A family.
Each package style is available in an environmentally
friendly lead-free (Pb-free) option. The Pb-free packages
include an extra ‘G’ in the package style name. For
example, the standard “CS484” package becomes
“CSG484” when ordered as the Pb-free option. The
mechanical dimensions of the standard and Pb-free
packages are similar. Package drawings and package
material declaration data sheets (MDDS) are available on
www.xilinx.com.
For additional package information, see UG112: Device
Package User Guide.
Mechanical Drawings
Material Declaration Data Sheets (MDDS) are also available
on the www.xilinx.com for each package.
Table 60: Spartan-3A Family Package Options(1)
Package Leads Type Maximum
I/O
Lead Pitch
(mm)
Body Area
(mm)
Height
(mm)
VQ100 / VQG100 100 Very Thin Quad Flat Pack (VQFP) 68 0.5 14 x 14 1.20
TQ144 / TQG144 144 Thin Quad Flat Pack (TQFP) 108 0.5 20 x 20 1.60
FT256 / FTG256 256 Fine-pitch Thin Ball Grid Array (FBGA) 195 1.0 17 x 17 1.55
FG320 / FGG320 320 Fine-pitch Ball Grid Array (FBGA) 251 1.0 19 x 19 2.00
FG400 / FGG400 400 Fine-pitch Ball Grid Array (FBGA) 311 1.0 21 x 21 2.43
FG484 / FGG484 484 Fine-pitch Ball Grid Array (FBGA) 375 1.0 23 x 23 2.60
FG676 / FGG676 676 Fine-pitch Ball Grid Array (FBGA) 502 1.0 27 x 27 2.60
Notes:
1. See the package material declaration data sheet for package mass.
Pinout Descriptions
DS529 (v2.1) December 18, 2018 www.xilinx.com 69
Package Thermal Characteristics
The power dissipated by an FPGA application has
implications on package selection and system design. The
power consumed by a Spartan-3A FPGA is reported using
either the XPower Power Estimator or the XPower Analyzer
calculator integrated in the Xilinx® ISE® development
software. Table 61 provides the thermal characteristics for
the various Spartan-3A FPGA package offerings. This
information is also available using the Thermal Query tool
on xilinx.com (www.xilinx.com/cgi-bin/thermal/thermal.pl).
The junction-to-case thermal resistance (θJC) indicates the
difference between the temperature measured on the
package body (case) and the die junction temperature per
watt of power consumption. The junction-to-board (θJB)
value similarly reports the difference between the board and
junction temperature. The junction-to-ambient (θJA) value
reports the temperature difference between the ambient
environment and the junction temperature. The θJA value is
reported at different air velocities, measured in linear feet
per minute (LFM). The “Still Air (0 LFM)” column shows the
θJA value in a system without a fan. The thermal resistance
drops with increasing air flow.
Table 61: Spartan-3A Package Thermal Characteristics
Package Device
Junction-to-Case
(θJC)
Junction-to-
Board (θJB)
Junction-to-Ambient (θJA)
at Different Air Flows
Units
Still Air
(0 LFM) 250 LFM 500 LFM 750 LFM
VQ100
VQG100
XC3S50A 12.9 30.1 48.5 40.4 37.6 36.6 °C/Watt
XC3S200A 10.9 25.7 42.9 35.7 33.2 32.4 °C/Watt
TQ144
TQG144 XC3S50A 16.5 32.0 42.4 36.3 35.8 34.9 °C/Watt
FT256
FTG256
XC3S50A 16.0 33.5 42.3 35.6 35.5 34.5 °C/Watt
XC3S200A 10.3 23.8 32.7 26.6 26.1 25.2 °C/Watt
XC3S400A 8.4 19.3 29.9 24.9 23.0 22.3 °C/Watt
XC3S700A 7.8 18.6 28.1 22.3 21.2 20.7 °C/Watt
XC3S1400A 5.4 14.1 24.2 18.7 17.5 17.0 °C/Watt
FG320
FGG320
XC3S200A 11.7 18.5 27.8 22.3 21.1 20.3 °C/Watt
XC3S400A 9.9 15.4 25.2 19.8 18.6 17.8 °C/Watt
FG400
FGG400
XC3S400A 9.8 15.5 25.6 19.2 18.0 17.3 °C/Watt
XC3S700A 8.2 13.0 23.1 17.9 16.7 16.0 °C/Watt
FG484
FGG484
XC3S700A 7.9 12.8 22.3 17.4 16.2 15.5 °C/Watt
XC3S1400A 6.0 9.9 19.5 14.7 13.5 12.8 °C/Watt
FG676
FGG676 XC3S1400A 5.8 9.4 17.8 13.5 12.4 11.8 °C/Watt
Pinout Descriptions
70 www.xilinx.com DS529 (v2.1) December 18, 2018
VQ100: 100-lead Very Thin Quad Flat Package
The XC3S50A and XC3S200 are available in the 100-lead
very thin quad flat package, VQ100.
Table 62 lists all the package pins. They are sorted by bank
number and then by pin name. Pins that form a differential
I/O pair appear together in the table. The table also shows
the pin number for each pin and the pin type, as defined
earlier.
The VQ100 does not support Suspend mode (SUSPEND
and AWAKE are not connected), the address output pins for
the Byte-wide Peripheral Interface (BPI) configuration mode,
or daisy chain configuration (DOUT is not connected).
Table 62 also indicates that some differential I/O pairs have
different assignments between the XC3S50A and the
XC3S200A, highlighted in light blue. See "Footprint
Migration Differences," page 72 for additional information.
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip.
Pinout Table
Table 62: Spartan-3A VQ100 Pinout
Bank Pin Name Pin Type
0 IO_0/GCLK11 P90 CLK
0 IO_L01N_0 P78 IO
0 IO_L01P_0/VREF_0 P77 VREF
0 IO_L02N_0/GCLK5 P84 CLK
0 IO_L02P_0/GCLK4 P83 CLK
0 IO_L03N_0/GCLK7 P86 CLK
0 IO_L03P_0/GCLK6 P85 CLK
0 IO_L04N_0/GCLK9 P89 CLK
0 IO_L04P_0/GCLK8 P88 CLK
0 IO_L05N_0