XC2C32A Datasheet

Xilinx Inc.

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Datasheet

DS310 (v2.1) November 6, 2008 www.xilinx.com 1
Product Specification
© 2004–2008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
Optimized for 1.8V systems
- As fast as 3.8 ns pin-to-pin logic delays
- As low as 12 μA quiescent current
Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation: 1.5V through 3.3V
Available in multiple package options
- 32-land QFN with 21 user I/Os
- 44-pin VQFP with 33 user I/Os
- 56-ball CP BGA with 33 user I/Os
- Pb-free available for all packages
Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Two separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
- Optional DualEDGE triggered registers
- Global signal options with macrocell control
· Multiple global clocks with phase selection per
macrocell
· Multiple global output enables
· Global set/reset
- Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
- Advanced design security
- Open-drain output option for Wired-OR and LED
drive
- Optional configurable grounds on unused I/Os
- Optional bus-hold, 3-state, or weak pullup on
selected I/O pins
- Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
- PLA architecture
· Superior pinout retention
· 100% product term routability across function
block
- Hot pluggable
Refer to the CoolRunner™-II family data sheet for the archi-
tecture description.
Description
The CoolRunner™-II 32-macrocell device is designed for
both high performance and low power applications. This
lends power savings to high-end communication equipment
and high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reli-
ability is improved.
This device consists of two Function Blocks interconnected
by a low power Advanced Interconnect Matrix (AIM). The
AIM feeds 40 true and complement inputs to each Function
Block. The Function Blocks consist of a 40 by 56 P-term
PLA and 16 macrocells which contain numerous configura-
tion bits that allow for combinational or registered modes of
operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain, and programmable grounds. A Schmitt trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers can be
configured as "direct input" registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as a
synchronous clock source. Macrocell registers can be indi-
vidually configured to power up to the zero or one state. A
global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset, and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
The CoolRunner-II 32-macrocell CPLD is I/O compatible
with standard LVTTL and LVCMOS18, LVCMOS25, and
LVCMOS33 (see Ta bl e 1 ). This device is also 1.5V I/O com-
patible with the use of Schmitt-trigger inputs.
Another feature that eases voltage translation is I/O bank-
ing. Two I/O banks are available on the CoolRunner-II 32A
macrocell device that permit easy interfacing to 3.3V, 2.5V,
1.8V, and 1.5V devices.
0
XC2C32A CoolRunner-II CPLD
DS310 (v2.1) November 6, 2008 00Product Specification
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XC2C32A CoolRunner-II CPLD
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Product Specification
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RealDigital Design Technology
Xilinx® CoolRunner-II CPLDs are fabricated on a
0.18 micron process technology which is derived from lead-
ing edge FPGA product development. CoolRunner-II
CPLDs employ RealDigital, a design technique that makes
use of CMOS technology in both the fabrication and design
methodology. RealDigital design technology employs a cas-
cade of CMOS gates to implement sum of products instead
of traditional sense amplifier methodology. Due to this tech-
nology, Xilinx CoolRunner-II CPLDs achieve both high per-
formance and low power operation.
Supported I/O Standards
The CoolRunner-II CPLD 32 macrocell features both
LVCMOS and LVTTL I/O implementations. See Tab le 1 for
I/O standard voltages. The LVTTL I/O standard is a general
purpose EIA/JEDEC standard for 3.3V applications that use
an LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, and 1.8V applica-
tions. CoolRunner-II CPLDs are also 1.5V I/O compatible
with the use of Schmitt-trigger inputs.
Tab l e 1 : I/O Standards for XC2C32A
IOSTANDARD
Attribute
Output
VCCIO
Input
VCCIO
Input
VREF
Board
Termination
Voltage VT
LVTTL 3.3 3.3 N/A N/A
LVCMOS33 3.3 3.3 N/A N/A
LVCMOS25 2.5 2.5 N/A N/A
LVCMOS18 1.8 1.8 N/A N/A
LVCM OS 15 (1) 1.5 1.5 N/A N/A
1. LVCMOS15 requires Schmitt-trigger inputs.
Figure 1: ICC vs. Frequency
Tab le 2 : ICC vs. Frequency (LVCMOS 1.8V TA = 25°C)(1)
Frequency (MHz)
0 25 50 75 100 150 175 200 225 250 300
Typical ICC (mA) 0.016 0.87 1.75 2.61 3.44 5.16 5.99 6.81 7.63 8.36 9.93
Notes:
1. 16-bit up/down, resettable binary counter (one counter per function block).
Frequency (MHz)
DS091_01_030105
ICC (mA)
0
0
5
10
15
20
30025020015010050
XC2C32A CoolRunner-II CPLD
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Product Specification
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Recommended Operating Conditions
DC Electrical Characteristics Over Recommended Operating Conditions
Absolute Maximum Ratings
Symbol Description Value Units
VCC Supply voltage relative to ground –0.5 to 2.0 V
VCCIO Supply voltage for output drivers –0.5 to 4.0 V
VJTAG(2) JTAG input voltage limits –0.5 to 4.0 V
VCCAUX JTAG input supply voltage –0.5 to 4.0 V
VIN(1) Input voltage relative to ground –0.5 to 4.0 V
VTS(1) Voltage applied to 3-state output –0.5 to 4.0 V
TSTG(3) Storage Temperature (ambient) –65 to +150 °C
TJJunction Temperature +150 °C
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,
the device pins might undershoot to –2.0V or overshoot to +4.5V, provided this overshoot or undershoot lasts less than 10 ns and
with the forcing current being limited to 200 mA.
2. Valid over commercial temperature range.
3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb free
packages, see XAPP427.
Symbol Parameter Min Max Units
VCC Supply voltage for internal logic
and input buffers
Commercial TA = 0°C to +70°C 1.7 1.9 V
Industrial TA = –40°C to +85°C 1.7 1.9 V
VCCIO Supply voltage for output drivers @ 3.3V operation 3.0 3.6 V
Supply voltage for output drivers @ 2.5V operation 2.3 2.7 V
Supply voltage for output drivers @ 1.8V operation 1.7 1.9 V
Supply voltage for output drivers @ 1.5V operation 1.4 1.6 V
VCCAUX JTAG programming pins 1.7 3.6 V
Symbol Parameter Test Conditions Typical Max. Units
ICCSB Standby current Commercial VCC = 1.9V, VCCIO = 3.6V 22 90 μA
ICCSB Standby current Industrial VCC = 1.9V, VCCIO = 3.6V 38 150 μA
ICC(1) Dynamic current f = 1 MHz - 0.25 mA
f = 50 MHz - 2.5 mA
CJTAG JTAG input capacitance f = 1 MHz - 10 pF
CCLK Global clock input capacitance f = 1 MHz - 12 pF
CIO I/O capacitance f = 1 MHz - 10 pF
IIL(2) Input leakage current VIN = 0V or VCCIO to 3.9V - +/-1 μA
IIH(2) I/O High-Z leakage VIN = 0V or VCCIO to 3.9V - +/-1 μA
Notes:
1. 16-bit up/down resettable binary counter (one per Function Block) tested at VCC = VCCIO = 1.9V.
2. See Quality and Reliability section of the CoolRunner-II family data sheet.
XC2C32A CoolRunner-II CPLD
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Product Specification
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LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications
LVCMOS 2.5V DC Voltage Specifications
LVCMOS 1.8V DC Voltage Specifications
LVCMOS 1.5V DC Voltage Specifications
Symbol Parameter Test Conditions Min. Max. Units
VCCIO Input source voltage 3.0 3.6 V
VIH High level input voltage 2 3.9 V
VIL Low level input voltage –0.3 0.8 V
VOH High level output voltage IOH = –8 mA, VCCIO = 3V VCCIO – 0.4V - V
IOH = –0.1 mA, VCCIO = 3V VCCIO – 0.2V - V
VOL Low level output voltage IOL = 8 mA, VCCIO = 3V - 0.4 V
IOL = 0.1 mA, VCCIO = 3V - 0.2 V
Symbol Parameter Test Conditions Min. Max. Units
VCCIO Input source voltage 2.3 2.7 V
VIH High level input voltage 1.7 VCCIO + 0.3(1) V
VIL Low level input voltage –0.3 0.7 V
VOH High level output voltage IOH = –8 mA, VCCIO = 2.3V VCCIO – 0.4V - V
IOH = –0.1 mA, VCCIO = 2.3V VCCIO – 0.2V - V
VOL Low level output voltage IOL = 8 mA, VCCIO = 2.3V - 0.4 V
IOL = 0.1mA, VCCIO = 2.3V - 0.2 V
1. The VIH Max value represents the JEDEC specification for LVCMOS25. The CoolRunner-II CPLD input buffer can tolerate up to 3.9V
without physical damage.
Symbol Parameter(1) Test Conditions Min. Max. Units
VCCIO Input source voltage 1.7 1.9 V
VIH High level input voltage 0.65 x VCCIO VCCIO + 0.3(1) V
VIL Low level input voltage –0.3 0.35 x VCCIO V
VOH High level output voltage IOH = –8 mA, VCCIO = 1.7V VCCIO – 0.45 - V
IOH = –0.1 mA, VCCIO = 1.7V VCCIO – 0.2 - V
VOL Low level output voltage IOL = 8 mA, VCCIO = 1.7V - 0.45 V
IOL = 0.1 mA, VCCIO = 1.7V - 0.2 V
1. The VIH Max value represents the JEDEC specification for LVCMOS18. The CoolRunner-II CPLD input buffer can tolerate up to 3.9V
without physical damage.
Symbol Parameter Test Conditions Min. Max. Units
VCCIO Input source voltage 1.4 1.6 V
VT+ Input hysteresis threshold voltage 0.5 x VCCIO 0.8 x VCCIO V
VT- 0.2 x VCCIO 0.5 x VCCIO V
VOH High level output voltage IOH = –8 mA, VCCIO = 1.4V VCCIO – 0.45 - V
IOH = –0.1 mA, VCCIO = 1.4V VCCIO – 0.2 - V
VOL Low level output voltage IOL = 8 mA, VCCIO = 1.4V - 0.4 V
IOL = 0.1 mA, VCCIO = 1.4V - 0.2 V
Notes:
1. Hysteresis used on 1.5V inputs.
XC2C32A CoolRunner-II CPLD
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Product Specification
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Schmitt Trigger Input DC Voltage Specifications
AC Electrical Characteristics Over Recommended Operating Conditions
Symbol Parameter Test Conditions Min. Max. Units
VCCIO Input source voltage 1.4 3.9 V
VT+ Input hysteresis threshold voltage 0.5 x VCCIO 0.8 x VCCIO V
VT- 0.2 x VCCIO 0.5 x VCCIO V
Symbol Parameter
-4 -6
UnitsMin. Max. Min. Max.
TPD1 Propagation delay single p-term - 3.8 - 5.5 ns
TPD2 Propagation delay OR array - 4.0 - 6.0 ns
TSUD Direct input register clock setup time 1.7 - 2.2 - ns
TSU1 Setup time fast (single p-term) 1.9 - 2.6 - ns
TSU2 Setup time (OR array) 2.1 - 3.1 - ns
THD Direct input register hold time 0.0 - 0.0 - ns
THP-term hold time 0.0 - 0.0 - ns
TCO Clock to output - 3.7 - 4.7 ns
FTOGGLE(1) Internal toggle rate - 500 - 300 MHz
FSYSTEM1(2) Maximum system frequency - 323 - 200 MHz
FSYSTEM2(2) Maximum system frequency - 303 - 182 MHz
FEXT1(3) Maximum external frequency - 179 - 137 MHz
FEXT2(3) Maximum external frequency - 172 - 128 MHz
TPSUD Direct input register p-term clock setup time 0.4 - 0.9 - ns
TPSU1 P-term clock setup time (single p-term) 0.6 - 1.3 - ns
TPSU2 P-term clock setup time (OR array) 0.8 - 1.8 - ns
TPHD Direct input register p-term clock hold time 1.5 - 1.6 - ns
TPH P-term clock hold 1.3 - 1.2 - ns
TPCO P-term clock to output - 5.0 - 6.0 ns
TOE/TOD Global OE to output enable/disable - 4.7 - 5.5 ns
TPOE/TPOD P-term OE to output enable/disable - 6.2 - 6.7 ns
TMOE/TMOD Macrocell driven OE to output enable/disable - 6.2 - 6.9 ns
TPAO P-term set/reset to output valid - 5.5 - 6.8 ns
TAO Global set/reset to output valid - 4.5 - 5.5 ns
TSUEC Register clock enable setup time 2.0 - 3.0 - ns
THEC Register clock enable hold time 0.0 - 0.0 - ns
TCW Global clock pulse width High or Low 1.4 - 2.2 - ns
TPCW P-term pulse width High or Low 4.0 - 6.0 - ns
TAPRPW Asynchronous preset/reset pulse width (High or Low) 4.0 - 6.0 - ns
TCONFIG(4) Configuration time - 50 - 50 μs
Notes:
1. FTOGGLE is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II family data sheet).
2. FSYSTEM1 (1/TCYCLE) is the internal operating frequency for a device fully populated with one 16-bit counter through one p-term per
macrocell while FSYSTEM2 is through the OR array.
3. FEXT1 (1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array.
4. Typical configuration current during TCONFIG is 500 μA.
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Product Specification
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Internal Timing Parameters
Symbol Parameter(1)
-4 -6
UnitsMin. Max. Min. Max.
Buffer Delays
TIN Input buffer delay - 1.3 - 1.7 ns
TDIN Direct register input delay - 1.5 - 2.4 ns
TGCK Global Clock buffer delay - 1.3 - 2.0 ns
TGSR Global set/reset buffer delay - 1.6 - 2.0 ns
TGTS Global 3-state buffer delay - 1.1 - 2.1 ns
TOUT Output buffer delay - 1.8 - 2.0 ns
TEN Output buffer enable/disable delay - 2.9 - 3.4 ns
P-term Delays
TCT Control term delay - 1.3 - 1.6 ns
TLOGI1 Single p-term delay adder - 0.4 - 1.1 ns
TLOGI2 Multiple p-term delay adder - 0.2 - 0.5 ns
Macrocell Delay
TPDI Input to output valid - 0.3 - 0.7 ns
TLDI Setup before clock (transparent latch) - 1.5 - 2.5 ns
TSUI Setup before clock 1.5 - 1.8 - ns
THI Hold after clock 0.0 - 0.0 - ns
TECSU Enable clock setup time 0.7 - 1.7 - ns
TECHO Enable clock hold time 0.0 - 0.0 - ns
TCOI Clock to output valid - 0.6 - 0.7 ns
TAOI Set/reset to output valid - 1.1 - 1.5 ns
Feedback Delays
TFFeedback delay - 0.6 - 1.4 ns
TOEM Macrocell to global OE delay - 0.7 - 0.8 ns
I/O Standard Time Adder Delays 1.5V CMOS
THYS15 Hysteresis input adder - 3.0 - 4.0 ns
TOUT15 Output adder - 0.8 - 1.0 ns
TSLEW15 Output slew rate adder - 4.0 - 5.0 ns
I/O Standard Time Adder Delays 1.8V CMOS
THYS18 Hysteresis input adder - 3.0 - 4.0 ns
TOUT18 Output adder - 0.0 - 0.0 ns
TSLEW Output slew rate adder - 4.0 - 5.0 ns
XC2C32A CoolRunner-II CPLD
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Product Specification
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Switching Characteristics AC Test Circuit
I/O Standard Time Adder Delays 2.5V CMOS
TIN25 Standard input adder - 0.5 - 0.6 ns
THYS25 Hysteresis input adder - 3.0 - 4.0 ns
TOUT25 Output adder - 0.6 - 0.7 ns
TSLEW25 Output slew rate adder - 4.0 - 5.0 ns
I/O Standard Time Adder Delays 3.3V CMOS/TTL
TIN33 Standard input adder - 0.5 - 0.6 ns
THYS33 Hysteresis input adder - 3.0 - 4.0 ns
TOUT33 Output adder - 1.0 - 1.2 ns
TSLEW33 Output slew rate adder - 4.0 - 5.0 ns
Notes:
1. 1.5 ns input pin signal rise/fall.
Internal Timing Parameters (Continued)
Symbol Parameter(1)
-4 -6
UnitsMin. Max. Min. Max.
Figure 2: Derating Curve for TPD
Number of Outputs Switching
12 4 8 16
3.0
4.0
5.0
VCC = VCCIO = 1.8V @ 25
o
C
TPD2 (ns)
5.5
4.5
3.5
DS091_02_112002
Figure 3: AC Load Circuit
R1
VCC
CL
R2
Device
Under Test
Output Type
LVTTL33
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
CL includes test fixtures and probe capacitance.
1.5 nsec maximum rise/fall times on inputs.
R1
268Ω
275Ω
188Ω
112.5Ω
150Ω
R2
235Ω
275Ω
188Ω
112.5Ω
150Ω
CL
35 pF
35 pF
35pF
35pF
35pF
DS310_03_102108
Test Point
XC2C32A CoolRunner-II CPLD
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Product Specification
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Typical I/O Output Curves
Figure 4: Typical I/V Curve for XC2C32A
VO (Output Volts)
XC32_VoIo_all_0403
IO (Output Current mA)
0
0
40
10
50
20
30
60
3.02.52.01.51.0.5 3.5
3.3V
1.5V
1.8V
2.5V
Iol
Pin Descriptions
Function Block Macrocell QFG32 PC44(1) VQ44 CP56 I/O Bank
1 1 44 38 F1 Bank 2
1 2 43 37 E3 Bank 2
1 3 42 36 E1 Bank 2
1(GTS1) 4 3 40 34 D1 Bank 2
1(GTS0) 5 2 39 33 C1 Bank 2
1(GTS3) 6 1 38 32 A3 Bank 2
1(GTS2) 7 32 37 31 A2 Bank 2
1(GSR)8 313630B1Bank 2
1 9 303529A1Bank 2
1 10 29 34 28 C4 Bank 2
1 11283327C5Bank 2
1 12242923C8Bank 2
113 2822A10Bank 2
1 14232721B10Bank 2
1 15 26 20 C10 Bank 2
1 16 25 19 E8 Bank 2
215139G1Bank 1
2 2 2 40 F3 Bank 1
2 3 3 41 H1 Bank 1
2 4 4 42 G3 Bank 1
2(GCK0) 5 6 5 43 J1 Bank 1
2(GCK1) 6 7 6 44 K1 Bank 1
2(GCK2) 7 8 7 1 K2 Bank 1
XC2C32A CoolRunner-II CPLD
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Product Specification
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XC2C32A Global, JTAG, Power/Ground, and No Connect Pins
2 8 9 8 2 K3 Bank 1
2 9 10 9 3 H3 Bank 1
2 10 11 5 K5 Bank 1
211 126H5Bank 1
21213148H8Bank 1
2 13171812K8Bank 1
2 14181913H10Bank 1
2 15192014G10Bank 1
2 16 22 16 F10 Bank 1
Notes:
1. This is an obsolete package type. It remains here for legacy support only.
2. GTS = global output enable, GSR = global set reset, GCK = global clock.
3. GTS, GSR, and GCK pins can also be used for general purpose I/O.
Pin Type QFG32 PC44(1)(2) VQ44(2) CP56(2)
TCK 16 17 11 K10
TDI 14 15 9 J10
TDO 25 30 24 A6
TMS 15 16 10 K9
Input Only 22 (bank 2) 24 (bank 2) 18 (bank 2) D10 (bank 2)
VCCAUX (JTAG supply voltage) 4 41 35 D3
Power internal (VCC)
Power bank 1 I/O (VCCIO1)
Power bank 2 I/O (VCCIO2)
20 21 15 G8
12 13 7 H6
27 32 26 C6
Ground 11, 21, 26 10,23,31 4,17,25 H4, F8, C7
No connects - - K4, K6, K7, H7,
E10, A7, A9, D8,
A5, A8, A4, C3
Total user I/O (includes dual function pins) 21 33 33 33
Notes:
1. This is an obsolete package type. It remains here for legacy support only.
2. All packages pin compatible with larger macrocell densities.
Pin Descriptions (Continued)
Function Block Macrocell QFG32 PC44(1) VQ44 CP56 I/O Bank
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Product Specification
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Ordering Information
Device Part Marking
Figure 5: Sample Package with Part Marking
Note: Due to the small size of chip scale and quad flat no lead packages, the complete ordering part number cannot be
included on the package marking. Part marking on chip scale and quad flat no lead packages by line are:
Line 1 = X (Xilinx logo) then truncated part number
Line 2 = Not related to device part number
Line 3 = Not related to device part number
Line 4 = Package code, speed, operating temperature,
three digits not related to device part number. Package
codes: C3 = CP56, C4 = CPG56, Q1 = QFG32.
Part Number
Pin/Ball
Spacing
θJA
(°C/Watt)
θJC
(°C/Watt) Package Type
Package Body
Dimensions I/O
Comm. (C)
Ind. (I)(1)
XC2C32A-4QFG32C 0.5mm 35.5 24.0 Quad Flat No Lead; Pb-free 5mm x 5mm 21 C
XC2C32A-6QFG32C 0.5mm 35.5 24.0 Quad Flat No Lead; Pb-free 5mm x 5mm 21 C
XC2C32A-4VQ44C 0.8mm 47.7 8.2 Very Thin Quad Flat Pack 10mm x 10mm 33 C
XC2C32A-6VQ44C 0.8mm 47.7 8.2 Very Thin Quad Flat Pack 10mm x 10mm 33 C
XC2C32A-4CP56C 0.5mm 66.0 14.9 Chip Scale Package 6mm x 6mm 33 C
XC2C32A-6CP56C 0.5mm 66.0 14.9 Chip Scale Package 6mm x 6mm 33 C
XC2C32A-4VQG44C 0.8mm 47.7 8.2 Very Thin Quad Flat Pack; Pb-free 10mm x 10mm 33 C
XC2C32A-6VQG44C 0.8mm 47.7 8.2 Very Thin Quad Flat Pack; Pb-free 10mm x 10mm 33 C
XC2C32A-4CPG56C 0.5mm 66.0 14.9 Chip Scale Package; Pb-free 6mm x 6mm 33 C
XC2C32A-6CPG56C 0.5mm 66.0 14.9 Chip Scale Package; Pb-free 6mm x 6mm 33 C
XC2C32A-6QFG32I 0.5mm 35.5 24.0 Quad Flat No Lead; Pb-free 5mm x 5mm 21 I
XC2C32A-6VQ44I 0.8mm 47.7 8.2 Very Thin Quad Flat Pack 10mm x 10mm 33 I
XC2C32A-6CP56I 0.5mm 66.0 14.9 Chip Scale Package 6mm x 6mm 33 I
XC2C32A-6VQG44I 0.8mm 47.7 8.2 Very Thin Quad Flat Pack; Pb-free 10mm x 10mm 33 I
XC2C32A-6CPG56I 0.5mm 66.0 14.9 Chip Scale Package; Pb-free 6mm x 6mm 33 I
Notes:
1. C = Commercial (TA = 0°C to +70°C); I = Industrial (TA = –40°C to +85°C)
Standard Example: XC2C128
Device
Speed Grade
Package Type
Number of Pins
Temperature Range
-4 TQ C144 Pb-Free Example:
XC2C128 TQ G 144 C
Device
Speed Grade
Package Type
Pb-Free
Number of Pins
-4
Temperature Range
XC2Cxxx
TQ144
7C
Device Type
Package
Speed
Operating Range
This line not
related to device
part number
R
Part marking for non-chip scale package
DS310_05_102108
XC2C32A CoolRunner-II CPLD
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Product Specification
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Figure 6: QFG32 Package Figure 7: VQ44 Package
Figure 8: PC44 Package
QFG32
Top View
I/O
I/O
Input
Gnd
Vcc
I/O
I/O
I/O
I/O(1)
I/O(3)
I/O
I/O
I/O
Vccio2
Gnd
TDO
I/O
I/O
Gnd
Vccio1
I/O
TDI
TMS
TCK
I/O(1)
I/O(1)
I/O(1)
V
AUX
I/O
I/O(2)
I/O(2)
I/O(2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
VQ44
Top View
I/O(1)
I/O(1)
I/O(1)
I/O(3)
I/O
I/O
I/O
VCCIO2
GND
TDO
I/O
I/O
(2)
I/O
(2)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
AUX
I/O
(1)
I/O
I/O
I/O
VCC
I/O
GND
I
I/O
I/O
I/O
I/O
I/O(2)
I/O
I/O
GND
I/O
I/O
VCCIO1
I/O
TDI
TMS
TCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
(1) - Global Output Enabl
e
(2) - Global Clock
(3) - Global Set/Reset
XC2C32A CoolRunner-II CPLD
12 www.xilinx.com DS310 (v2.1) November 6, 2008
Product Specification
R
Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Figure 9: CP56 Package
CP56
Bottom View
I/O(2) I/O(2) I/O NC I/O NC NC I/O TMS TCK
I/O(2) TDI
I/O I/O GND I/O
VCC
IO1
NC I/O I/O
I/O I/O VCC I/O
I/O I/O GND I/O
I/O I/O I/O NC
I/O(1) VAUX NC I
I/O(1) NC I/O I/O
VCC
IO2
GND I/O I/O
I/O(3) I/O
I/O I/O(1) I/O(1) NC NC TDO NC NC NC I/O
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
XC2C32A CoolRunner-II CPLD
DS310 (v2.1) November 6, 2008 www.xilinx.com 13
Product Specification
R
Additional Information
Additional information is available for the following CoolRunner-II topics:
XAPP784: Bulletproof CPLD Design Practices
XAPP375: Timing Model
XAPP376: Logic Engine
XAPP378: Advanced Features
XAPP382: I/O Characteristics
XAPP389: Powering CoolRunner-II
XAPP399: Assigning VREF Pins
To access these and all application notes with their associ-
ated reference designs, click the following links and scroll
down the page until you find the document you want:
CoolRunner-II CPLD Data Sheets and Application Notes
Device Packages
Revision History
The following table shows the revision history for this document.
Date Version Revision
6/15/04 1.0 Initial Xilinx release.
8/30/04 1.1 Pb-free documentation
10/01/04 1.2 Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics.
11/08/04 1.3 Product Release. No changes to documentation.
11/22/04 1.4 Changes to output enable/disable specifications; changes to ICCSB.
02/17/05 1.5 Changes to fTOGGLE, tSLEW25, and tSLEW33
03/07/05 1.6 Improvement of pin-to-pin logic delay, page 1. Modifications to Table 1, IOSTANDARDs.
06/28/05 1.7 Move to Product Specification. Change to TIN25, TOUT25, TIN33, and TOUT33.
03/20/06 1.8 Add Warranty Disclaimer. Add note to Pin Descriptions that GCK, GSR, and GTS pins can also
be used for general purpose I/O.
02/15/07 1.9 Change to VIH specification for 2.5V and 1.8V LVCMOS. Change to TOEM for -4 speed
grade.
03/08/07 2.0 Fixed typo in note for VIL for LVCMOS18; removed note for VIL for LVCMOS33.
11/06/08 2.1 Added note to Pin Description tables to indicate the PC44 packages are obsolete. Removed
part numbers for devices in PC44 packages from ordering information. See Product
Discontinuation Notice xcn07022.pdf.
XC2C32A CoolRunner-II CPLD
14 www.xilinx.com DS310 (v2.1) November 6, 2008
Product Specification
R

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