CAD | USD

STM32F469xx Datasheet

STMicroelectronics

View All Related Products | Download PDF Datasheet

Datasheet

This is information on a product in full production.
May 2018 DS11189 Rev 5 1/219
STM32F469xx
Arm
®
Cortex
®
-M4 32b MCU+FPU, 225DMIPS, up to 2MB Flash/384+4KB RAM, USB OTG HS/FS,
Ethernet, FMC, dual Quad-SPI, Graphical accelerator, Camera IF, LCD-TFT & MIPI DSI
Datasheet - production data
Features
Core: Arm® 32-bit Cortex®-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 180 MHz,
MPU, 225 DMIPS/1.25 DMIPS/MHz
(Dhrystone 2.1), and DSP instructions
Memories
Up to 2 MB of Flash memory organized into two
banks allowing read-while-write
Up to 384+4 KB of SRAM including 64 KB of
CCM (core coupled memory) data RAM
Flexible external memory controller with up to
32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR, SDRAM, Flash NOR/NAND
memories
Dual-flash mode Quad-SPI interface
Graphics:
Chrom-ART Accelerator™ (DMA2D), graphical
hardware accelerator enabling enhanced
graphical user interface with minimum CPU load
LCD parallel interface, 8080/6800 modes
LCD TFT controller supporting up to XGA
resolution
–MIPI
® DSI host controller supporting up to 720p
30Hz resolution
Clock, reset and supply management
1.7 V to 3.6 V application supply and I/Os
POR, PDR, PVD and BOR
4-to-26 MHz crystal oscillator
Internal 16 MHz factory-trimmed RC (1%
accuracy)
32 kHz oscillator for RTC with calibration
Internal 32 kHz RC with calibration
Low power
Sleep, Stop and Standby modes
–V
BAT supply for RTC, 20×32 bit backup registers
+ optional 4 KB backup SRAM
3×12-bit, 2.4 MSPS ADC: up to 24 channels
and 7.2 MSPS in triple interleaved mode
2×12-bit D/A converters
General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
Up to 17 timers: up to twelve 16-bit and two 32-
bit timers up to 180 MHz, each with up to 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input. 2x watchdogs and
SysTick timer
Debug mode
SWD & JTAG interfaces
–Cortex
®-M4 Trace Macrocell™
Up to 161 I/O ports with interrupt capability
Up to 157 fast I/Os up to 90 MHz
Up to 159 5 V-tolerant I/Os
Up to 21 communication interfaces
Up to 3 × I2C interfaces (SMBus/PMBus)
Up to 4 USARTs and 4 UARTs (11.25 Mbit/s,
ISO7816 interface, LIN, IrDA, modem control)
Up to 6 SPIs (45 Mbits/s), 2 with muxed full-
duplex I2S for audio class accuracy via internal
audio PLL or external clock
1 x SAI (serial audio interface)
2 × CAN (2.0B Active)
SDIO interface
Advanced connectivity
USB 2.0 full-speed device/host/OTG controller
with on-chip PHY
USB 2.0 high-speed/full-speed device/host/OTG
controller with dedicated DMA, on-chip full-
speed PHY and ULPI
Dedicated USB power rail enabling on-chip
PHYs operation throughout the entire MCU
power supply range
10/100 Ethernet MAC with dedicated DMA:
supports IEEE 1588v2 hardware, MII/RMII
8- to 14-bit parallel camera interface up to
54 Mbytes/s
True random number generator
CRC calculation unit
RTC: subsecond accuracy, hardware calendar
96-bit unique ID
Table 1. Device summary
Reference Part numbers
STM32F469xx
STM32F469AE, STM32F469AG, STM32F469AI
STM32F469BE, STM32F469BG, STM32F469BI
STM32F469IE, STM32F469IG, STM32F469II
STM32F469NE, STM32F469NG, STM32F469NI
STM32F469VE, STM32469VG, STM32469VI
STM32F469ZE, STM32469ZG, STM32469ZI
&"'!
WLCSP168
UFBGA176 (10 x 10 mm)
TFBGA216 (13 x 13 mm)
LQFP100 (14 × 14 mm)
LQFP144 (20 × 20 mm)
LQFP176 (24 × 24 mm)
LQFP208 (28 × 28 mm)
UFBGA169 (7 × 7 mm)
www.st.com
Contents STM32F469xx
2/219 DS11189 Rev 5
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1 Compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.1.1 LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.1.2 LQFP208 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.1.3 UFBGA176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.1.4 TFBGA216 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.1 Arm® Cortex®-M4 with FPU and embedded Flash and SRAM . . . . . . . . 21
2.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 21
2.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 22
2.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.9 Flexible Memory Controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.10 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.11 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.12 DSI Host (DSIHOST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.13 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.14 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 27
2.15 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.16 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.17 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.18 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.19 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.19.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.19.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.20 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.20.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.20.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DS11189 Rev 5 3/219
STM32F469xx Contents
5
2.20.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 35
2.21 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 35
2.22 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.23 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.24 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.24.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.24.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.24.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.24.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.24.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.24.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.25 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.26 Universal synchronous/asynchronous receiver transmitters (USART) . . 40
2.27 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.28 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.29 Serial Audio interface (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.30 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.31 Audio and LCD PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.32 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 42
2.33 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 43
2.34 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.35 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 44
2.36 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 44
2.37 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.38 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.39 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.40 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.41 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.42 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.43 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.44 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Contents STM32F469xx
4/219 DS11189 Rev 5
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 96
5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 96
5.3.5 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . 96
5.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 123
5.3.13 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.3.14 MIPI D-PHY PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.3.15 MIPI D-PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.3.16 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.3.17 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.3.18 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 132
5.3.19 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.3.20 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.3.21 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.3.22 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.3.23 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.3.24 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
DS11189 Rev 5 5/219
STM32F469xx Contents
5
5.3.25 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.3.26 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.3.27 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.3.28 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
5.3.29 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.3.30 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
5.3.31 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 186
5.3.32 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 187
5.3.33 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 189
5.3.34 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.2 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.3 WLCSP168 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
6.4 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.5 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.6 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
6.7 LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
6.8 TFBGA216 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
6.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 216
A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
List of tables STM32F469xx
6/219 DS11189 Rev 5
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F469xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 32
Table 4. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 5. Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 6. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 7. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 8. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 9. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 10. STM32F469xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 11. FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 12. Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 13. STM32F469xx register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 18. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 95
Table 19. VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 20. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 96
Table 21. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 96
Table 22. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 23. Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled except prefetch) or RAM,
regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled), regulator ON . . . . . . . . . . . . . . 101
Table 26. Typical and maximum current consumption in Run mode, code with data
processing running from Flash memory (ART accelerator enabled except prefetch),
regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 27. Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 103
Table 28. Typical and maximum current consumption in Sleep mode, regulator OFF . . . . . . . . . . . 104
Table 29. Typical and maximum current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 30. Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 106
Table 31. Typical and maximum current consumption in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 107
Table 32. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 33. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 34. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 35. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 36. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 37. HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 38. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 39. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 40. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 41. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 42. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 43. PLLSAI (audio and LCD-TFT PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
DS11189 Rev 5 7/219
STM32F469xx List of tables
8
Table 44. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 45. MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 46. MIPI D-PHY AC characteristics LP mode and HS/LP transitions . . . . . . . . . . . . . . . . . . . 126
Table 47. DSI-PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 48. DSI regulator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 49. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 50. Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 51. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 52. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 53. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 54. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 55. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 56. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 57. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 58. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 59. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 60. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 61. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 62. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 63. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 64. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 65. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 66. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 67. USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 68. USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 69. USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 70. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 71. USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 72. Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 73. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 74. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 75. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 76. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 77. ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 78. ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 79. ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 80. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 159
Table 81. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 159
Table 82. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 83. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 84. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 85. internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 86. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 87. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR - read timings . . . . . . . . . . . . . . . . 167
Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 167
Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 168
Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 169
Table 92. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 93. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 170
Table 94. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 95. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 172
List of tables STM32F469xx
8/219 DS11189 Rev 5
Table 96. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 97. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 98. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 99. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 100. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 101. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 102. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 103. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 104. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 105. LPSDR SDRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 106. Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 107. Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 108. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 109. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 110. Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V . . . . . . . . . . . . . 190
Table 111. Dynamic characteristics: SD / MMC characteristics, VDD = 1.71 to 1.9 V . . . . . . . . . . . . 191
Table 112. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 113. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 114. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 115. WLCSP168 - 168-pin, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 116. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 117. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 118. UFBGA176+25, - 201-ball, 10 x 10 mm, 0.65 mm pitch,
ultra fine pitch ball grid array package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 119. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 207
Table 120. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 121. TFBGA216 - thin fine pitch ball grid array 13 × 13 × 0.8mm
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 122. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 123. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 124. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 216
Table 125. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
DS11189 Rev 5 9/219
STM32F469xx List of figures
11
List of figures
Figure 1. Incompatible board design for LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 2. Incompatible board design for LQFP208 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3. UFBGA176 port-to-terminal assignment differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 4. TFBGA216 port-to-terminal assignment differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 5. STM32F469xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6. STM32F469xx Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 7. VDDUSB connected to an external independent power supply . . . . . . . . . . . . . . . . . . . . . 29
Figure 8. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 30
Figure 9. PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1 , VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 12. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1 , VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 35
Figure 13. STM32F46x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 14. STM32F46x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 15. STM32F46x WLCSP168 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 16. STM32F46x UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 17. STM32F46x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 18. STM32F46x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 19. STM32F46x LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 20. STM32F46x TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 21. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 22. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 23. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 24. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 25. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 26. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 27. Typical VBAT current consumption
(RTC ON / backup SRAM ON and LSE in Low drive mode) . . . . . . . . . . . . . . . . . . . . . . 107
Figure 28. Typical VBAT current consumption
(RTC ON / backup SRAM ON and LSE in High drive mode) . . . . . . . . . . . . . . . . . . . . . . 108
Figure 29. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 30. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 31. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 32. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 33. ACCHSI vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 34. ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 35. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 36. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 37. MIPI D-PHY HS/LP clock lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 38. MIPI D-PHY HS/LP data lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 39. FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 40. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 41. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 42. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 43. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 44. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
List of figures STM32F469xx
10/219 DS11189 Rev 5
Figure 45. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 46. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 47. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 48. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 49. USB OTG full speed timings: definition of data signal rise and fall time. . . . . . . . . . . . . . 151
Figure 50. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 51. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 52. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 53. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 54. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 55. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 56. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 161
Figure 57. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 161
Figure 58. 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 59. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 166
Figure 60. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 168
Figure 61. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 62. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 63. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 64. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 65. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 66. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 67. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 68. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 69. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 180
Figure 70. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 181
Figure 71. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 72. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 73. Quad-SPI SDR timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 74. Quad-SPI DDR timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 75. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 76. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 77. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 78. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 79. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 80. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 192
Figure 81. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 82. LQFP100 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 83. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 195
Figure 84. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 85. LQFP144 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 86. WLCSP168 - 168-pin, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip
scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 87. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 88. UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 89. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 202
Figure 90. LQFP176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 91. LQFP176 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 92. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch,
DS11189 Rev 5 11/219
STM32F469xx List of figures
11
ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 93. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball
grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 94. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 208
Figure 95. LQFP208 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 96. LQFP208 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 97. TFBGA216 - thin fine pitch ball grid array 13 × 13 × 0.8mm, package outline . . . . . . . . . 212
Figure 98. TFBGA216 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Description STM32F469xx
12/219 DS11189 Rev 5
1 Description
The STM32F469xx devices are based on the high-performance Arm®(a) Cortex®-M4 32-bit
RISC core operating at a frequency of up to 180 MHz. The Cortex®-M4 core features a
Floating point unit (FPU) single precision which supports all Arm® single-precision data-
processing instructions and data types. It also implements a full set of DSP instructions and
a memory protection unit (MPU) which enhances application security.
The STM32F469xx devices incorporate high-speed embedded memories (Flash memory
up to 2 Mbytes, up to 384 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an
extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB
buses and a 32-bit multi-AHB bus matrix.
All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers,
and a true random number generator (RNG). They also feature standard and advanced
communication interfaces:
Up to three I2Cs
Six SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can
be clocked via a dedicated internal audio PLL or via an external clock to allow
synchronization.
Four USARTs plus four UARTs
An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI)
Two CANs
One SAI serial audio interface
An SDMMC host interface
Ethernet and camera interface
LCD-TFT display controller
Chrom-ART Accelerator™
DSI Host.
Advanced peripherals include an SDMMC interface, a flexible memory control (FMC)
interface, a Quad-SPI Flash memory, and camera interface for CMOS sensors. Refer to
Table 2 for the list of peripherals available on each part number.
The STM32F469xx devices operate in the –40 to +105 °C temperature range from a 1.7 to
3.6 V power supply. A dedicated supply input for USB (OTG_FS and OTG_HS) only in full
speed mode, is available on all packages.
The supply voltage can drop to 1.7 V (refer to Section 2.19.2). A comprehensive set of
power-saving mode allows the design of low-power applications.
The STM32F469xx devices are offered in eight packages, ranging from 100 to 216 pins.
The set of included peripherals changes with the device chosen, according to Table 2.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS11189 Rev 5 13/219
STM32F469xx Description
47
These features make the STM32F469xx microcontrollers suitable for a wide range of
applications:
Motor drive and application control
Medical equipment
Industrial applications: PLC, inverters, circuit breakers
Printers, and scanners
Alarm systems, video intercom, and HVAC
Home audio appliances
Figure 5 shows the general block diagram of the device family.
Table 2. STM32F469xx features and peripheral counts
Peripherals
STM32F469Vx
STM32F469Zx
STM32F469Ax
STM32F469Ix
STM32F469Bx
STM32F469Nx
Flash memory in Kbytes
512
1024
2048
512
1024
2048
512
1024
2048
512
1024
2048
512
1024
2048
512
1024
2048
SRAM in
Kbytes
System 384 (160+32+128+64)
Backup 4
FMC memory controller Yes
Quad-SPI Yes
Ethernet No Yes
Timers
General-
purpose 10
Advanced-
control 2
Basic 2
Random number generator Yes
Communication
interfaces
SPI / I2S 4/2(full duplex)(1) 6/2(full duplex)(1)
I2C3
USART/UART 4/3 4/4
USB OTG FS Yes
USB OTG HS Yes
CAN 2
SAI 1
SDIO Yes
Camera interface Yes
Description STM32F469xx
14/219 DS11189 Rev 5
MIPI-DSI Host Yes
LCD-TFT Yes
Chrom-ART Accelerator™
(DMA2D) Yes
GPIOs 71 106 114 131 161 161
12-bit ADC
Number of channels
3
14 20 24 16 24 24
12-bit DAC
Number of channels
Yes
2
Maximum CPU frequency 180 MHz
Operating voltage 1.7 to 3.6V(2)
Operating temperatures Ambient operating temperature: 40 to 85 °C / 40 to 105 °C
Junction temperature: 40 to 105 °C / 40 to 125 °C
Package LQFP100 LQPF144 UFBGA169
WLCSP168
LQFP176
UFBGA176 LQFP208 TFBGA216
1. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
2. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.19.2).
Table 2. STM32F469xx features and peripheral counts (continued)
Peripherals
STM32F469Vx
STM32F469Zx
STM32F469Ax
STM32F469Ix
STM32F469Bx
STM32F469Nx
DS11189 Rev 5 15/219
STM32F469xx Description
47
1.1 Compatibility throughout the family
STM32F469xx devices are not compatible with other STM32F4xx devices.
Figure 1 and Figure 2 show incompatible board designs, respectively, for LQFP176 and
LQFP208 packages (highlighted pins).
The UFBGA176 and TFBGA216 ballouts are compatible with other STM32F4xx devices,
only few IO port pins are substituted, as shown in Figure 3 and Figure 4.
The LQFP100, LQFP144 and UFBGA169 packages are incompatible with other
STM32F4xx devices.
Description STM32F469xx
16/219 DS11189 Rev 5
1.1.1 LQFP176 package
Figure 1. Incompatible board design for LQFP176 package
1. Pins from 85 to 133 are not compatible.
069
966
3,
3,
  
 3,
 9''
 966
 9&$3
 3$
 3$
 3$
 3$
 3$
 3$
 3&
 3&
 3&
3&
9''86%
966
3*
3*
3*
3*
3*
 3*
3*
 966'6,
 '6,+267B'1
 '6,+267B'3
 9'''6,
 '6,+267B&.1
 '6,+267B&.3
 966'6,
 '6,+267B'1
 '6,+267B'3
 9&$3'6,
 9''6,
 3'
 3'
 9''
 966
 3'
 3'
 3'
 3'
 3'
 3'
    
670)[[[[
/4)3
3+
3%
3%
3%
3%

966
3,
3,
  
 3,
 3,
 3+
 3+
 3+
 9''
 966
 9&$3
 3$
 3$
 3$
 3$
 3$
3$
3&
3&
3&
3&
9''
966
3*
 3*
3*
 3*
 3*
 3*
 3*
 3'
 3'
 9''
 966
 3'
 3'
 3'
 3'
 3'
 3'
 3%
 3%
 3%
 3%
 9''
 966
 3+
    
3+
3+
3+
3+
670)[[
/4)3
3+
DS11189 Rev 5 17/219
STM32F469xx Description
47
1.1.2 LQFP208 package
Figure 2. Incompatible board design for LQFP208 package
1. Pins from 118 to 128 and pin 137 are not compatible
069
 3& 3&
 9''86% 9''
 966 966
 3* 3*
 3* 3*
 3* 3*
 3* 3*
 3* 3*
 3* 3*
 3* 3*
 966'6, 3.
 '6,+267B'1 3.
 '6,+267B'3 3.
 9'''6, 966
 '6,+267B&.1 9''
 '6,+267B&.3 3-
 966'6, 3-
 '6,+267B'1 3-
 '6,+267B'3 3-
9&$3'6, 3-
9'''6, 3-
3' 3'
3' 3'
670)[670)[
/4)3
670)[[[[
/4)3























Description STM32F469xx
18/219 DS11189 Rev 5
1.1.3 UFBGA176 package
Figure 3. UFBGA176 port-to-terminal assignment differences
1. The highlighted pins are substituted with dedicated DSI IO pins on STM32F469xx/479xx devices.
'6,
+267B
'3
'6,
+267B
'1
'6,
+267B
&.1
'6,
+267B
&.3
9&$3
'6,
9''
'6,
9''B
86%
966
'6,
'6,
+267B
'3
'6,
+267B
'1
9''
'6,
1&
069
     
$3(3(
3( 3( 3% 3% 3 * 3* 3% 3% 3' 3& 3$ 3 $ 3 $
%3(3(
3( 3% 3% 3% 3* 3* 3* 3* 3' 3' 3& 3& 3$
&9%$7 3, 3, 3, 3'5
B21
9'' 3* 3' 3' 3, 3$
'3& 3, 3, 3, %227 966 966 966 3' 3' 3' 3, 3$
(3& 3) 3, 3, 3, 3$
)3&
966 9'' 3+ 966 9&$3 3& 3$
*3+ 966 9'' 3+ 966 9'' 3& 3&
+3+ 3) 3) 3+ 3* 3&
-15 67 3) 3 + 3* 3*
.3) 3)
3)
9'' 966 3* 3* 3*
/3) %<3$66
B5(* 3' 3*
0966$3&
3)
3& 3& 3& 3% 3* 9&$3
B 3+ 3' 3'
195() 3$ 3$ 3& 3) 3* 9'' 9'' 9'' 3( 3+ 3' 3' 3'
33$ 3$ 3$ 3& 3) 3) 3( 3( 3( 3( 3% 3% 3' 3'
53$ 3% 3) 3( 3( 3( 3% 3 % 3% 3%
966

3$
9''
9'' 9'' 9''
95()
9''$ 3$3% 3) 3)
966 966 966 966
966966966 966 966
966966966 966 966
966966966 966 966
966966966 966 966
966 966
3)
3)
3' 3, 3,
3' 3,
3+ 3,
966 9&$3 3&
966 9'' 3&
966 9'' 3*
3*
3* 3*
3'
3'
3+
3+
9''
3+
3+
3+ 3+
3+
9''
3' 3, 1&
3' 3,
'6,
+267B
'3
3,
966 9&$3 3&
966 9'' 3&
966
'6,
9''B
86% 3*
3*
3* 3*
3'
3'
9''
'6,
'6,
+267B
'1
9''
'6,
9&$3
'6,
'6,
+267B
&.3
'6,
+267B
'3
'6,
+267B
'1
'6,
+267B
&.1
9''
^dDϯϮ&ϰϮdždžͬϯdždž
^dDϯϮ&ϰϬdždžͬϰϭdždž
^dDϯϮ&ϰϲϵdždž
^dDϯϮ&ϰϳϵdždž
DS11189 Rev 5 19/219
STM32F469xx Description
47
1.1.4 TFBGA216 package
Figure 4. TFBGA216 port-to-terminal assignment differences
1. The highlighted pins are substituted with dedicated DSI IO pins on STM32F469xx/479xx devices.
06Y9
  
$3* 3( 3( 3% 3% 3% 3% 3' 3& 3$ 3$ 3$
%3( 3( 3* 3% 3% 3% 3* 3* 3- 3- 3' 3' 3& 3& 3$
&9%$7 3, 3, 3. 3. 3. 3* 3* 3- 3' 3' 3, 3, 3$ 
'3& 3) 3, 3, 3, 3, 3. 3. 3* 3- 3' 3' 3+ 3, 3$
(3& 3) 3, 3, %227 9'' 9'' 9'' 9'' 9&$3 3+ 3+ 3, 3$
)3& 966 3, 9'' 3& 3$
*3+ 3) 3, 3, 9'' 3& 3&
+3+ 3, 3+ 966 3* 3&
-1567 3) 3+ 3+ 966 9'' 3* 3*
.3) 3) 3) 3+ 9'' 966 966 966 966 966 9'' 3' 3% 3'
/3) 3& %<3$66
5(* 3% 3' 3'
0966$ 3* 3' 3' 3* 3* 3- 3+
195() 3$ 3$ 3$ 3& 3) 3* 3- 3( 3' 3* 3* 3+ 3+ 3+
95() 3$ 3$ 3$ 3& 3) 3- 3) 3( 3( 3( 3% 3+ 3+ 3+
3$ 3$ 3% 3% 3- 3- 3( 3( 3( 3( 3( 3% 3% 3%
3)
3
59''$
3'5
21
3( 3( 3(
9''
9''
966
966
966
966 966 966 966 966
966
9''
3-3)
9'' 9'' 9'' 9&$3 3'
9''
3)
3)
3& 3& 3& 3% 3)
9''
966
3'
^dDϯϮ&ϰϮdždžͬϯdždž
^dDϯϮ&ϰϬdždžͬϰϭdždž
^dDϯϮ&ϰϲϵdždž
^dDϯϮ&ϰϳϵdždž
9''
9'' 3'
9''
9''
9'' 3'
9''
9''
'6,
'6,
+267B
&.3
9'''
86%
966
'6,
9''
'6,
'6,
+267B
&.1
'6,
+267B
'3
9&$3
'6,
'6,
+267B
'1
'6,
+267B
'3
'6,
+267B
'1
3-
9'' 3-3.
3-
3-
3-
3-
3. 3/
9''
Description STM32F469xx
20/219 DS11189 Rev 5
Figure 5. STM32F469xx block diagram
1. The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to
APB1 are clocked from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration
in the RCC_DCKCFGR register.
4XDG63,
069
86$570%SV*3,23257$
$+%$3%
86$570%SV
(;7,7:.83
$)
3$>@
86$570%SV
*3,23257%
3%>@
86$570%SV
7,0(53:0
FRPSOFKDQ7,0B&+>@1
FKDQ7,0B&+>@(75
%.,1DV$)
86$570%SV7,0(53:0
86$570%SV
*3,23257&
3&>@
86$570%SV
86$57
5;7;6&.
&76576DV$)
86$570%SV*3,23257'
3'>@
86$570%SV*3,23257(
3(>@
86$570%SV
*3,23257)
3)>@
86$570%SV*3,23257*
3*>@
86$570%SV
63,,6
$3% 0 + ]
DQDORJLQSXWVFRPPRQ
WRWKH$'&V
DQDORJLQSXWVFRPPRQ
WRWKH$'&
9''5()B$'&
DQDORJLQSXWVWR$'&
&KDQQHOV(75DV$)
7,0
7,0
7,0
&KDQQHOV
7,0
5;7;6&.
86$57
5;7;6&.
86$57
5;7;DV$)
8$57
5;7;DV$)
8$57
026,0,626&.
166:60&.DV$)
63,,6
026,0,626&.
63,,6 166:60&.DV$)
6&/6'$60%$DV$)
,&60%86
6&/6'$60%$DV$)
,&60%86
7;5;
E[&$1
7;5;
E[&$1
'$&DV$)
'$&
'$&DV$)
'$&
,7)
7,0(5
7,0(5
::'*
.%%.35$0
57&B7$03
57&B7$03
57&B287
57&B5(),1
57&B76
26&B,1
26&B287
26&,1
26&287
9''$966$
1567
86$570%SV86$57
5;7;6&.
&76576DV$)
VPFDUG
LU'$
VPFDUG
LU'$
VPFDUG
LU'$
VPFDUG
LU'$
E
E
E
E
E
E
E
E
&76576DV$)
&76576DV$)
6',200&
'>@
&0'&.DV$)
9%$7 WR9
'0$
$+%$3%
'0$
6&/6'$60%$DV$)
,&60%86
86$570%SV*3,23257+
3+>@
-7$*6:
$50
&RUWH[0
0+] ,%86
6%86
'%86
19,&(70
038)38
-7567-7',
-7&.6:&/.
-7'26:'-7'2
75$&(&.
75$&('
86% '0$
),)2
27*+6
''
9''86% WR9
8/3,&/.'
',56731;7
6&/6'$,17,'9%86 *3'0$ 6WUHDPV
),)2
*3'0$ 6WUHDPV
),)2
)ODVK0%
$&&(/
&$&+(
65$0.%
65$0.%
(;70(0&75/)0&
65$0365$0125)ODVK
1$1')ODVK6'5$0
&/.1(>@$>@'>@
12(1:(11%/>@
6'&/.(>@6'1(>@
15$61&$61$'9
1:$,7,175
&$0(5$ +6<1&96<1&
3,;&.'
,7)
86%
3+<
27*)6 ''
9''86% WR9
6&/6'$,17,'9%86
),)2
3+<
),)2
86$570%SV
7(036(1625
$'&
$'&
$'&
,)
,)
#9''$
#9''$
3253'5
6833/<
683(59,6,21
39'
5HVHW
,QW
325
;7$/26&
0+]
;7$/N+]
0$1$*7
57&
5&+6
5&/6
6WDQGE\LQWHUIDFH
,:'*
#9%$7
#9''$
$:8
5(6(7
&/2&.
&75/
3//
#9''$#9''
%DFNXS5HJLVWHU
$+%0+]
/6
/6
&KDQQHOVDV$)
7,0
&KDQQHOVDV$)
7,0
&+DV$)
7,0
E
E
E
86$570%SV7,0(5
FKDQQHOVDV$)
86$570%SV
7,0(5
FKDQQHODV$)
E
E
86$570%SV
7,0(5
FKDQQHODV$) E
%25
),)2
8$57
8$57
86$570%SV63,
6'6&.)6
0&/.DV$)
&5&
86$570%SV
6$,
'LJ)LOWHU
),)2
&/.
%.B1&6%.B1&6
'>@
86$570%SV
63,
),)2
)ODVK0%
65$0.%
51*
$+%0+]
&KDQQHOV(75DV$)
&KDQQHOV(75DV$)
86$570%SV*3,23257,
3,>@
86$570%SV*3,23257-
3->@
86$570%SV*3,23257.
3.>@
$+%0+]
+&/.[
3&/.[
86$570%SV
63,
026,0,626&.
166DV$)
026,0,626&.
166DV$)
026,0,626&.
166DV$)
026,0,626&.
166DV$)
&&0GDWD5$0.%
/&'7)7 ),)2
'0$' ),)2
'6,+RVW
'6,
3+,
'6,+267B'31
'6,+267B'31
'6,+267B&.31
9'''6,9''6,966'6,
9&$3'6,
'6,+267B7(
FRPSOFKDQ7,0B&+>@1
FKDQ7,0B&+>@(75
%.,1DV$)
5;7;DV$)
5;7;DV$)
$+%%860$75,;
$3%0+]
$3%0+]
DS11189 Rev 5 21/219
STM32F469xx Functional overview
47
2 Functional overview
2.1 Arm® Cortex®-M4 with FPU and embedded Flash and SRAM
The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU core is a 32-bit RISC processor that features exceptional
code-efficiency, delivering the high-performance expected from an Arm® core in the
memory size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions that allow efficient signal processing and
complex algorithm execution. Its single precision FPU (floating point unit) speeds up
software development by using metalanguage development tools, while avoiding saturation.
The STM32F46x line is compatible with all Arm® tools and software.
Figure 5 shows the general block diagram of the STM32F46x line.
Note: Cortex®-M4 with FPU core is binary compatible with the Cortex®-M3 core.
2.2 Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator optimized for STM32 industry-standard
Arm® Cortex®-M4 with FPU processors. It balances the inherent performance advantage of
the Arm® Cortex®-M4 with FPU over Flash memory technologies, which normally require
the processor to wait for the Flash memory at higher frequencies.
To release the processor full 225 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark® benchmark, the
performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 180 MHz.
2.3 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 GBytes
of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
Functional overview STM32F469xx
22/219 DS11189 Rev 5
2.4 Embedded Flash memory
The devices embed a Flash memory of up to 2 Mbytes available for storing programs and
data.
2.5 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
2.6 Embedded SRAM
All devices embed:
Up to 384Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory)
data RAM
RAM memory is accessed (read/write) at CPU clock speed with 0 wait states.
4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or VBAT mode.
2.7 Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB
HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, QUADSPI, AHB
and APB peripherals) and ensures a seamless and efficient operation even when several
high-speed peripherals work simultaneously.
DS11189 Rev 5 23/219
STM32F469xx Functional overview
47
Figure 6. STM32F469xx Multi-AHB matrix
2.8 DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
ZD
ŽƌƚĞdžͲDϰ
'W
Dϭ
'W
DϮ
D
ƚŚĞƌŶĞƚ
h^Kd'
,^
ƵƐŵĂƚƌŝdžͲ^
/K
K
>
&ůĂƐŚ
ŵĞŵŽƌLJ
^ZDϭ
ϭϲϬ<ďLJƚĞ
^ZDϮ
ϯϮ<ďLJƚĞ
,Ϯ
ƉĞƌŝƉŚĞƌĂůƐ
,ϭ
ƉĞƌŝƉŚĞƌĂůƐ
&DĞdžƚĞƌŶĂů
DĞŵƚů
/ͲďƵƐ
ͲďƵƐ
^ͲďƵƐ
DͺW/
DͺDDϭ
DͺDDϮ
DͺWϮ
d,ZEdͺD
h^ͺ,^ͺD
D^ϯϯϴϲϮsϭ
DĚĂƚĂZD
ϲϰͲ<ďLJƚĞ
Wϭ
WϮ
^ZDϯ
ϭϮϴ<ďLJƚĞ
>Ͳd&d ŚƌŽŵZd
ĐĐĞůĞƌĂƚŽƌ;DϮͿ
>Ͳd&dͺD
DϮ
YƵĂĚ^W/
Functional overview STM32F469xx
24/219 DS11189 Rev 5
The DMA can be used with the main peripherals:
SPI and I2S
I2C
USART
General-purpose, basic and advanced-control timers TIMx
DAC
SDIO
Camera interface (DCMI)
ADC
SAI1
QUADSPI.
2.9 Flexible Memory Controller (FMC)
The Flexible memory controller (FMC) includes three memory controllers:
The NOR/PSRAM memory controller
The NAND/memory controller
The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
The main features of the FMC controller are the following:
Interface with static-memory mapped devices including:
Static random access memory (SRAM)
NOR Flash memory/OneNAND Flash memory
– PSRAM
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
8-,16-,32-bit data bus width
Independent Chip Select control for each memory bank
Independent configuration for each memory bank
Write FIFO
Read FIFO for SDRAM controller
The Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is
HCLK/2.
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
DS11189 Rev 5 25/219
STM32F469xx Functional overview
47
2.10 Quad-SPI memory interface (QUADSPI)
All STM32F469xx devices embeds a Quad-SPI memory interface, which is a specialized
communication interface targeting Single, Dual, Quad or Dual-flash SPI memories. It can
work in direct mode through registers, external flash status register polling mode and
memory mapped mode. Up to 256 Mbytes external Flash memory are mapped, supporting
8, 16 and 32-bit access. Code execution is supported.
The opcode and the frame format are fully programmable. Communication can be either in
Single Data Rate or Dual Data Rate.
2.11 LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
2 displays layers with dedicated FIFO (64x32-bit)
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
Up to 8 Input color formats selectable per layer
Flexible blending between two layers using alpha value (per pixel or constant)
Flexible programmable parameters for each layer
Color keying (transparency color)
Up to 4 programmable interrupt events.
2.12 DSI Host (DSIHOST)
The DSI Host is a dedicated peripheral for interfacing with MIPI® DSI compliant displays. It
includes a dedicated video interface internally connected to the LTDC and a generic APB
interface that can be used to transmit information to the display.
These interfaces are as follows:
LTDC interface:
Used to transmit information in Video Mode, in which the transfers from the host
processor to the peripheral take the form of a real-time pixel stream (DPI).
Through a customized for mode, this interface can be used to transmit information
in full bandwidth in the Adapted Command Mode (DBI).
APB slave interface:
Allows the transmission of generic information in Command mode, and follows a
proprietary register interface.
Can operate concurrently with either LTDC interface in either Video Mode or
Adapted Command Mode.
Video mode pattern generator:
Allows the transmission of horizontal/vertical color bar and D-PHY BER testing
pattern without any kind of stimuli.
Functional overview STM32F469xx
26/219 DS11189 Rev 5
The DSI Host main features:
Compliant with MIPI® Alliance standards
Interface with MIPI® D-PHY
Supports all commands defined in the MIPI® Alliance specification for DCS:
Transmission of all Command mode packets through the APB interface
Transmission of commands in low-power and high-speed during Video Mode
Supports up to two D-PHY data lanes
Bidirectional communication and escape mode support through data lane 0
Supports non-continuous clock in D-PHY clock lane for additional power saving
Supports Ultra Low-Power mode with PLL disabled
ECC and Checksum capabilities
Support for End of Transmission Packet (EoTp)
Fault recovery schemes
3D transmission support
Configurable selection of system interfaces:
AMBA APB for control and optional support for Generic and DCS commands
Video Mode interface through LTDC
Adapted Command Mode interface through LTDC
Independently programmable Virtual Channel ID in
Video Mode
Adapted Command Mode
APB Slave
Video Mode interfaces features
LTDC interface color coding mappings into 24-bit interface:
16-bit RGB, configurations 1, 2, and 3
18-bit RGB, configurations 1 and 2
24-bit RGB
Programmable polarity of all LTDC interface signals
Maximum resolution is limited by available DSI physical link bandwidth:
Number of lanes: 2
Maximum speed per lane: 500Mbps
Adapted interface features
Support for sending large amounts of data through the memory_write_start (WMS) and
memory_write_continue (WMC) DCS commands
LTDC interface color coding mappings into 24-bit interface:
16-bit RGB, configurations 1, 2, and 3
18-bit RGB, configurations 1 and 2
24-bit RGB
DS11189 Rev 5 27/219
STM32F469xx Functional overview
47
Video mode pattern generator
Vertical and horizontal color bar generation without LTDC stimuli
BER pattern without LTDC stimuli
2.13 Chrom-ART Accelerator™ (DMA2D)
The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
Rectangle filling with a fixed color
Rectangle copy
Rectangle copy with pixel format conversion
Rectangle composition with blending and pixel format conversion.
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
2.14 Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 93 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-
M4 with FPU core.
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor state automatically saved on interrupt entry, and restored on interrupt exit,
with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
2.15 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 23 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 159 GPIOs can be connected
to the 16 external interrupt lines.
Functional overview STM32F469xx
28/219 DS11189 Rev 5
2.16 Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full
temperature range. The application can then select as system clock either the RC oscillator
or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is
detected, the system automatically switches back to the internal RC oscillator and a
software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing
to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL
clock entry is available when necessary (for example if an indirectly used external oscillator
fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 180 MHz while the maximum frequency of the high-speed APB domains is
90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz.
The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio
class performance. In this case, the I2S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
2.17 Boot modes
At startup, boot pins are used to select one out of three boot options:
Boot from user Flash
Boot from system memory
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory
through a serial interface. Refer to application note AN2606 for details.
2.18 Power supply schemes
VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset
blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
Note: VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to
Section 2.19.2). Refer to Table 3 to identify the packages supporting this option.
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
VDDUSB can be connected either to VDD or an external independent power supply (3.0
to 3.6 V) for USB transceivers.
For example, when device is powered at 1.8V, an independent power supply 3.3 V can
be connected to VDDUSB. When the VDDUSB is connected to a separated power supply,
it is independent from VDD or VDDA but it must be the last supply to be provided and the
first to disappear.
DS11189 Rev 5 29/219
STM32F469xx Functional overview
47
The following conditions must be respected:
During power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
During power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
–V
DDUSB rising and falling time rate specifications must be respected.
In operating mode phase, VDDUSB could be lower or higher than VDD:
If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by
VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX.The VDDUSB
supplies both USB transceivers (USB OTG_HS and USB OTG_FS).
If only one USB transceiver is used in the application, the GPIOs associated to
the other USB transceiver are still supplied by VDDUSB.
If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered
by VDDUSB are operating between VDD_MIN and VDD_MAX.
If USB (USB OTG_HS/OTG_FS) is not used and the associated GPIOs
powered by VDDUSB are not used, then VDDUSB should be tied to VSS or VDD
(VDDUSB must not be floating).
Figure 7. VDDUSB connected to an external independent power supply
The DSI (Display Serial Interface) sub-system uses several power supply pins that are
independent from the other supply pins:
VDDDSI is an independent DSI power supply dedicated for DSI Regulator and MIPI
D-PHY. This supply must be connected to global VDD.
VCAPDSI pin is the output of DSI Regulator (1.2 V), which must be connected
externally to VDD12DSI.
VDD12DSI pin is used to supply the MIPI D-PHY, and to supply clock and data lanes
pins. An external capacitor of 2.2 µF must be connected on VDD12DSI pin.
VSSDSI pin is an isolated supply ground used for DSI sub-system.
If DSI functionality is not used at all, then:
VDDDSI pin must be connected to global VDD.
069
9
''86%B0,1
9
''B0,1
WLPH
9
''86%B0$;
86% IXQFWLRQDODUHD
9
''
9
''$
86% QRQ
IXQFWLRQDO
DUHD
9
''86%
3RZHURQ 3RZHUGRZQ
2SHUDWLQJPRGH
86%QRQ
IXQFWLRQDO
DUHD
Functional overview STM32F469xx
30/219 DS11189 Rev 5
VCAPDSI pin must be connected externally to VDD12DSI but the external
capacitor is no more needed.
VSSDSI pin must be grounded.
2.19 Power supply supervisor
2.19.1 Internal reset ON
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On other packages the power supply supervisor is always enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes. The device remains in reset mode when VDD is below a specified threshold,
VPOR/PDR or VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
2.19.2 Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor VDD and NRST and should maintain
the device in reset mode as long as VDD is below a specified threshold. PDR_ON must be
connected to VSS, as shown in Figure 8.
Figure 8. Power supply supervisor interconnection with internal reset OFF
3'5B21
670)[[
966
3'5QRWDFWLYH99''9
9%$7
9''
$SSOLFDWLRQUHVHW
VLJQDORSWLRQDO
069
DS11189 Rev 5 31/219
STM32F469xx Functional overview
47
The VDD specified threshold, below which the device must be maintained under reset, is
1.7 V (see Figure 9).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
The brownout reset (BOR) circuitry must be disabled
The embedded programmable voltage detector (PVD) is disabled
VBAT functionality is no more available and VBAT pin should be connected to VDD.
All packages allow to disable the internal reset through the PDR_ON signal when connected
to VSS.
Figure 9. PDR_ON control with internal reset OFF
1. PDR_ON signal to be kept always low.
2.20 Voltage regulator
The regulator has four operating modes:
Regulator ON
Main regulator mode (MR)
Low power regulator (LPR)
– Power-down
Regulator OFF
069
9''
WLPH
3'5 9
WLPH
1567
3'5B21 3'5B21
5HVHWE\RWKHUVRXUFHWKDQ
SRZHUVXSSO\VXSHUYLVRU
Functional overview STM32F469xx
32/219 DS11189 Rev 5
2.20.1 Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
MR mode used in Run/sleep modes or in Stop modes
In Run/Sleep mode
The MR mode is used either in the normal mode (default mode) or the over-drive
mode (enabled by software). Different voltages scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
The over-drive mode allows operating at a higher frequency than the normal mode
for a given voltage scaling.
In Stop modes
The MR can be configured in two ways during stop mode:
MR operates in normal mode (default mode of MR in stop mode)
MR operates in under-drive mode (reduced leakage mode).
LPR is used in the Stop modes:
The LP regulator mode is configured by software when entering Stop mode.
Like the MR mode, the LPR can be configured in two ways during stop mode:
LPR operates in normal mode (default mode when LPR is ON)
LPR operates in under-drive mode (reduced leakage mode).
Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Refer to Table 3 for a summary of voltage regulator modes versus device operating modes.
Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin. Refer to
Section 2.18 and Table 124.
All packages have the regulator ON feature.
Table 3. Voltage regulator configuration mode versus device operating mode(1)
1. ‘-’ means that the corresponding configuration is not available.
Voltage regulator
configuration Run mode Sleep mode Stop mode Standby mode
Normal mode MR MR MR or LPR -
Over-drive
mode(2)
2. The over-drive mode is not available when VDD = 1.7 to 2.1 V.
MR MR - -
Under-drive mode - - MR or LPR -
Power-down
mode ---Yes
DS11189 Rev 5 33/219
STM32F469xx Functional overview
47
2.20.2 Regulator OFF
This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply
externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency. Refer to Operating conditions.The two
2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer
to Section 2.18.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
In regulator OFF mode, the following features are no more supported:
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
The over-drive and under-drive modes are not available.
The Standby mode is not available.
Figure 10. Regulator OFF
DL9
%<3$66B5(*
9&$3B
9&$3B
3$
9
9'' 1567
9''
$SSOLFDWLRQUHVHW
VLJQDORSWLRQDO
([WHUQDO9&$3BSRZHU
VXSSO\VXSHUYLVRU
([WUHVHWFRQWUROOHUDFWLYH
ZKHQ9&$3B0LQ9
9
Functional overview STM32F469xx
34/219 DS11189 Rev 5
The following conditions must be respected:
VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for
VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1
and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 11).
Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see
Figure 12).
If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a
reset must be asserted on PA0 pin.
Note: The minimum value of V12 depends on the maximum frequency targeted in the application
(see Operating conditions).
Figure 11. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1 , VCAP_2 stabilization
1. This figure is valid whatever the internal reset mode (ON or OFF).
DLJ
9''
WLPH
0LQ9
3'5 RU9 9&$3B9&$3B
9
1567
WLPH
3$
DS11189 Rev 5 35/219
STM32F469xx Functional overview
47
Figure 12. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1 , VCAP_2 stabilization
1. This figure is valid whatever the internal reset mode (ON or OFF).
2.20.3 Regulator ON/OFF and internal reset ON/OFF availability
2.21 Real-time clock (RTC), backup SRAM and backup registers
The backup domain includes:
The real-time clock (RTC)
4 Kbytes of backup SRAM
20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-
coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC provides a programmable alarm and programmable
periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is
also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
9''
WLPH
0LQ9
9&$3B9&$3B
9
3$
1567
WLPH DLI
3'5 RU9
Table 4. Regulator ON/OFF and internal reset ON/OFF availability
Package Regulator ON Regulator OFF Internal reset ON Internal reset OFF
WLCSP168
UFBGA169
LQFP144
LQFP208
Yes No
Yes
PDR_ON set to VDD
Yes
PDR_ON set to VSS
LQFP176
UFBGA176
TFBGA216
Yes
BYPASS_REG set
to VSS
Yes
BYPASS_REG set
to VDD
LQFP100 Yes No Yes No
Functional overview STM32F469xx
36/219 DS11189 Rev 5
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary auto-reload downcounter with programmable resolution is available
and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data
which need to be retained in VBAT and standby mode. This memory area is disabled by
default to minimize power consumption (see Section 2.22). It can be enabled by software.
The backup registers are 32-bit registers used to store 80 bytes of user application data
when VDD power is not present. Backup registers are not reset by a system, a power reset,
or when the device wakes up from the Standby mode (see Section 2.22).
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
Like backup SRAM, the RTC and backup registers are supplied through a switch that is
powered either from the VDD supply when present or from the VBAT pin.
2.22 Low-power modes
The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled.
The voltage regulator can be put either in main regulator mode (MR) or in low-power
mode (LPR). Both modes can be configured as follows (see Table 5):
Normal mode (default mode when MR or LPR is enabled)
Under-drive mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup).
DS11189 Rev 5 37/219
STM32F469xx Functional overview
47
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event
occurs.
The standby mode is not supported when the embedded voltage regulator is bypassed
and the 1.2 V domain is controlled by an external power.
2.23 VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when no external battery and an external supercapacitor are
present.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no
more available and VBAT pin should be connected to VDD.
2.24 Timers and watchdogs
The devices include two advanced-control timers, eight general-purpose timers, two basic
timers and two watchdog timers.
All timer counters can be frozen in debug mode.
Table 6 compares the features of the advanced-control, general-purpose and basic timers.
Table 5. Voltage regulator modes in stop mode
Voltage regulator
configuration Main regulator (MR) Low-power regulator (LPR)
Normal mode MR ON LPR ON
Under-drive mode MR in under-drive mode LPR in under-drive mode
Functional overview STM32F469xx
38/219 DS11189 Rev 5
2.24.1 Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
Input capture
Output compare
PWM generation (edge- or center-aligned modes)
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
Table 6. Timer feature comparison
Timer
type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complementary
output
Max
interface
clock
(MHz)
Max
timer
clock
(MHz)(1)
Advanced
control
TIM1,
TIM8 16-bit
Up,
Down,
Up/down
Any integer
between 1
and 65536
Yes 4 Yes 90 180
General
purpose
TIM2,
TIM5 32-bit
Up,
Down,
Up/down
Any integer
between 1
and 65536
Yes 4 No 45 90/180
TIM3,
TIM4 16-bit
Up,
Down,
Up/down
Any integer
between 1
and 65536
Yes 4 No 45 90/180
TIM9 16-bit Up
Any integer
between 1
and 65536
No 2 No 90 180
TIM10
,
TIM11
16-bit Up
Any integer
between 1
and 65536
No 1 No 90 180
TIM12 16-bit Up
Any integer
between 1
and 65536
No 2 No 45 90/180
TIM13
,
TIM14
16-bit Up
Any integer
between 1
and 65536
No 1 No 45 90/180
Basic TIM6,
TIM7 16-bit Up
Any integer
between 1
and 65536
Yes 0 No 45 90/180
1. The maximum timer clock is either 90 or 180 MHz depending on TIMPRE bit configuration in the
RCC_DCKCFGR register.
DS11189 Rev 5 39/219
STM32F469xx Functional overview
47
2.24.2 General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32F46x devices
(see Table 6 for differences).
TIM2, TIM3, TIM4, TIM5
The STM32F46x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3,
and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/down
counter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit auto-
reload up/down counter and a 16-bit prescaler. They all feature 4 independent
channels for input capture/output compare, PWM or one-pulse mode output. This gives
up to 16 input capture/output compare/PWMs on the largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9
and TIM12 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers. They can also be used as simple time bases.
2.24.3 Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
2.24.4 Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
2.24.5 Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
Functional overview STM32F469xx
40/219 DS11189 Rev 5
2.24.6 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source.
2.25 Inter-integrated circuit interface (I2C)
Up to three I²C bus interfaces can operate in multimaster and slave modes. They can
support the standard (up to 100 KHz), and fast (up to 400 KHz) modes. They support the
7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC
generation/verification is embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
The devices also include programmable analog and digital noise filters (see Tabl e 7).
2.26 Universal synchronous/asynchronous receiver transmitters
(USART)
The devices embed four universal synchronous/asynchronous receiver transmitters
(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver
transmitters (UART4, UART5, UART7, and UART8).
These six interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to
communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate
at up to 5.62 bit/s.
USART1, USART2, USART3 and USART6 also provide hardware management of the CTS
and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication
capability. All interfaces can be served by the DMA controller.
Table 7. Comparison of I2C analog and digital filters
Filter Analog Digital
Pulse width of suppressed spikes 50 ns Programmable length from 1 to 15 I2C peripheral clocks
DS11189 Rev 5 41/219
STM32F469xx Functional overview
47
2.27 Serial peripheral interface (SPI)
The devices feature up to six SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 45 Mbits/s,
SPI2 and SPI3 can communicate at up to 22.5 Mbit/s. The 3-bit prescaler gives 8 master
mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the
DMA controller.
The SPI interface can be configured to operate in TI mode for communications in master
mode and slave mode.
2.28 Inter-integrated sound (I2S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be
operated in master or slave mode, in full duplex and simplex communication modes, and
can be configured to operate with a 16-/32-bit resolution as an input or output channel.
Table 8. USART feature comparison(1)
Name Standard
features
Modem
(RTS/CTS) LIN SPI
master irDA Smartcard
(ISO 7816)
Max. baud rate in Mbit/s
APB
mapping
Oversampling
by 16
Oversampling
by 8
USART1 X X X X X X 5.62 11.25
APB2
(max.
90 MHz)
USART2 X X X X X X 2.81 5.62
APB1
(max.
45 MHz)
USART3 X X X X X X 2.81 5.62
APB1
(max.
45 MHz)
UART4 X - X - X - 2.81 5.62
APB1
(max.
45 MHz)
UART5 X - X - X - 2.81 5.62
APB1
(max.
45 MHz)
USART6 X X X X X X 5.62 11.25
APB2
(max.
90 MHz)
UART7 X - X - X - 2.81 5.62
APB1
(max.
45 MHz)
UART8 X - X - X - 2.81 5.62
APB1
(max.
45 MHz)
1. X = feature supported.
Functional overview STM32F469xx
42/219 DS11189 Rev 5
Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of
the I2S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
All I2Sx can be served by the DMA controller.
Note: For I2S2 full-duplex mode, I2S2_CK and I2S2_WS signals can be used only on GPIO Port
B and GPIO Port D.
2.29 Serial Audio interface (SAI1)
The serial audio interface (SAI1) is based on two independent audio sub-blocks which can
operate as transmitter or receiver with their FIFO. Many audio protocols are supported by
each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both sub-blocks
can be configured in master or in slave mode.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of
the sampling frequency.
The two sub-blocks can be configured in synchronous mode when full-duplex mode is
required.
SAI1 can be served by the DMA controller.
2.30 Audio PLL (PLLI2S)
The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows
to achieve error-free I2S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change
without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the
I2S/SAI flow with an external PLL (or Codec output).
2.31 Audio and LCD PLL(PLLSAI)
An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the
PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or
11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.
The PLLSAI is also used to generate the LCD-TFT clock.
2.32 Secure digital input/output interface (SDIO)
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
DS11189 Rev 5 43/219
STM32F469xx Functional overview
47
The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital
protocol Rev1.1.
2.33 Ethernet MAC interface with dedicated DMA and IEEE 1588
support
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
The devices include the following features:
Supports 10 and 100 Mbit/s rates
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors (see the STM32F4xx reference manual for details)
Tagged MAC frame support (VLAN support)
Half-duplex (CSMA/CD) and full-duplex operation
MAC control sublayer (control frames) support
32-bit CRC generation and removal
Several address filtering modes for physical and multicast address (multicast and
group addresses)
32-bit status code for each transmitted or received frame
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
Triggers interrupt when system time becomes greater than target time
2.34 Controller area network (bxCAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for each CAN.
Functional overview STM32F469xx
44/219 DS11189 Rev 5
2.35 Universal serial bus on-the-go full-speed (OTG_FS)
The device embeds an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The major features are:
Combined Rx and Tx FIFO size of 1.28 KB with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints
12 host channels with periodic OUT support
Software configurable to OTG1.3 and OTG2.0 modes of operation
USB 2.0 LPM (Link Power Management) support
Internal FS OTG PHY support
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
2.36 Universal serial bus on-the-go high-speed (OTG_HS)
The device embeds a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral.
The USB OTG HS supports both full-speed and high-speed operations. It integrates the
transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI)
for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an
external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The major features are:
Combined Rx and Tx FIFO size of 4 KB with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
8 bidirectional endpoints
16 host channels with periodic OUT support
Software configurable to OTG1.3 and OTG2.0 modes of operation
USB 2.0 LPM (Link Power Management) support
Internal FS OTG PHY support
External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
Internal USB DMA
HNP/SNP/IP inside (no need for any external resistor)
for OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
DS11189 Rev 5 45/219
STM32F469xx Functional overview
47
2.37 Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication can be 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
Supports continuous mode or snapshot (a single frame) mode
Capability to automatically crop the image black & white.
2.38 Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
2.39 General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 90 MHz.
2.40 Analog-to-digital converters (ADCs)
Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16
external channels, performing conversions in the single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
Simultaneous sample and hold
Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.
Functional overview STM32F469xx
46/219 DS11189 Rev 5
2.41 Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the same input channel as VBAT
, ADC1_IN18, which is used to convert the
sensor output voltage into a digital value. When the temperature sensor and VBAT
conversion are enabled at the same time, only VBAT conversion is performed.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
2.42 Digital-to-analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
two DAC converters: one for each output channel
8-bit or 10-bit monotonic output
left or right data alignment in 12-bit mode
synchronized update capability
noise-wave generation
triangular-wave generation
dual DAC channel independent or simultaneous conversions
DMA capability for each channel
external triggers for conversion
input voltage reference VREF+
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.
2.43 Serial wire JTAG debug port (SWJ-DP)
The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
2.44 Embedded Trace Macrocell™
The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F46x through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
DS11189 Rev 5 47/219
STM32F469xx Functional overview
47
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer that runs the debugger software. TPA
hardware is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
Pinouts and pin description STM32F469xx
48/219 DS11189 Rev 5
3 Pinouts and pin description
Figure 13. STM32F46x LQFP100 pinout
1. The above figure shows the package top view.
069
/4)3
















3+
3&
3&
3&
3&
966$
95()
9''$
3$
3$
3$
3$
966
9''
3$
3+
1567
3&
3&
9''
3(
966
9%$7
3&
966











































































3$
3$
3%
3(
3(
3$
3%
3(
3(
3%
3%
3(
3(
9&$3
3%
3(
3(
966
3%
3%
3(
3%
9''
3%
3'
3&
'6,+267B'1
'6,+267B'3
9'''6,
'6,+267B&.1
'6,+267B&.3
966'6,
'6,+267B'1
'6,+267B'3
9&$3'6,
9'''6,
3'
3'
3'
3'
3&
9''86%
3$
3$
3&
3$
3$
3$
3$
3&
9''
3%
3%
3%
3'
3%
%227
3%
3'
3'
3%
3%
3'
3&
3$
3'
3'
3&
3$
9''
3'
3'
3&
966
9&$3
DS11189 Rev 5 49/219
STM32F469xx Pinouts and pin description
83
Figure 14. STM32F46x LQFP144 pinout
1. The above figure shows the package top view.
069
/4)3
























3&
3&
3&
9''
966$
95()
9''$
3$
3$
3$
3$
966
9''
3$
3$
1567
3&
966
3)
3+
3)
3)
9''
3+










































































3$
3&
3%
3)
3)
3&
3%
9''
3*
3(
3%
3)
3(
966
3(
3)
3)
9''
3(
3(
3*
3(
3(
3(
3'
'6,+267B'3
'6,+267B&.1
'6,+267B&.3
966'6,
'6,+267B'1
'6,+267B'3
9&$3'6,
9'''6,
3'
3'
9''
966
3'
3'
3'
'6,+267B'1
9'''6,
3*
3*
3*
9''86%
3*
3*
3*
3*
3(
9''
3(
%227
3%
3'5B21
3(
3%
3*
3*
3%
3%
9''
3*
3'
3%
3%
3*
9''
3'
3%
966
3*
966
 3'
3'
3'
3'
3'
3&
3&
3&
3$
3$
9''
 966
 9&$3





3$
3$
3$
3$
3$


3&
3&


3&
3&
 3$




3%
3%
3'
3%




3%
9&$3
3%
9''


3(
3%

3$



3)
3)
3&
3&
3)
3(
9%$7
3&
3)
3(
3(
3(
Pinouts and pin description STM32F469xx
50/219 DS11189 Rev 5
Figure 15. STM32F46x WLCSP168 pinout
1. The above figure shows the package bottom view.
06Y9

3, 9'' 3( 3% 3% 9'' 3* 3' 966 3' 3$ 3,
3(
$
%
&
'
(
)
*
+
-
.
/
0
1
3
3, 966 3% 3% 966 3*9'' 3' 3&3, 3+
9%$7 3( 3, 3( 3% 3* 3' 3' 3& 3, 9'' 966
3& 3( 3, 3'5B
21 3* 3* 3' 3& 3$ 3+ 9&$3 3$
3& 3& 3( 3% 3* 3' 3' 3, 3+ 3$ 3$3$
966 3,3, 3( %227 3$ 3$ 3& 3& 3& 966 9''
86%
3) 9'' 3) 3, 3% 3& 3* 3* 3* 3* 3* 3*
3) 3) 3) 1567 3) 966 3* 3% 3'
'6,
+267
B'3
'6,
+267
B'1
966
'6,
9'' 966 3) 3& 3$3) 3* 3( 3'
'6,
+267
B'1
'6,
+267
B&.1
'6,
+267
B&.3
3+ 3+ 3) 3$3+ 3)3( 3%3%
'6,
+267
B'3
9''
'6,
9&$3
'6,
3& 966$ 3$3$3$3) 3( 3+ 3' 3' 3' 9''
'6,
9''$ 3+ 3+ 3$3) 3( 3( 3+ 3+ 3' 3' 966
3+ 966 3$3% 966 3( 3(9&$3 3+3% 3'
3%
9'' 3$3% 3% 9'' 3* 3( 3( 966 9'' 3+ 3%
DS11189 Rev 5 51/219
STM32F469xx Pinouts and pin description
83
Figure 16. STM32F46x UFBGA169 ballout
1. The above figure shows the package top view.
06Y9
3, 3$
$3, %227 3* 3&3* 3' 3$3( 3( 3$ 3$
3, 3,
%3( 3% 3' 3&3* 3' 3$,3, 3% 3$ 3,
3( 3+
&3( 3% 3' 3'3' 3' 3&
3'5B
21 3% 3, 3+
3( 3*
'3( 3% 3' 3+3% 3$ 9''9'' 3% 966 9&$3
3& 3*
(3, 9%$7 3* 3$3* 3$ 3&966 3, 3* 3*
3& 3*
)3, 966 9'' 3&3* 966 3&3) 9'' 3* 3*
3+
'6,
+267B
'1
*3+ 3) 966 9663( 9'' 3&3) 3& 9''
86%
'6,
+267B
'3
'6,B
+267
&.1
+1567 3) 3( 3+3( 3+ 3+
3) 3) 966'6,
'6,
+267B
&.3
3)
966
'6,
+267B
'1
966$ 3$ 966 3+966 3( 9669''$ 9'' 9''
'6,
'6,
+267B
'3
3$9''
'6,
.3$ 3% 3( 3+9'' 3( 9''3$ 3$ 966'6, 9&$3
'6,
3+ 3'
/3+ 3% 3( 9''9'' 3( 3'3+ 3) 3' 3'
3& 3%
13$ 3) 3( 9&$33* 3% 3%3$ 3% 3% 3%
3& 3'
03+ 3) 3* 9663) 3% 3'3$ 3) 3' 3'
-

Pinouts and pin description STM32F469xx
52/219 DS11189 Rev 5
Figure 17. STM32F46x UFBGA176 ballout
1. The above figure shows the package top view.
069
  
$3(3(
3( 3 ( 3 % 3% 3* 3* 3% 3% 3' 3& 3$ 3$ 3$
%3(3(
3( 3% 3% 3% 3* 3* 3* 3* 3' 3' 3& 3& 3$
&9%$7 3, 3, 3, 3'5
B21 3* 3' 3' 3, 1&
'3& 3, 3, 3, %227 966 966 966 3' 3' 3' 3, 3$
(3& 3 ) 3, 3,
'6,
+267B
'3
3, 3$
)3&
966 9'' 3+ 9 66 9&$3 3 & 3$
*3+ 966 9'' 3+ 966 9'' 3& 3&
+3+ 3) 3) 3+ 966
'6,
9''B
86% 3* 3&
-1567 3) 3+ 3* 3*
.3) 3)
3)
9'' 966 3* 3* 3*
/3) %<3$66
B5(* 3*
0966$3&
3)
3& 3 & 3 & 3% 3* 9&$3
B 3+ 3'
195() 3$ 3$ 3& 3) 3 * 9 '' 9 '' 9 '' 3 + 3 ' 3 ' 3 '
33 $ 3$ 3 $ 3& 3) 3) 3( 3( 3( 3%  3% 3' 3'
53$ 3% 3) 3( 3( 3 % 3 %  3 % 
966

3$
9''
'6,
'6,
+267B
'1
9''
'6,
9&$3
'6,
'6,
+267B
&.3
'6,
+267B
'3
'6,
+267B
'1
'6,
+267B
&.1
9''
9'' 9'' 9''
95()
9''$ 3$3% 3) 3(
966 966 966 966
966966966 966 966
966966966 966 966
966966966 966 966
966966966 966 966
966 966
3)
3)
3'
3'
9'' 3$
3(
3(
3( 3%
DS11189 Rev 5 53/219
STM32F469xx Pinouts and pin description
83
Figure 18. STM32F46x LQFP176 pinout
1. The above figure shows the package top view.
069
3'5B21
9''
3(
3(
3%
3%
%227
3%
3%
3%
3%
3%
3*
9''
966
3*
3*
3*
3*
3*
3*
3'
3'
9''
966
3'
3'
3'
3'
3'
3'
3&
3&
3&
3,
3,
3(
3$
3(
3$
3(
3(
3$
3(
3$
9%$7
3&
3,
3&
3&
3&
3&
3&
3)
9''86%
3)
966
3)
3*
3)
3*
3)
3*
3)
3*
3*
3*
3)
3*
3)
966'6,
3)
'6,+267B'1
3)
'6,+267B'3
3)
9'''6,
3+
'6,+267B&.1
3+
'6,+267B&.3
1567
966'6,
3&
'6,+267B'1
3&
'6,+267B'3
3&
9&$3'6,
3&
9'''6,
3'
3'
95()
9''
966
3$
3'
3$
3'
3$
3'
3$
%<3$66B5(*
9''
3$
3$
3$
3$
3&
3&
3%
3%
3%
3)
3)
966
3)
3)
3)
3*
3*
3(
3(
3(
3(
3(
3(
3(
3(
3(
3%
3%
9&$3B



























































































/4)3












































3$
3,
3$
3$
9''
966
3,
3,
3,








3+
3+
3+
3+
3%
3%
3%
3% 







3,
9''
966
9&$3
3$
3'
3'
3'
















3&
3,
3,
3,
966
3+
3+
9''
966
9''
9''
966$
9''$
9''
966
9''
9''
Pinouts and pin description STM32F469xx
54/219 DS11189 Rev 5
Figure 19. STM32F46x LQFP208 pinout
1. The above figure shows the package top view.
06Y9
/4)3
3,
3,
3,
3,
9''
3'5B21
966
3(
3(
3%
3%
%227
3%
3%
3%
3%
3%
3*
3.
3.
3.
3.
3.
9''
966
3*
3*
3*
3*
3*
3*
3-
3-
3-
3-
3'
3'
9''
966
3'
3'
3'
3'
3'
3'
3&
3&
3&
3$
3$
9''
3,




















































3(  3,
3(  3,
3(  3,
3(  3+
3(  3+
9%$7  3+
3,  9''
3&  966
3&  9&$3
3&   3$
3,  3$
3,   3$
3,   3$
966   3$
9''   3$
3)   3&
3)   3&
3)   3&
3,   3&
3,   9''86%
3,   966
3)   3*
3)   3*
3)   3*
966   3*
9''   3*
3)   3*
3)   3*
3)   966'6,
3)   '6,+267B'1
3)   '6,+267B'3
3+   9'''6,
3+   '6,+267B&.1
1567   '6,+267B&.3
3&   966'6,
3&   '6,+267B'1
3&   '6,+267B'3
3&  9&$3'6,
9''  9'''6,
966$  3'
95()  3'
9''$  9''
3$ 966
3$ 3'
3$ 3'
3+   3'
3+  3'
3+   3'
3+   3'
3$   3%
966   3%
9''   3%




















































3$
3$
3$
3$
3&
3&
9''
966
3%
3%
3%
3,
3-
3-
3-
3-
3-
3)
3)
966
9''
3)
3)
3)
3*
3*
3(
3(
3(
966
9''
3(
3(
3(
3(
3(
3(
3%
3%
9&$3
966
9''
3-
3+
3+
3+
3+
3+
3+
3+
9''
3%
DS11189 Rev 5 55/219
STM32F469xx Pinouts and pin description
83
Figure 20. STM32F46x TFBGA216 ballout
1. The above figure shows the package top view.
06Y9
   
$3* 3( 3( 3% 3% 3% 3% 3' 3& 3$ 3$ 3$
%3( 3( 3* 3% 3% 3% 3* 3* 3- 3- 3' 3' 3& 3& 3$
&9%$7 3, 3, 3. 3. 3. 3* 3* 3- 3' 3' 3, 3, 3$
'3& 3) 3, 3, 3, 3, 3. 3. 3* 3- 3' 3' 3+ 3, 3$
(3& 3) 3, 3, %227 9'' 9'' 9'' 9'' 9&$3 3+ 3+ 3, 3$
)3& 966 3, 9'' 3& 3$
*3+ 3) 3, 3, 9'' 3& 3&
+3+ 3, 3+ 966 3* 3&
-1567 3) 3+ 3+ 966 9'' 3* 3*
.3) 3) 3) 3+ 9'' 966 966 966 966 966 9'' 3' 3% 3'
/3) 3& %<3$66
5(* 3% 3' 3'
0966$ 3* 3' 3' 3* 3* 3- 3+
195() 3$ 3$ 3$ 3& 3) 3* 3- 3( 3' 3* 3* 3+ 3+ 3+
95() 3$ 3$ 3$ 3& 3) 3- 3) 3( 3( 3( 3% 3+ 3+ 3+
3$ 3$ 3% 3% 3- 3- 3( 3( 3( 3( 3( 3% 3% 3%
3)
3
59''$
9''
'6,
'6,
+267B
&.3
9'''
86%
966
'6,
9''
'6,
'6,
+267B
&.1
'6,
+267B
'3
3'5
21
9&$3
'6,
'6,
+267B
'1
'6,
+267B
'3
'6,
+267B
'1
3( 3( 3(
9''
9''
966
966
966
966 966 966 966 966
966
9''
3-3)
9'' 9'' 9'' 9&$3 3'
9''
3)
3)
3& 3& 3& 3% 3)
9''
966
3'
Pinouts and pin description STM32F469xx
56/219 DS11189 Rev 5
Table 9. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin type
S Supply pin
I Input only pin
I/O Input / output pin
I/O structure
FT 5 V tolerant I/O
TTa 3.3 V tolerant I/O directly connected to analog parts
B Dedicated BOOT0 pin
RST Bidirectional reset pin with weak pull-up resistor
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
functions Functions selected through GPIOx_AFR registers
Additional
functions Functions directly selected/enabled through peripheral registers
DS11189 Rev 5 57/219
STM32F469xx Pinouts and pin description
83
Table 10. STM32F469xx pin and ball definitions
Pin number
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
1 144 B2 F9 A2 1 1 A3 PE2 I/O FT -
TRACECLK, SPI4_SCK,
SAI1_MCLK_A,
QUADSPI_BK1_IO2,
ETH_MII_TXD3, FMC_A23,
EVENTOUT
-
NC
(2) 1 C1 E10 A1 2 2 A2 PE3 I/O FT - TRACED0, SAI1_SD_B,
FMC_A19, EVENTOUT -
NC
(2) 2 C2 C11 B1 3 3 A1 PE4 I/O FT -
TRACED1, SPI4_NSS,
SAI1_FS_A, FMC_A20,
DCMI_D4, LCD_B0,
EVENTOUT
-
NC
(2) 3 D1 B12 B2 4 4 B1 PE5 I/O FT -
TRACED2, TIM9_CH1,
SPI4_MISO, SAI1_SCK_A,
FMC_A21, DCMI_D6,
LCD_G0, EVENTOUT
-
NC
(2) 4 D2 D11 B3 5 5 B2 PE6 I/O FT -
TRACED3, TIM9_CH2,
SPI4_MOSI, SAI1_SD_A,
FMC_A22, DCMI_D7,
LCD_G1, EVENTOUT
-
2------G6 VSS S-- - -
-------F5 VDD S-- - -
3 5 E5 C12 C1 6 6 C1 VBAT S - - - -
- - - - D2 7 7 C2 PI8 I/O FT
(3)
(4) EVENTOUT
RTC_TAMP1/
RTC_TAMP2/
RTC_TS
4 6G4D12D18 8D1 PC13 I/OFT
(3)
(4) EVENTOUT
RTC_TAMP1/
RTC_TS/
RTC_OUT
5 7 E1 E11 E1 9 9 E1 PC14-OSC32_IN
(PC14) I/O FT
(3)
(4) EVENTOUT OSC32_IN
68F1E12F11010F1
PC15-
OSC32_OUT
(PC15)
I/O FT
(3)
(4) EVENTOUT OSC32_OUT
-------G5 VDD S-- - -
- - E2 G9 D3 11 11 E4 PI9 I/O FT CAN1_RX, FMC_D30,
LCD_VSYNC, EVENTOUT -
- - E4 F10 E3 12 12 D5 PI10 I/O FT
ETH_MII_RX_ER,
FMC_D31, LCD_HSYNC,
EVENTOUT
-
- - F2 F11 E4 13 13 F3 PI11 I/O FT
LCD_G6,
OTG_HS_ULPI_DIR,
EVENTOUT
-
- - F5 F12 F2 14 14 F2 VSS S - - - -
--F4G11F31515F4 VDD S-- - -
Pinouts and pin description STM32F469xx
58/219 DS11189 Rev 5
- 9 F3 G10 E2 16 16 D2 PF0 I/O FT I2C2_SDA, FMC_A0,
EVENTOUT -
- 10 G3 H10 H3 17 17 E2 PF1 I/O FT I2C2_SCL, FMC_A1,
EVENTOUT -
- 11 G5 G12 H2 18 18 G2 PF2 I/O FT I2C2_SMBA, FMC_A2,
EVENTOUT -
- - - - - - 19 E3 PI12 I/O FT LCD_HSYNC, EVENTOUT -
- - - - - - 20 G3 PI13 I/O FT LCD_VSYNC, EVENTOUT -
- - - - - - 21 H3 PI14 I/O FT LCD_CLK, EVENTOUT -
- 12 H4 H11 J2 19 22 H2 PF3 I/O FT (5) FMC_A3, EVENTOUT ADC3_IN9
- 13 L4 J10 J3 20 23 J2 PF4 I/O FT (5) FMC_A4, EVENTOUT ADC3_IN14
- 14 H3 H12 K3 21 24 K3 PF5 I/O FT (5) FMC_A5, EVENTOUT ADC3_IN15
7 15 G7 J11 G2 22 25 H6 VSS S - - - -
8 16 G8 J12 G3 23 26 H5 VDD S - - - -
- - - - K2 24 27 K2 PF6 I/O FT (5)
TIM10_CH1, SPI5_NSS,
SAI1_SD_B, UART7_Rx,
QUADSPI_BK1_IO3,
EVENTOUT
ADC3_IN4
- - - - K1 25 28 K1 PF7 I/O FT (5)
TIM11_CH1, SPI5_SCK,
SAI1_MCLK_B, UART7_Tx,
QUADSPI_BK1_IO2,
EVENTOUT
ADC3_IN5
- - - - L3 26 29 L3 PF8 I/O FT (5)
SPI5_MISO, SAI1_SCK_B,
TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
ADC3_IN6
- - - - L2 27 30 L2 PF9 I/O FT (5)
SPI5_MOSI, SAI1_FS_B,
TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
ADC3_IN7
- 17 H1 K10 L1 28 31 L1 PF10 I/O FT (5)
QUADSPI_CLK,
DCMI_D11, LCD_DE,
EVENTOUT
ADC3_IN8
9 18 G2 K11 G1 29 32 G1 PH0-OSC_IN
(PH0) I/O FT - EVENTOUT OSC_IN
10 19 G1 K12 H1 30 33 H1 PH1-OSC_OUT
(PH1) I/O FT - EVENTOUT OSC_OUT
11 20 H2 H9 J1 31 34 J1 NRST I/O RST -
12 21 M1 J9 M2 32 35 M2 PC0 I/O FT (5)
OTG_HS_ULPI_STP,
FMC_SDNWE, LCD_R5,
EVENTOUT
ADC123_
IN10
Table 10. STM32F469xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
DS11189 Rev 5 59/219
STM32F469xx Pinouts and pin description
83
13 22 N1 L12 M3 33 36 M3 PC1 I/O FT (5)
TRACED0,
SPI2_MOSI/I2S2_SD,
SAI1_SD_A, ETH_MDC,
EVENTOUT
ADC123_
IN11
14 23 - - M4 34 37 M4 PC2 I/O FT (5)
SPI2_MISO, I2S2ext_SD,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2,
FMC_SDNE0, EVENTOUT
ADC123_
IN12
15 24 - - M5 35 38 L4 PC3 I/O FT (5)
SPI2_MOSI/I2S2_SD,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0,
EVENTOUT
ADC123_
IN13
- 25 - - - 36 39 J5 VDD S - - - -
-------J6 VSS S-- - -
16 26 J2 L11 M1 37 40 M1 VSSA S - - - -
----N1--N1 VREF- S-- - -
17 27 - - P1 38 41 P1 VREF+ S - - - -
18 28 J3 M12 R1 39 42 R1 VDDA S - - - -
19 29 J5 L10 N3 40 43 N3 PA0-WKUP(PA0) I/O FT (6)
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
USART2_CTS, UART4_TX,
ETH_MII_CRS,
EVENTOUT
ADC123_IN0,
WKUP
20 30 K1 K9 N2 41 44 N2 PA1 I/O FT (5)
TIM2_CH2, TIM5_CH2,
USART2_RTS, UART4_RX,
QUADSPI_BK1_IO3,
ETH_MII_RX_CLK/ETH_R
MII_REF_CLK, LCD_R2,
EVENTOUT
ADC123_IN1
21 31 K2 L9 P2 42 45 P2 PA2 I/O FT (5)
TIM2_CH3, TIM5_CH3,
TIM9_CH1, USART2_TX,
ETH_MDIO, LCD_R1,
EVENTOUT
ADC123_IN2
- - L2 M11 F4 43 46 K4 PH2 I/O FT -
QUADSPI_BK2_IO0,
ETH_MII_CRS,
FMC_SDCKE0, LCD_R0,
EVENTOUT
-
- - L1 N12 G4 44 47 J4 PH3 I/O FT -
QUADSPI_BK2_IO1,
ETH_MII_COL,
FMC_SDNE0, LCD_R1,
EVENTOUT
-
- - M2 M10 H4 45 48 H4 PH4 I/O FT -
I2C2_SCL, LCD_G5,
OTG_HS_ULPI_NXT,
LCD_G4, EVENTOUT
-
Table 10. STM32F469xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
Pinouts and pin description STM32F469xx
60/219 DS11189 Rev 5
- - L3 K8 J4 46 49 J3 PH5 I/O FT - I2C2_SDA, SPI5_NSS,
FMC_SDNWE, EVENTOUT -
22 32 K3 N10 R2 47 50 R2 PA3 I/O FT (5)
TIM2_CH4, TIM5_CH4,
TIM9_CH2, USART2_RX,
LCD_B2,
OTG_HS_ULPI_D0,
ETH_MII_COL, LCD_B5,
EVENTOUT
ADC123_IN3
23 33 J1 N11 - - 51 K6 VSS S - - - -
- - - - L4 48 - L5 BYPASS_REG I FT - - -
24 34 J4 P12 K4 49 52 K5 VDD S - - - -
25 35 N2 M9 N4 50 53 N4 PA4 I/O TTa -
SPI1_NSS,
SPI3_NSS/I2S3_WS,
USART2_CK,
OTG_HS_SOF,
DCMI_HSYNC,
LCD_VSYNC, EVENTOUT
ADC12_IN4,
DAC_OUT1
26 36 M3 L8 P4 51 54 P4 PA5 I/O TTa -
TIM2_CH1/TIM2_ETR,
TIM8_CH1N, SPI1_SCK,
OTG_HS_ULPI_CK,
LCD_R4, EVENTOUT
ADC12_IN5,
DAC_OUT2
27 37 N3 P11 P3 52 55 P3 PA6 I/O FT (5)
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN, SPI1_MISO,
TIM13_CH1,
DCMI_PIXCLK, LCD_G2,
EVENTOUT
ADC12_IN6
28 38 K4 J8 R3 53 56 R3 PA7 I/O FT (5)
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N, SPI1_MOSI,
TIM14_CH1,
QUADSPI_CLK,
ETH_MII_RX_DV/ETH_RMI
I_CRS_DV, FMC_SDNWE,
EVENTOUT
ADC12_IN7
NC
(2) 39 - - N5 54 57 N5 PC4 I/O FT (5)
ETH_MII_RXD0/ETH_RMII
_RXD0, FMC_SDNE0,
EVENTOUT
ADC12_IN14
NC
(2) 40 - - P5 55 58 P5 PC5 I/O FT (5)
ETH_MII_RXD1/ETH_RMII
_RXD1, FMC_SDCKE0,
EVENTOUT
ADC12_IN15
------59L7 VDD S-- - -
------60L6 VSS S-- - -
29 41 N4 P10 R5 56 61 R5 PB0 I/O FT (5)
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N, LCD_R3,
OTG_HS_ULPI_D1,
ETH_MII_RXD2, LCD_G1,
EVENTOUT
ADC12_IN8
Table 10. STM32F469xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
DS11189 Rev 5 61/219
STM32F469xx Pinouts and pin description
83
30 42 K5 N9 R4 57 62 R4 PB1 I/O FT (5)
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N, LCD_R6,
OTG_HS_ULPI_D2,
ETH_MII_RXD3, LCD_G0,
EVENTOUT
ADC12_IN9
31 43 L5 P9 M6 58 63 M5 PB2-
BOOT1(PB2) I/O FT - EVENTOUT -
- - - - - - 64 G4 PI15 I/O FT - LCD_G2, LCD_R0,
EVENTOUT -
------65R6 PJ0 I/OFT- LCD_R7, LCD_R1,
EVENTOUT -
- - - - - - 66 R7 PJ1 I/O FT - LCD_R2, EVENTOUT -
------67P7 PJ2 I/OFT-
DSIHOST_TE, LCD_R3,
EVENTOUT -
- - - - - - 68 N8 PJ3 I/O FT - LCD_R4, EVENTOUT -
- - - - - - 69 M9 PJ4 I/O FT - LCD_R5, EVENTOUT -
- 44M5K7R65970P8 PF11 I/OFT -
SPI5_MOSI,
FMC_SDNRAS,
DCMI_D12, EVENTOUT
-
- 45 N5 M8 P6 60 71 M6 PF12 I/O FT - FMC_A6, EVENTOUT -
- - J6 N8 M8 61 72 K7 VSS S - - - -
- 46K6P8N86273L8 VDD S - - - -
- 47M4J7N66374N6 PF13 I/OFT - FMC_A7, EVENTOUT -
- 48H5L7R76475P6 PF14 I/OFT - FMC_A8, EVENTOUT -
- 49M6H8P76576M8 PF15 I/OFT - FMC_A9, EVENTOUT -
- 50N6J6N76677N7 PG0 I/OFT - FMC_A10, EVENTOUT -
- 51M7P7M76778M7 PG1 I/OFT - FMC_A11, EVENTOUT -
32 52 N7 N7 R8 68 79 R8 PE7 I/O FT -
TIM1_ETR, UART7_Rx,
QUADSPI_BK2_IO0,
FMC_D4, EVENTOUT
-
33 53 G6 M7 P8 69 80 N9 PE8 I/O FT -
TIM1_CH1N, UART7_Tx,
QUADSPI_BK2_IO1,
FMC_D5, EVENTOUT
-
34 54 H6 K6 P9 70 81 P9 PE9 I/O FT -
TIM1_CH1,
QUADSPI_BK2_IO2,
FMC_D6, EVENTOUT
-
- 55 J7 - M9 71 82 K8 VSS S - - - -
- 56 L6 - N9 72 83 L9 VDD S - - - -
35 57 H7 P6 R9 73 84 R9 PE10 I/O FT -
TIM1_CH2N,
QUADSPI_BK2_IO3,
FMC_D7, EVENTOUT
-
Table 10. STM32F469xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
Pinouts and pin description STM32F469xx
62/219 DS11189 Rev 5
36 58 K7 N6 P10 74 85 P10 PE11 I/O FT -
TIM1_CH2, SPI4_NSS,
FMC_D8, LCD_G3,
EVENTOUT
-
37 59 L7 M6 R10 75 86 R10 PE12 I/O FT -
TIM1_CH3N, SPI4_SCK,
FMC_D9, LCD_B4,
EVENTOUT
-
38 60 J8 L6 N11 76 87 R12 PE13 I/O FT -
TIM1_CH3, SPI4_MISO,
FMC_D10, LCD_DE,
EVENTOUT
-
39 61 K8 J5 P11 77 88 P11 PE14 I/O FT -
TIM1_CH4, SPI4_MOSI,
FMC_D11, LCD_CLK,
EVENTOUT
-
40 62 L8 P5 R11 78 89 R11 PE15 I/O FT - TIM1_BKIN, FMC_D12,
LCD_R7, EVENTOUT -
41 63 M8 N5 R12 79 90 P12 PB10 I/O FT -
TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
USART3_TX,
QUADSPI_BK1_NCS,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER, LCD_G4,
EVENTOUT
-
42 64 N8 K5 R13 80 91 R13 PB11 I/O FT -
TIM2_CH4, I2C2_SDA,
USART3_RX,
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_RMI
I_TX_EN, DSIHOST_TE,
LCD_G5, EVENTOUT
-
43 65 N9 N4 M10 81 92 L11 VCAP1 S - - - -
44 - M9 P4 - - 93 K9 VSS S - - - -
45 66 L9 P3 N10 82 94 L10 VDD S - - - -
- - - - - - 95 M14 PJ5 I/O FT - LCD_R6, EVENTOUT -
- - - - M11 83 96 P13 PH6 I/O FT -
I2C2_SMBA, SPI5_SCK,
TIM12_CH1,
ETH_MII_RXD2,
FMC_SDNE1, DCMI_D8,
EVENTOUT
-
- - - - N12 84 97 N13 PH7 I/O FT -
I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3,
FMC_SDCKE1, DCMI_D9,
EVENTOUT
-
- - H8 M5 - - 98 P14 PH8 I/O FT -
I2C3_SDA, FMC_D16,
DCMI_HSYNC, LCD_R2,
EVENTOUT
-
- - H9 L5 - - 99 N14 PH9 I/O FT -
I2C3_SMBA, TIM12_CH2,
FMC_D17, DCMI_D0,
LCD_R3, EVENTOUT
-
Table 10. STM32F469xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
DS11189 Rev 5 63/219
STM32F469xx Pinouts and pin description
83
- - J9 M4 - - 100 P15 PH10 I/O FT -
TIM5_CH1, FMC_D18,
DCMI_D1, LCD_R4,
EVENTOUT
-
- - K9 N3 - - 101 N15 PH11 I/O FT -
TIM5_CH2, FMC_D19,
DCMI_D2, LCD_R5,
EVENTOUT
-
- - H10 P2 - - 102 M15 PH12 I/O FT -
TIM5_CH3, FMC_D20,
DCMI_D3, LCD_R6,
EVENTOUT
-
---H7---K10 VSS S-- - -
-66----103K11 VDD S-- - -
46 67 N10 H5 P12 85 104 L13 PB12 I/O FT -
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
USART3_CK, CAN2_RX,
OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_RMII
_TXD0, OTG_HS_ID,
EVENTOUT
-
47 68 N11 K4 P13 86 105 K14 PB13 I/O FT -
TIM1_CH1N,
SPI2_SCK/I2S2_CK,
USART3_CTS, CAN2_TX,
OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_RMII
_TXD1, EVENTOUT
OTG_HS_
VBUS
48 69 N12 P1 R14 87 106 R14 PB14 I/O FT -
TIM1_CH2N, TIM8_CH2N,
SPI2_MISO, I2S2ext_SD,
USART3_RTS,
TIM12_CH1, OTG_HS_DM,
EVENTOUT
-
49 70 N13 N2 R15 88 107 R15 PB15 I/O FT -
RTC_REFIN, TIM1_CH3N,
TIM8_CH3N,
SPI2_MOSI/I2S2_SD,
TIM12_CH2, OTG_HS_DP,
EVENTOUT
-
50 71 L10 L4 P15 89 108 L15 PD8 I/O FT - USART3_TX, FMC_D13,
EVENTOUT -
51 72 M10 N1 P14 90 109 L14 PD9 I/O FT - USART3_RX, FMC_D14,
EVENTOUT -
52 73 L11 M3 N15 91 110 K15 PD10 I/O FT - USART3_CK, FMC_D15,
LCD_B3, EVENTOUT -
- 74 M11 J4 N14 92 111 N10 PD11 I/O FT -
USART3_CTS,
QUADSPI_BK1_IO0,
FMC_A16/FMC_CLE,
EVENTOUT
-
Table 10. STM32F469xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
Pinouts and pin description STM32F469xx
64/219 DS11189 Rev 5
- 75 M13 M2 N13 93 112 M10 PD12 I/O FT -
TIM4_CH1, USART3_RTS,
QUADSPI_BK1_IO1,
FMC_A17/FMC_ALE,
EVENTOUT
-
- - M12 H4 M15 94 113 M11 PD13 I/O FT -
TIM4_CH2,
QUADSPI_BK1_IO3,
FMC_A18, EVENTOUT
-
- 76 J10 M1 - 95 114 J10 VSS S - - - -
- 77 K10 - J13 96 115 J11 VDD S - - - -
53 78 L12 L3 M14 97 116 L12 PD14 I/O FT - TIM4_CH3, FMC_D0,
EVENTOUT -
54 79 L13 L2 L14 98 117 K13 PD15 I/O FT - TIM4_CH4, FMC_D1,
EVENTOUT -
55 80 K13 L1 J12 99 118 H11 VDDDSI S - - - -
-------H10 VSS S-- - -
56 81 K12 K1 K12 100 119 K12 VCAPDSI S - - - -
- - - K2 D13 - - G13 VDD12DSI S - - - -
57 82 J12 K3 M12 101 120 J12 DSIHOST_D0P I/O - - - -
58 83 J13 J3 M13 102 121 J13 DSIHOST_D0N I/O - - - -
59 84 K11 H1 H12 103 122 G12 VSSDSI S - - - -
60 85 H12 J1 L12 104 123 H12 DSIHOST_CKP I/O -