M24C64-(W,R,F,DF) Datasheet

STMicroelectronics

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Datasheet

This is information on a product in full production.
March 2018 DS6638 Rev 36 1/54
M24C64-W M24C64-R
M24C64-F M24C64-DF
64-Kbit serial I²C bus EEPROM
Datasheet - production data
Features
Compatible with all I2C bus modes:
–1 MHz
400 kHz
100 kHz
Memory array:
64 Kbit (8 Kbyte) of EEPROM
Page size: 32 byte
Additional Write lockable page (M24C64-D
order codes)
Single supply voltage:
1.7 V to 5.5 V over –40 °C / +85 °C
1.6 V to 5.5 V over 0 °C / +85 °C
Write:
Byte Write within 5 ms
Page Write within 5 ms
Random and sequential Read modes
Write protect of the whole memory array
Enhanced ESD/Latch-Up protection
More than 4 million Write cycles
More than 200-years data retention
Packages
PDIP8 ECOPACK2®
SO8 ECOPACK2®
TSSOP8 ECOPACK2®
UFDFPN ECOPACK2®
WLCSP ECOPACK2®
Unsawn wafer (each die is tested)
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
UFDFPN8 (MC)
DFN8 - 2x3 mm
WLCSP (CS)
Thin WLCSP (CT)
UFDFPN5 (MH)
DFN5 -1.7x1.4 mm
PDIP8 (BN)
WLCSP
(CU) Unsawn wafer
www.st.com
Contents M24C64-W M24C64-R M24C64-F M24C64-DF
2/54 DS6638 Rev 36
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.3 Write Identification Page (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . 18
5.1.4 Lock Identification Page (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . 18
5.1.5 ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 18
5.1.6 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19
5.2 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2.1 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DS6638 Rev 36 3/54
M24C64-W M24C64-R M24C64-F M24C64-DF Contents
3
5.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3 Read Identification Page (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . . 21
5.4 Read the lock status (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.1 UFDFPN5 (DFN5) package information . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.2 UFDFPN8 (DFN8) package information . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.3 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.4 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.5 PDIP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.6 WLCSP4 ultra thin package information . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.7 WLCSP5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.8 WLCSP8 thin package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
List of tables M24C64-W M24C64-R M24C64-F M24C64-DF
4/54 DS6638 Rev 36
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. WLCSP 4-bump signals vs. bump position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. WLCSP 5-bump signals vs. bump position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. WLCSP 8-bump signals vs bump position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 13. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 14. Cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 15. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. DC characteristics (M24C64-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 17. DC characteristics (M24C64-R device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 18. DC characteristics (M24C64-F, M24C64-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . . 29
Table 19. 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 20. 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 21. UFDFPN5 - 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch
dual flat package, no lead - package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 22. UFDFPN8 – 2x3 mm, 0.55 thickness, ultra thin fine pitch dual flat package,
no lead - package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 23. TSSOP8 – 3 x 4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 24. SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 25. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data. . . . . . . . . . . . 40
Table 26. Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip
scale package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 27. WLCSP- 5-bump, 0.959 x 1.073 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 28. Thin WLCSP- 8-bump, 1.073 x 0.959 mm, wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 29. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 30. Ordering information scheme (unsawn wafer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 31. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
DS6638 Rev 36 5/54
M24C64-W M24C64-R M24C64-F M24C64-DF List of figures
5
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. UFDFPN5 (DFN5) package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. WLCSP 4 bump ultra thin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. WLCSP 5-bump connections (M24C64-FCS6TP/K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. WLCSP 8-bump thin connections (M24C64-DFCT6TP/K) . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Chip enable inputs connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. Maximum Rbus value versus bus parasitic capacitance (Cbus) for
an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16. Maximum Rbus value versus bus parasitic capacitance Cbus) for
an I2C bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 17. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 18. UFDFPN5 – 1.7x1.4 mm, 0.55 mm thickness, ultra thin fine pitch
dual flat package, no lead - package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 19. UFDFPN5 - 5-lead, 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch
dual flat package, no lead recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 20. UFDFPN8 – 2x3 mm, 0.55 thickness, ultra thin fine pitch
dual flat package, no lead - package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 21. TSSOP8 – 3x4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 22. SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package outline . 38
Figure 23. SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width,
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 24. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . . 40
Figure 25. Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm,wafer level chip
scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 26. Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 27. WLCSP 5-bump, 0.959 x 1.073 mm, 0.4 mm pitch wafer level chip scale
(M24C64-FCS6TP/K)- package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 28. WLCSP - 5-bump, 0.959 x 1.073 mm, 0.4 mm pitch wafer level chip scale
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 29. Thin WLCSP- 8-bump, 1.073 x 0.959 mm, wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 30. Thin WLCSP- 8-bump, 1.073 x 0.959 mm, wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Description M24C64-W M24C64-R M24C64-F M24C64-DF
6/54 DS6638 Rev 36
1 Description
The M24C64 is a 64-Kbit I2C-compatible EEPROM (Electrically Erasable PROgrammable
Memory) organized as 8 K × 8 bits.
Over an ambient temperature range of -40 °C / +85 °C, the M24C64-W can operate with a
supply voltage from 2.5 V to 5.5 V, the M24C64-R can operate with a supply voltage from
1.8 V to 5.5 V, and the M24C64-F and M24C64-DF can operate with a supply voltage from
1.7 V to 5.5 V ( the M24C64-F can also operate down to 1.6 V, under some restricting
conditions).
The M24C64-D offers an additional page, named the Identification Page (32 byte). The
Identification Page can be used to store sensitive application parameters which can be
(later) permanently locked in Read-only mode.
Figure 1. Logic diagram
Figure 2. 8-pin package connections, top view
1. See Section 9: Package information for package dimensions, and how to identify pin 1
Table 1. Signal names
Signal name Function Direction
E2, E1, E0 Chip Enable Input
SDA Serial Data I/O
SCL Serial Clock Input
WC Write Control Input
VCC Supply voltage -
VSS Ground -
$,I
(( 6'$
9&&
0[[[
:&
6&/
966
$,I
6'$966
6&/
:&(
( 9&&
(
DS6638 Rev 36 7/54
M24C64-W M24C64-R M24C64-F M24C64-DF Description
53
Figure 3. UFDFPN5 (DFN5) package connections
1. Inputs E2, E1, E0 are not connected, therefore read as (000). Please refer to Section 2.3 for further
explanations.
Figure 4. WLCSP 4 bump ultra thin package connections
1. Inputs E2, E1, E0 are read as (000). Please refer to Section 2.3 for further explanations.
Figure 5. WLCSP 5-bump connections (M24C64-FCS6TP/K)
1. Inputs E2, E1, E0 are internally connected to (001). Please refer to Section 2.3 for further explanations.
Table 2. WLCSP 4-bump signals vs. bump position
Position A B
1V
CC SCL
2V
SS SDA
069
6'$ 6&/
:&

9
&&
9
66
7RSYLHZ
PDUNLQJVLGH
%RWWRPYLHZ
SDGVVLGH
$%&'
;<=: 9
66
06Y9
0DUNLQJVLGH
WRSYLHZ
%XPSVLGH
ERWWRPYLHZ
9&& 966
6&/ 6'$
9&&
966
6&/6'$

$ $
% %
069
6'$
6&/ :&
%XPSVLGH
ERWWRPYLHZ
9&&
6'$
:& 6&/
0DUNLQJVLGH
WRSYLHZ
966 $
%
&
$
%
&

966 9&&
Description M24C64-W M24C64-R M24C64-F M24C64-DF
8/54 DS6638 Rev 36
Figure 6. WLCSP 8-bump thin connections (M24C64-DFCT6TP/K)
Table 3. WLCSP 5-bump signals vs. bump position
PositionABC
1V
CC -WC
2-SDA-
3V
SS -SCL
Table 4. WLCSP 8-bump signals vs bump position
PositionABC
1WC-SCL
2-SDA-
3V
CC -V
SS
4-E0-
5E1-E2
069
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DS6638 Rev 36 9/54
M24C64-W M24C64-R M24C64-F M24C64-DF Signal description
53
2 Signal description
2.1 Serial Clock (SCL)
The signal applied on the SCL input is used to strobe the data available on SDA(in) and to
output the data on SDA(out).
2.2 Serial Data (SDA)
SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an
open drain output that may be wire-OR’ed with other open drain or open collector signals on
the bus. A pull-up resistor must be connected from Serial Data (SDA) to VCC (Figure 15
indicates how to calculate the value of the pull-up resistor).
2.3 Chip Enable (E2, E1, E0)
(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code (see Table 5). These inputs must
be tied to VCC or VSS, as shown in Figure 7. When not connected (left floating), these inputs
are read as low (0).
For the 4-balls WLCSP package (see Figure 4), the (E2,E1,E0) inputs are internally
connected to (0, 0, 0).
For the 5-balls WLCSP package (see Figure 5), the (E2,E1,E0) inputs are internally
connected to (0,0,1).
Figure 7. Chip enable inputs connection
2.4 Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either
driven low or left floating.
When Write Control (WC) is driven high, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
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Signal description M24C64-W M24C64-R M24C64-F M24C64-DF
10/54 DS6638 Rev 36
2.5 VSS (ground)
VSS is the reference for the VCC supply voltage.
2.6 Supply voltage (VCC)
2.6.1 Operating supply voltage (VCC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions
in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually of the order of
10 nF to 100 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a write instruction, until the completion of the internal write cycle (tW).
2.6.2 Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
(see Operating conditions in Section 8: DC and AC parameters).
2.6.3 Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until VCC has reached the
internal reset threshold voltage. This threshold is lower than the minimum VCC operating
voltage (see Operating conditions in Section 8: DC and AC parameters). When VCC passes
over the POR threshold, the device is reset and enters the Standby Power mode; however,
the device must not be accessed until VCC reaches a valid and stable DC voltage within the
specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC
parameters).
In a similar way, during power-down (continuous decrease in VCC), the device must not be
accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset
threshold voltage, the device stops responding to any instruction sent to it.
2.6.4 Power-down conditions
During power-down (continuous decrease in VCC), the device must be in the Standby Power
mode (mode reached after decoding a Stop condition, assuming that there is no internal
write cycle in progress).
DS6638 Rev 36 11/54
M24C64-W M24C64-R M24C64-F M24C64-DF Memory organization
53
3 Memory organization
The memory is organized as shown below.
Figure 8. Block diagram
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12/54 DS6638 Rev 36
4 Device operation
The device supports the I2C protocol. This is summarized in Figure 9. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
Figure 9. I2C bus protocol
DS6638 Rev 36 13/54
M24C64-W M24C64-R M24C64-F M24C64-DF Device operation
53
4.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
4.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and
driven high. A Stop condition terminates communication between the device and the bus
master. A Read instruction that is followed by NoAck can be followed by a Stop condition to
force the device into the Standby mode.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
4.3 Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
4.4 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
Device operation M24C64-W M24C64-R M24C64-F M24C64-DF
14/54 DS6638 Rev 36
4.5 Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 5 (most significant bit first).
When the device select code is received, the device only responds if the Chip Enable
address is the same as the value on its Chip Enable E2,E1,E0 inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the device select code, the device deselects itself from the bus, and goes into Standby
mode.
Table 5. Device select code
Device type identifier(1)
1. The most significant bit, b7, is sent first.
Chip Enable address(2)
2. E0, E1 and E2 are compared with the value read on input pins E0, E1 and E2.
RW
b7 b6 b5 b4 b3 b2 b1 b0
Device select code
when addressing the
memory array
1010E2E1E0RW
Device select code
when accessing the
Identification page
1011E2E1E0RW
DS6638 Rev 36 15/54
M24C64-W M24C64-R M24C64-F M24C64-DF Instructions
53
5 Instructions
5.1 Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in Figure 10, and waits for two address
bytes. The device responds to each address byte with an acknowledge bit, and then waits
for the data byte.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle tW is triggered. A Stop condition at any other time slot does not trigger the internal
Write cycle.
After the Stop condition and the successful completion of an internal Write cycle (tW), the
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 11.
Table 6. Most significant address byte
A15 A14 A13 A12 A11 A10 A9 A8
Table 7. Least significant address byte
A7 A6 A5 A4 A3 A2 A1 A0
Instructions M24C64-W M24C64-R M24C64-F M24C64-DF
16/54 DS6638 Rev 36
5.1.1 Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 10.
Figure 10. Write mode sequences with WC = 0 (data write enabled)
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DS6638 Rev 36 17/54
M24C64-W M24C64-R M24C64-F M24C64-DF Instructions
53
5.1.2 Page Write
The Page Write mode allows up to 32 byte to be written in a single Write cycle, provided that
they are all located in the same page in the memory: that is, the most significant memory
address bits, A15/A5, are the same. If more bytes are sent than will fit up to the end of the
page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the same
page, from location 0.
The bus master sends from 1 to 32 byte of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck, as
shown in Figure 11. After each transferred byte, the internal page address counter is
incremented.
The transfer is terminated by the bus master generating a Stop condition.
Figure 11. Write mode sequences with WC = 1 (data write inhibited)
Instructions M24C64-W M24C64-R M24C64-F M24C64-DF
18/54 DS6638 Rev 36
5.1.3 Write Identification Page (M24C64-D only)
The Identification Page (32 byte) is an additional page which can be written and (later)
permanently locked in Read-only mode. It is written by issuing the Write Identification Page
instruction. This instruction uses the same protocol and format as Page Write (into memory
array), except for the following differences:
Device type identifier = 1011b
MSB address bits A15/A5 are don't care except for address bit A10 which must be ‘0’.
LSB address bits A4/A0 define the byte address inside the Identification page.
If the Identification page is locked, the data bytes transferred during the Write Identification
Page instruction are not acknowledged (NoAck).
5.1.4 Lock Identification Page (M24C64-D only)
The Lock Identification Page instruction (Lock ID) permanently locks the Identification page
in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions:
Device type identifier = 1011b
Address bit A10 must be ‘1’; all other address bits are don't care
The data byte must be equal to the binary value xxxx xx1x, where x is don't care
5.1.5 ECC (Error Correction Code) and Write cycling
The ECC is offered only in devices identified with process letter K, all other devices
(identified with a different process letter) do not embed the ECC logic.
The Error Correction Code (ECC) is an internal logic function which is transparent for the
I2C communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes(a). Inside a group, if a
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
other bytes located in the same group(a). As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the 4 bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined Table 14: Cycling performance.
a.A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.
DS6638 Rev 36 19/54
M24C64-W M24C64-R M24C64-F M24C64-DF Instructions
53
5.1.6 Minimizing Write delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in AC characteristics tables in Section 8: DC and AC parameters, but the typical time
is shorter. To make use of this, a polling sequence can be used by the bus master.
The sequence, as shown in Figure 12, is:
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 12. Write cycle polling flowchart using ACK
1. The seven most significant bits of the Device Select code of a Random Read (bottom right box in the figure) must be
identical to the seven most significant bits of the Device Select code of the Write (polling instruction in the figure).
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Instructions M24C64-W M24C64-R M24C64-F M24C64-DF
20/54 DS6638 Rev 36
5.2 Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device internal address counter is
incremented by one, to point to the next byte address.
For the Read instructions, after each byte read (data out), the device waits for an
acknowledgment (data in) during the 9th bit time. If the bus master does not acknowledge
during this 9th time, the device terminates the data transfer and switches to its Standby
mode.
Figure 13. Read mode sequences
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DS6638 Rev 36 21/54
M24C64-W M24C64-R M24C64-F M24C64-DF Instructions
53
5.2.1 Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 13) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the RW bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a Stop condition.
5.2.2 Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W bit set to 1. The device acknowledges this, and
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 13, without acknowledging the byte.
Note that the address counter value is defined by instructions accessing either the memory
or the Identification page. When accessing the Identification page, the address counter
value is loaded with the byte location in the Identification page, therefore the next Current
Address Read in the memory uses this new address counter value. When accessing the
memory, it is safer to always use the Random Address Read instruction (this instruction
loads the address counter with the byte location to read in the memory, see Section 5.2.1)
instead of the Current Address Read instruction.
5.2.3 Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 13.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter “rolls-over”, and the device continues to output data from memory address
00h.
5.3 Read Identification Page (M24C64-D only)
The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
The Identification Page can be read by issuing an Read Identification Page instruction. This
instruction uses the same protocol and format as the Random Address Read (from memory
array) with device type identifier defined as 1011b. The MSB address bits A15/A5 are don't
care, the LSB address bits A4/A0 define the byte address inside the Identification Page. The
number of bytes to read in the ID page must not exceed the page boundary (e.g.: when
reading the Identification Page from location 10d, the number of bytes should be less than
or equal to 22, as the ID page boundary is 32 bytes).
Instructions M24C64-W M24C64-R M24C64-F M24C64-DF
22/54 DS6638 Rev 36
5.4 Read the lock status (M24C64-D only)
The locked/unlocked status of the Identification page can be checked by transmitting a
specific truncated command [Identification Page Write instruction + one data byte] to the
device. The device returns an acknowledge bit if the Identification page is unlocked,
otherwise a NoAck bit if the Identification page is locked.
Right after this, it is recommended to transmit to the device a Start condition followed by a
Stop condition, so that:
Start: the truncated command is not executed because the Start condition resets the
device internal logic,
Stop: the device is then set back into Standby mode by the Stop condition.
DS6638 Rev 36 23/54
M24C64-W M24C64-R M24C64-F M24C64-DF Initial delivery state
53
6 Initial delivery state
The device is delivered with all the memory array bits and Identification page bits set to 1
(each byte contains FFh).
When delivered in unsawn wafer, all memory bits are set to 1 (each memory byte contains
FFh) except the last byte located at address 1FFFh which is written with the value 22h.
Maximum rating M24C64-W M24C64-R M24C64-F M24C64-DF
24/54 DS6638 Rev 36
7 Maximum rating
Stressing the device outside the ratings listed in Table 8 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 8. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
Ambient operating temperature -40 130 °C
TSTG Storage temperature –65 150 °C
TLEAD
Lead temperature during soldering see note(1)
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK2®
7191395 specification, and the European directive on Restrictions of Hazardous Substances (RoHS
directive 2011/65/EU of July 2011).
°C
PDIP-specific lead temperature during soldering - 260(2)
2. TLEAD max must not be applied for more than 10 s.
°C
IOL DC output current (SDA = 0) - 5 mA
VIO Input or output range –0.50 6.5 V
VCC Supply voltage –0.50 6.5 V
VESD Electrostatic pulse (Human Body model)(3)
3. Positive and negative pulses applied on different combinations of pin connections, according to AEC-
Q100-002 (compliant with ANSI/ESDA/JEDEC JS-001-2012 standard, C1=100 pF, R1=1500 Ω).
- 3000(4)
4. 4000 V for devices identified with process letter K and P.
V
DS6638 Rev 36 25/54
M24C64-W M24C64-R M24C64-F M24C64-DF DC and AC parameters
53
8 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
Table 9. Operating conditions (voltage range W)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 2.5 5.5 V
TAAmbient operating temperature –40 85 °C
fCOperating clock frequency - 1(1)
1. 400 kHz for devices identified by process letter P.
MHz
Table 10. Operating conditions (voltage range R)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 1.8 5.5 V
TAAmbient operating temperature –40 85 °C
fCOperating clock frequency - 1(1)
1. 400 kHz for devices identified by process letter P.
MHz
Table 11. Operating conditions (voltage range F)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 1.6(1)
1. Only for devices identified with process letter T
1.7 5.5 V
TA
Ambient operating temperature: READ -40 -40 85
°C
Ambient operating temperature: WRITE 0 -40 85
fC
Operating clock frequency, VCC 1.6 V(1) -400
kHz
Operating clock frequency, VCC 1.7 V - 1000
Table 12. AC measurement conditions
Symbol Parameter Min. Max. Unit
Cbus Load capacitance - 100 pF
-SCL input rise/fall time, SDA input fall time - 50 ns
-Input levels 0.2 VCC to 0.8 VCC V
-Input and output timing reference levels 0.3 VCC to 0.7 VCC V
DC and AC parameters M24C64-W M24C64-R M24C64-F M24C64-DF
26/54 DS6638 Rev 36
Figure 14. AC measurement I/O waveform
Table 13. Input parameters
Symbol Parameter(1)
1. Characterized only, not tested in production.
Test condition Min. Max. Unit
CIN Input capacitance (SDA) - - 8 pF
CIN Input capacitance (other pins) - - 6 pF
ZLInput impedance (E2, E1, E0, WC)(2)
2. input impedance when the memory is selected (after a Start condition).
VIN < 0.3 VCC 30 - kΩ
ZHVIN > 0.7 VCC 500 - kΩ
Table 14. Cycling performance
Symbol Parameter Test condition Max.(1)
1. Cycling performance for products identified by process letter K or T (previous products were specified with
1 million cycles at 25 °C)
Unit
Ncycle Write cycle
endurance(2)
2. The Write cycle endurance is defined by characterization and qualification. For devices embedding the
ECC functionality (see Chapter 5.1.5), the write cycle endurance is defined for group of four bytes located
at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where N is an integer.
TA 25 °C, VCC(min) < VCC < VCC(max) 4,000,000 Write cycle(3)
3. A Write cycle is executed when either a Page Write, a Byte write, a Write Identification Page or a Lock
Identification Page instruction is decoded. When using the Byte Write, the Page Write or the Write
Identification Page, refer also to Section 5.1.5: ECC (Error Correction Code) and Write cycling
TA = 85 °C, VCC(min) < VCC < VCC(max) 1,200,000
Table 15. Memory cell data retention
Parameter Test condition Min. Unit
Data retention(1)
1. The data retention behavior is checked in production, while the data retention limit defined in this table is
extracted from characterization and qualification results.
TA = 55 °C 200(2)
2. For products identified by process letter K or T (previous products were specified with a data retention of 40
years at 55°C).
Year
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DS6638 Rev 36 27/54
M24C64-W M24C64-R M24C64-F M24C64-DF DC and AC parameters
53
Table 16. DC characteristics (M24C64-W, device grade 6)
Symbol Parameter Test conditions (in addition to those
in Table 9)Min. Max. Unit
ILI
Input leakage current
(SCL, SDA, E2, E1,
E0)
VIN = VSS or VCC, device in Standby
mode 2µA
ILO
Output leakage
current
SDA in Hi-Z, external voltage applied
on SDA: VSS or VCC
2µA
ICC Supply current (Read)
2.5 V < VCC < 5.5 V, fc = 400 kHz
(rise/fall time < 50 ns) -2mA
2.5 V < VCC < 5.5 V, fc = 1 MHz(1)
(rise/fall time < 50 ns)
1. For devices identified with process letter K or T.
-2.5mA
ICC0 Supply current (Write) During tW,
2.5 V VCC 5.5 V -2.5
(2)
2. Characterized value, not tested in production.
mA
ICC1
Standby supply
current
Device not selected(3),
VIN = VSS or VCC, VCC = 2.5 V
3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
-2µA
Device not selected(3),
VIN = VSS or VCC, VCC = 5.5 V -3
(4)
4. Previous products (identified with process letter P) offer ICC1(max) = 5 μA
µA
VIL
Input low voltage
(SCL, SDA, WC, E2,
E1, E0)(5)
5. Ei inputs should be tied to Vss (see Section 2.3).
- –0.45 0.3 VCC V
VIH
Input high voltage
(SCL, SDA) -0.7 V
CC 6.5 V
Input high voltage
(WC, E2, E1, E0)(6)
6. Ei inputs should be tied to Vcc (see Section 2.3).
-0.7 V
CC VCC+0.6 V
VOL Output low voltage IOL = 2.1 mA, VCC = 2.5 V or
IOL = 3 mA, VCC = 5.5 V -0.4V
DC and AC parameters M24C64-W M24C64-R M24C64-F M24C64-DF
28/54 DS6638 Rev 36
Table 17. DC characteristics (M24C64-R device grade 6)
Symbol Parameter Test conditions(1) (in addition to
those in Table 10)
1. If the application uses the voltage range R device with 2.5 V < Vcc < 5.5 V and -40 °C < TA < +85 °C,
please refer to Table 16 instead of this table.
Min. Max. Unit
ILI
Input leakage current
(E0, E1, E2, SCL, SDA)
VIN = VSS or VCC, device in
Standby mode 2µA
ILO Output leakage current SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
2µA
ICC Supply current (Read)
VCC = 1.8 V, fc= 400 kHz - 0.8 mA
fc= 1 MHz(2)
2. Only for devices operating at fC max = 1 MHz (see note (1) in Table 20).
-2.5mA
ICC0 Supply current (Write)(3)
3. For devices identified with process letter K or T
During tW
1.8 V VCC 2.5 V -1.5
(4)
4. Characterized value, not tested in production.
mA
ICC1 Standby supply current Device not selected(5),
VIN = VSS or VCC, VCC = 1.8 V
5. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
-1µA
VIL
Input low voltage
(SCL, SDA)(6)
6. Ei inputs should be tied to Vss (see Section 2.3).
1.8 V VCC < 2.5 V –0.45 0.25 VCC V
VIH
Input high voltage
(SCL, SDA) 1.8 V VCC < 2.5 V 0.75 VCC 6.5 V
Input high voltage
(WC)(7)
7. Ei inputs should be tied to Vcc (see Section 2.3).
1.8 V VCC < 2.5 V 0.75 VCC VCC+ 0.6 V
VOL Output low voltage IOL = 1 mA, VCC = 1.8 V(8)
8. IOL = 0.7 mA for devices identified by process letter P.
-0.2V
DS6638 Rev 36 29/54
M24C64-W M24C64-R M24C64-F M24C64-DF DC and AC parameters
53
Table 18. DC characteristics (M24C64-F, M24C64-DF, device grade 6)
Symbol Parameter Test conditions(1) (in addition to
those in Table 11)
1. If the application uses the voltage range F device with 2.5 V < VCC < 5.5 V and -40 °C < TA < +85 °C,
please refer to Table 16 instead of this table.
Min. Max. Unit
ILI
Input leakage current
(E1, E2, SCL, SDA)
VIN = VSS or VCC
device in Standby mode 2µA
ILO Output leakage current SDA in Hi-Z, external voltage applied
on SDA: VSS or VCC
2µA
ICC Supply current (Read)
VCC = 1.6 V or 1.7 V, fC = 400 kHz - 0.8
mA
fC = 1 MHz(2)
2. Only for devices identified by process letter K or T (see Table 20).
-2.5
ICC0 Supply current (Write) During tW, VCC < 2.5 V - 1.5(3)
3. Characterized value, not tested in production.
mA
ICC1 Standby supply current
Device not selected(4),
VIN = VSS or VCC, VCC = 1.6 V or
1.7 V
4. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
-1µA
VIL
Input low voltage
(SCL, SDA, WC, Ei)(5)
5. Ei inputs should be tied to VSS(see Section 2.3).
VCC < 2.5 V –0.45 0.25 VCC V
VIH
Input high voltage
(SCL, SDA) VCC < 2.5 V 0.75 VCC 6.5
V
Input high voltage
(WC, E2, E1, E0)(6)
6. Ei inputs should be tied to VCC (see Section 2.3).
VCC < 2.5 V 0.75 VCC VCC+ 0.6
VOL Output low voltage IOL =1mA, VCC = 1.6 V or 1.7 V - 0.2 V
DC and AC parameters M24C64-W M24C64-R M24C64-F M24C64-DF
30/54 DS6638 Rev 36
Table 19. 400 kHz AC characteristics
Symbol Alt. Parameter Min. Max. Unit
fCfSCL Clock frequency - 400 kHz
tCHCL tHIGH Clock pulse width high 600 - ns
tCLCH tLOW Clock pulse width low 1300 - ns
tQL1QL2(1)
1. Characterized only, not tested in production.
tFSDA (out) fall time 20(2)
2. With CL = 10 pF.
300 ns
tXH1XH2 tRInput signal rise time (3)
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC < 400 kHz.
(3) ns
tXL1XL2 tFInput signal fall time (3) (3) ns
tDXCH tSU:DAT Data in set up time 100 - ns
tCLDX tHD:DAT Data in hold time 0 - ns
tCLQX(4)
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
tDH Data out hold time 50(5)
5. The previous products were specified with tCLQX longer than 50 ns. it should be noted that any tCLQX value
longer than 50ns offers a safe margin when compared to the I2C-bus specification recommendations.
-ns
tCLQV(6)
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 15.
tAA Clock low to next data valid (access time) - 900 ns
tCHDL tSU:STA Start condition setup time 600 - ns
tDLCL tHD:STA Start condition hold time 600 - ns
tCHDH tSU:STO Stop condition set up time 600 - ns
tDHDL tBUF
Time between Stop condition and next Start
condition 1300 - ns
tWLDL(7)(1)
7. WC=0 set up time condition to enable the execution of a WRITE command.
tSU:WC WC set up time (before the Start condition) 0 - µs
tDHWH(8)(1)
8. WC=0 hold time condition to enable the execution of a WRITE command.
tHD:WC WC hold time (after the Stop condition) 1 - µs
tWtWR Internal Write cycle duration - 5 ms
tNS(1) -Pulse width ignored (input filter on SCL and
SDA) - single glitch -50
(9)
9. The previous products were specified with tNS longer than 50ns. it should be noted that the tNS (max) =
50ns is the value defined by the I2C-bus specification.
ns
DS6638 Rev 36 31/54
M24C64-W M24C64-R M24C64-F M24C64-DF DC and AC parameters
53
Table 20. 1 MHz AC characteristics
Symbol Alt. Parameter(1)
1. Only for devices identified by the process letter K or T (devices qualified at 1 MHz).
Min. Max. Unit
fCfSCL Clock frequency 0 1 MHz
tCHCL tHIGH Clock pulse width high 260 - ns
tCLCH tLOW Clock pulse width low 500 - ns
tXH1XH2 tRInput signal rise time (2)
2. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be less than 120 ns when fC < 1 MHz.
(2) ns
tXL1XL2 tFInput signal fall time (2) (2) ns
tQL1QL2(3)
3. Characterized only, not tested in production.
tFSDA (out) fall time 20(4)
4. With CL = 10 pF.
120 ns
tDXCH tSU:DAT Data in setup time 50 - ns
tCLDX tHD:DAT Data in hold time 0 - ns
tCLQX(5)
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
tDH Data out hold time 50(6)
6. The previous products were specified with tCLQX longer than 50 ns. it should be noted that any tCLQX value
longer than 50ns offers a safe margin when compared to the I2C-bus specification recommendations.
-ns
tCLQV(7)
7. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 16.
tAA Clock low to next data valid (access time) - 450 ns
tCHDL tSU:STA Start condition setup time 250 - ns
tDLCL tHD:STA Start condition hold time 250 - ns
tCHDH tSU:STO Stop condition setup time 250 - ns
tDHDL tBUF
Time between Stop condition and next Start
condition 500 - ns
tWLDL(8)(3)
8. WC=0 set up time condition to enable the execution of a WRITE command.
tSU:WC WC set up time (before the Start condition) 0 - µs
tDHWH(9)(3)
9. WC=0 hold time condition to enable the execution of a WRITE command.
tHD:WC WC hold time (after the Stop condition) 1 - µs
tWtWR Write time - 5 ms
tNS(3) -Pulse width ignored (input filter on SCL and
SDA) -50
(10)
10. The previous products were specified with tNS longer than 50 ns. it should be noted that the I2C-bus
specification recommends a tNS value longer than 50ns.
ns
DC and AC parameters M24C64-W M24C64-R M24C64-F M24C64-DF
32/54 DS6638 Rev 36
Figure 15. Maximum Rbus value versus bus parasitic capacitance (Cbus) for
an I2C bus at maximum frequency fC = 400 kHz
Figure 16. Maximum Rbus value versus bus parasitic capacitance Cbus) for
an I2C bus at maximum frequency fC = 1MHz
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DS6638 Rev 36 33/54
M24C64-W M24C64-R M24C64-F M24C64-DF DC and AC parameters
53
Figure 17. AC waveforms
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Package information M24C64-W M24C64-R M24C64-F M24C64-DF
34/54 DS6638 Rev 36
9 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
For die information concerning the M24C64 delivered in unsawn wafer, please contact your
nearest ST Sales Office.
9.1 UFDFPN5 (DFN5) package information
Figure 18. UFDFPN5 – 1.7x1.4 mm, 0.55 mm thickness, ultra thin fine pitch
dual flat package, no lead - package outline
1. On the bottom side, pin 1 is identified by the specific pad shape and, on the top side, pin 1 is defined from
the orientation of the marking: when reading the marking, pin 1 is below the upper left package corner.
Table 21. UFDFPN5 - 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch
dual flat package, no lead - package mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A 0.500 0.550 0.600 0.0197 0.0217 0.0236
A1 0.000 - 0.050 0.0000 - 0.0020
b(2) 0.175 0.200 0.225 0.0069 0.0079 0.0089
D 1.600 1.700 1.800 0.0630 0.0669 0.0709
D1 1.400 1.500 1.600 0.0551 0.0591 0.0630
E 1.300 1.400 1.500 0.0512 0.0551 0.0591
E1 0.175 0.200 0.225 0.0069 0.0079 0.0089
X - 0.200 - - 0.0079 -
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DS6638 Rev 36 35/54
M24C64-W M24C64-R M24C64-F M24C64-DF Package information
53
Figure 19. UFDFPN5 - 5-lead, 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch
dual flat package, no lead recommended footprint
1. Dimensions are expressed in millimeters.
Y - 0.200 - - 0.0079 -
e - 0.400 - - 0.0157 -
L 0.500 0.550 0.600 0.0197 0.0217 0.0236
L1 - 0.100 - - 0.0039 -
k - 0.400 - - 0.0157 -
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip.
Table 21. UFDFPN5 - 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch
dual flat package, no lead - package mechanical data (continued)
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
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Package information M24C64-W M24C64-R M24C64-F M24C64-DF
36/54 DS6638 Rev 36
9.2 UFDFPN8 (DFN8) package information
Figure 20. UFDFPN8 – 2x3 mm, 0.55 thickness, ultra thin fine pitch
dual flat package, no lead - package outline
1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) must be either connected to VSS or left floating
(not connected) in the end application.
Table 22. UFDFPN8 – 2x3 mm, 0.55 thickness, ultra thin fine pitch dual flat package,
no lead - package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to four decimal digits.
Min Typ Max Min Typ Max
A 0.450 0.550 0.600 0.0177 0.0217 0.0236
A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
D 1.900 2.000 2.100 0.0748 0.0787 0.0827
D2 1.200 - 1.600 0.0472 - 0.0630
E 2.900 3.000 3.100 0.1142 0.1181 0.1220
E2 1.200 - 1.600 0.0472 - 0.0630
e - 0.500 - - 0.0197 -
K 0.300 - - 0.0118 - -
L 0.300 - 0.500 0.0118 - 0.0197
L1 - - 0.150 - - 0.0059
L3 0.300 - - 0.0118 - -
eee(2)
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
0.080 - - 0.0031 - -
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DS6638 Rev 36 37/54
M24C64-W M24C64-R M24C64-F M24C64-DF Package information
53
9.3 TSSOP8 package information
Figure 21.TSSOP8 – 3x4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline,
package outline
1. Drawing is not to scale.
Table 23. TSSOP8 – 3 x 4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline,
package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to four decimal digits.
Min. Typ. Max. Min. Typ. Max.
A - - 1.200 - - 0.0472
A1 0.050 - 0.150 0.0020 - 0.0059
A2 0.800 1.000 1.050 0.0315 0.0394 0.0413
b 0.190 - 0.300 0.0075 - 0.0118
c 0.090 - 0.200 0.0035 - 0.0079
CP - - 0.100 - - 0.0039
D 2.900 3.000 3.100 0.1142 0.1181 0.1220
e - 0.650 - - 0.0256 -
E 6.200 6.400 6.600 0.2441 0.2520 0.2598
E1 4.300 4.400 4.500 0.1693 0.1732 0.1772
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
α0° - 8° 0° - 8°
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38/54 DS6638 Rev 36
9.4 SO8N package information
Figure 22. SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width,
package outline
1. Drawing is not to scale.
Table 24. SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width,
package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to four decimal digits.
Min. Typ. Max. Min. Typ. Max.
A - - 1.750 - - 0.0689
A1 0.100 - 0.250 0.0039 - 0.0098
A2 1.250 - - 0.0492 - -
b 0.280 - 0.480 0.0110 - 0.0189
c 0.170 - 0.230 0.0067 - 0.0091
D 4.800 4.900 5.000 0.1890 0.1929 0.1969
E 5.800 6.000 6.200 0.2283 0.2362 0.2441
E1 3.800 3.900 4.000 0.1496 0.1535 0.1575
e - 1.270 - - 0.0500 -
h 0.250 - 0.500 0.0098 - 0.0197
k 0° - 8° 0° - 8°
L 0.400 - 1.270 0.0157 - 0.0500
L1 - 1.040 - - 0.0409 -
ccc - - 0.100 - - 0.0039
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DS6638 Rev 36 39/54
M24C64-W M24C64-R M24C64-F M24C64-DF Package information
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Figure 23. SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width,
package recommended footprint
1. Dimensions are expressed in millimeters.
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9.5 PDIP8 package information
Figure 24. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline
1. Drawing is not to scale.
2. Not recommended for new designs.
Table 25. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to four decimal digits.
Min. Typ. Max. Min. Typ. Max.
A - - 5.33 - - 0.2098
A1 0.38 - - 0.0150 - -
A2 2.92 3.30 4.95 0.1150 0.1299 0.1949
b 0.36 0.46 0.56 0.0142 0.0181 0.0220
b2 1.14 1.52 1.78 0.0449 0.0598 0.0701
c 0.20 0.25 0.36 0.0079 0.0098 0.0142
D 9.02 9.27 10.16 0.3551 0.3650 0.4000
E 7.62 7.87 8.26 0.3000 0.3098 0.3252
E1 6.10 6.35 7.11 0.2402 0.2500 0.2799
e - 2.54 - - 0.1000 -
eA - 7.62 - - 0.3000 -
eB - - 10.92 - - 0.4299
L 2.92 3.30 3.81 0.1150 0.1299 0.1500
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DS6638 Rev 36 41/54
M24C64-W M24C64-R M24C64-F M24C64-DF Package information
53
9.6 WLCSP4 ultra thin package information
Figure 25. Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm,wafer level chip
scale package outline
1. Drawing is not to scale.
2. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
Table 26. Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip
scale package mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A 0.285 0.315 0.345 0.0112 0.0124 0.0136
A1 - 0.115 - - 0.0045 -
A2 - 0.175 - - 0.0069 -
A3 (BSC) - 0.025 - - 0.0010 -
b(2) (3) - 0.160 - - 0.0063 -
D - 0.795 0.815 - 0.0313 0.0321
E - 0.674 0.694 - 0.0265 0.0273
e - 0.400 - - 0.0157 -
F - 0.137 - - 0.0054 -
G - 0.198 - - 0.0078 -
aaa - - 0.110 - - 0.0043
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Package information M24C64-W M24C64-R M24C64-F M24C64-DF
42/54 DS6638 Rev 36
Figure 26. Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip scale
package recommended footprint
1. Dimensions are expressed in millimeters.
bbb - - 0.110 - - 0.0043
ccc - - 0.110 - - 0.0043
ddd - - 0.060 - - 0.0024
eee - - 0.060 - - 0.0024
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
Table 26. Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip
scale package mechanical data (continued)
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DS6638 Rev 36 43/54
M24C64-W M24C64-R M24C64-F M24C64-DF Package information
53
9.7 WLCSP5 package information
Figure 27. WLCSP 5-bump, 0.959 x 1.073 mm, 0.4 mm pitch wafer level chip scale
(M24C64-FCS6TP/K)- package outline
1. Drawing is not to scale.
2. The index on the wafer back side (circle) is above the index of the bump side (triangle/arrow).
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Package information M24C64-W M24C64-R M24C64-F M24C64-DF
44/54 DS6638 Rev 36
Figure 28. WLCSP - 5-bump, 0.959 x 1.073 mm, 0.4 mm pitch wafer level chip scale
recommended footprint
1. Dimensions are expressed in millimeters.
Table 27. WLCSP- 5-bump, 0.959 x 1.073 mm, 0.4 mm pitch wafer level chip scale
package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 0.455 0.545 0.645 0.0179 0.0215 0.0254
A1 - 0.190 - - 0.0075 -
A2 - 0.355 - - 0.0140 -
b(2)
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
- 0.270 - - 0.0106 -
D - 0.959 1.074 - 0.0378 0.0423
E - 1.073 1.168 - 0.0422 0.0460
e - 0.693 - - 0.0273 -
e1 - 0.400 - - 0.0157 -
e2 - 0.3465 - - 0.0136 -
F - 0.280 - - 0.0110 -
G - 0.190 - - 0.0075 -
aaa - - 0.110 - - 0.0043
bbb - - 0.110 - - 0.0043
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DS6638 Rev 36 45/54
M24C64-W M24C64-R M24C64-F M24C64-DF Package information
53
9.8 WLCSP8 thin package information
Figure 29. Thin WLCSP- 8-bump, 1.073 x 0.959 mm, wafer level chip scale
package outline
1. Drawing is not to scale.
2. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
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46/54 DS6638 Rev 36
Figure 30. Thin WLCSP- 8-bump, 1.073 x 0.959 mm, wafer level chip scale
package recommended footprint
1. Dimensions are expressed in millimeters.
Table 28. Thin WLCSP- 8-bump, 1.073 x 0.959 mm, wafer level chip scale
package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 0.300 0.315 0.330 0.0118 0.0124 0.0130
A1 - 0.115 - - 0.0045 -
A2 - 0.200 - - 0.0079 -
b(2)
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
- 0.160 - - 0.0063 -
D - 1.073 1.093 - 0.0422 0.0430
E - 0.959 0.979 - 0.0378 0.0385
e - 0.693 - - 0.0273 -
e1 - 0.800 - - 0.0315 -
e2 - 0.400 - - 0.0157 -
F - 0.133 - - 0.0052 -
G - 0.137 - - 0.0054 -
aaa - - 0.110 - - 0.0043
bbb - - 0.110 - - 0.0043
ccc - - 0.110 - - 0.0043
ddd - - 0.060 - - 0.0024
eee - - 0.060 - - 0.0024
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DS6638 Rev 36 47/54
M24C64-W M24C64-R M24C64-F M24C64-DF Ordering information
53
10 Ordering information
Table 29. Ordering information scheme
Example: M24C64 -D W MC 6 T P /P F
Device type
M24 = I2C serial access EEPROM
Device function
C64 = 64 Kbit (8192 x 8 bit)
Device family
Blank = Without Identification page
D = With Identification page
Operating voltage
W = VCC = 2.5 V to 5.5 V
R = VCC = 1.8 V to 5.5 V
F = VCC = 1.7 V to 5.5 V
Package
BN = PDIP8(1)
1. RoHS-compliant (ECOPACK1®)
MN = SO8 (150 mil width)(2)
2. ECOPACK2® ((RoHS compliant and free of brominated, chlorinated and antimony oxide flame retardants))
DW = TSSOP8 (169 mil width)(2)
MC = UFDFPN8 (DFN8)(2)
MH = UFDFPN5 (DFN5)(2)
CS = 5-bump WLCSP(2)
CT = 8-bump WLCSP(2)
CU = 4-bump WLCSP
Device grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
Option
T = Tape and reel packing
blank = tube packing
Plating technology
P or G = ECOPACK2®
Process(3) or Packing option
3. The process letter is used only when ordering WLCSP packages, the process letter is not specified when
ordering any other package. These process letters appear on the device package (marking) and on the
shipment box. Please contact your nearest ST Sales Office for further information.
/P or /K or /T = Manufacturing technology code
/12 = Packing 12 mm tape
Option
Blank = No Back Side Coating
F = Back Side Coating (WLCSP height = 0.345mm)
Ordering information M24C64-W M24C64-R M24C64-F M24C64-DF
48/54 DS6638 Rev 36
Table 30. Ordering information scheme (unsawn wafer)(1) (2)
1. For all information concerning the M24C64 delivered in unsawn wafer, please contact your nearest ST
Sales Office.
2. Unsawn wafer in preview.
Example: M24C64 - F T W 20 I /90
Device type
M24 = I2C serial access EEPROM
Device function
C64 = 64 Kbit (8192 x 8 bit)
Operating voltage
F = VCC = 1.7 V to 5.5 V
Process
T = F8H+
Delivery form
W = Wafer (bare die)
Wafer thickness
20 = Non-backlapped wafer
Wafer testing
I = Inkless test
Device grade
90 = -40°C to 85°C
DS6638 Rev 36 49/54
M24C64-W M24C64-R M24C64-F M24C64-DF Ordering information
53
Engineering samples
Parts marked as ES or E are not yet qualified and therefore not approved for use in
production. ST is not responsible for any consequences deriving from such use. In no event,
will ST be liable for the customer using of these engineering samples in production. ST’s
quality department must be contacted prior to any decision to use these engineering
samples to run qualification activity.
Revision history M24C64-W M24C64-R M24C64-F M24C64-DF
50/54 DS6638 Rev 36
11 Revision history
Table 31. Document revision history
Date Revision Changes
14-Mar-2011 22
Updated information concerning E2, E1, E0 for the WLCSP package:
note under Figure 3: UFDFPN5 package connections
comment under Figure 7: Chip enable inputs connection
note 3 under Table 2: Device select code
07-Apr-2011 23 Updated MLP8 package data and Section 10: Part numberingAdded
footnote (a) in Section 4.5: Memory addressing.
18-May-2011 24
Updated:
Figure 3: UFDFPN5 package connections
Table 6: Absolute maximum ratings
Small text changes
Added:
Figure 12: Memory cell characteristics
08-Sep-2011 25
Updated:
Table 22: UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no
lead, 2 x 3 mm, data
Figure 16: Maximum Rbus value versus bus parasitic capacitance
Cbus) for an I2C bus at maximum frequency fC = 1MHz
Figure 6: I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value
versus bus parasitic capacitance (Cbus).
Added tWLDL and tDHWH in:
Table 17: 400 kHz AC characteristics
Table 18: 1 MHz AC characteristics
Figure :
Minor text changes.
16-Dec-2011 26 Updated A dimension in Table 25: WLCSP- 5-bump, 0.959 x 1.073 mm,
0.4 mm pitch wafer level chip scale package mechanical data.
DS6638 Rev 36 51/54
M24C64-W M24C64-R M24C64-F M24C64-DF Revision history
53
28-Aug-2012 27
Datasheet split into:
– M24C64-DF, M24C64-W, M24C64-R,M24C64-F (this
datasheet) for standard products (range 6),
– M24C64-125 datasheet for automotive products (range 3).
Added 8-bump thin WLCSP.
Updated single supply voltage and number of Write cycles on cover
page.
Updated Section 2.1: Serial Clock (SCL) and Section 2.2: Serial Data
(SDA).
Updated Figure 8: Block diagram.
Added Section 4.5: Device addressing.
Section 5.1: Write operations move to Section 5: Instructions and
updated.
Moved Figure 10: Write mode sequences with WC = 0 (data write
enabled) to Section 5.1.1: Byte Write.
Section 5.1.2: Page Write: changed address bits to A15/A5 and updated
Figure 11.
Case of locked Write identification Page removed from Section 5.1.4:
Lock Identification Page (M24C64-D only).
Updated Section 5.1.5: ECC (Error Correction Code) and Write cycling
and move Figure 12: Write cycle polling flowchart using ACK to
Section 5.1.6: Minimizing Write delays by polling on ACK.
Added note 1 in Table 7: Operating conditions (voltage range W) and
Table 8: Operating conditions (voltage range R).
Added Table 12 and updated Table 13: Memory cell data retention.
Removed note 2 in Table 17: 400 kHz AC characteristics for tQL1QL2,
tWLDL, tDHWH, and tNS.
Table 27: Ordering information scheme: removed ambient operating
temperature for device grade 5 and added Note 3. to MLP8 and WLCSP
packages.
18-Nov-2013 28
Added text in Chapter 5.2.2: Current Address Read
Updated note (1) under Table 6: Absolute maximum ratings.
Removed note (3) in Table 3: Device select code.
Updated notes below Table 14: DC characteristics (M24C64-W, device
grade 6) and Table 15: DC characteristics (M24C64-R device grade 6)
Renamed Figure 19 and Table 25.
Updated captions above Figure 26 and Figure 24.
Table 31. Document revision history (continued)
Date Revision Changes
Revision history M24C64-W M24C64-R M24C64-F M24C64-DF
52/54 DS6638 Rev 36
21-Jul-2014 29
Updated Figure 3, Figure 6, Table 15, Table 9, Table 17, Table 18 and
Table 27.
Updated ECOPACK info on front page.
Updated notes:
(1) on Table 7 , Table 8, Table 14, Table 18
(2) merged with (3) on Table 15
(8) on Table 15
(2) on Table 16
(3) on Table 27
Added:
note (1) on Table 9
Added:
supply voltage level specification on Cover page.
package UFDFPN5 on Cover page
Table 18 and Figure 18 related to UFDFPN5 package.
Note (1) on Section 5.1.5
12-Nov-2014 30
Added:
note 2 on Table 14
note 2 on DW, MC and CS package on Table 27
note 1on BN package on Table 27
Figure 3
Updated:
Section 1: Description
Chapter 5.1.5
note 3 on Table 6
note 1 on Table 9
note 1 on Table 12
note 1 on Table 13
–I
CC0 max value and note 5 on Table 14
–I
CC0 max value on Table 15
–I
CC0 max value on Table 16
note 2 on Table 27
30-Jul-2015 31 Added WLCSP package.
Updated Table 27.
18-Feb-2016 32 Updated Figure 4, Figure 18,Table 19 and added Table 2
22-June-2016 33 Added Reference to unsawn wafer inside cover page and added
Table 28: Ordering information scheme (unsawn wafer)
Table 31. Document revision history (continued)
Date Revision Changes
DS6638 Rev 36 53/54
M24C64-W M24C64-R M24C64-F M24C64-DF Revision history
53
13-Sep-2017 34
Added reference to DFN8 and DFN5 in:
cover page figure, Figure 3: UFDFPN5 (DFN5) package connections,
Section 9.1: UFDFPN5 (DFN5) package information, Section 9.2:
UFDFPN8 (DFN8) package information and Table 29: Ordering
information scheme.
Added Figure 19: UFDFPN5 - 5-lead, 1.7 × 1.4 mm, 0.55 mm thickness,
ultra thin fine pitch dual flat package, no lead recommended footprint.
Updated Section Table 28.: Thin WLCSP- 8-bump, 1.073 x 0.959 mm,
wafer level chip scale package mechanical data
16-Nov-2017 35 Updated Table 29: Ordering information scheme
14-Mar-2018 36
Added Table 3: WLCSP 5-bump signals vs. bump position, Table 4:
WLCSP 8-bump signals vs bump position
Updated Figure 6: WLCSP 8-bump thin connections (M24C64-
DFCT6TP/K)
Table 31. Document revision history (continued)
Date Revision Changes
M24C64-W M24C64-R M24C64-F M24C64-DF
54/54 DS6638 Rev 36
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
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