74LVC(H)2T45

Nexperia USA Inc.

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Datasheet

74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
Rev. 9 — 13 August 2018 Product data sheet
1. General description
The 74LVC2T45; 74LVCH2T45 are dual bit, dual supply translating transceivers with 3-state
outputs that enable bidirectional level translation. They feature two 2-bits input-output ports
(nA and nB), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A)
and VCC(B) can be supplied at any voltage between 1.2 V and 5.5 V making the device suitable
for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V).
Pins nA and DIR are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR
allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.
The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing any damaging backflow current through the device when it is
powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and
B port are in the high-impedance OFF-state.
Active bus hold circuitry in the 74LVCH2T45 holds unused or floating data inputs at a valid logic
level.
2. Features and benefits
Wide supply voltage range:
VCC(A): 1.2 V to 5.5 V
VCC(B): 1.2 V to 5.5 V
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 4000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Maximum data rates:
420 Mbps (3.3 V to 5.0 V translation)
210 Mbps (translate to 3.3 V))
140 Mbps (translate to 2.5 V)
75 Mbps (translate to 1.8 V)
60 Mbps (translate to 1.5 V)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
±24 mA output drive (VCC = 3.0 V)
Inputs accept voltages up to 5.5 V
Low power consumption: 16 μA maximum ICC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
3. Ordering information
Table 1. Ordering information
PackageType number
Temperature range Name Description Version
74LVC2T45DC
74LVCH2T45DC
-40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
SOT765-1
74LVC2T45GT
74LVCH2T45GT
-40 °C to +125 °C XSON8 plastic extremely thin small outline package;
no leads; 8 terminals; body 1 × 1.95 × 0.5 mm
SOT833-1
74LVC2T45GF
74LVCH2T45GF
-40 °C to +125 °C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.35 × 1 × 0.5 mm
SOT1089
74LVC2T45GM
74LVCH2T45GM
-40 °C to +125 °C XQFN8 plastic, extremely thin quad flat package;
no leads; 8 terminals; body 1.6 × 1.6 × 0.5 mm
SOT902-2
74LVC2T45GN
74LVCH2T45GN
-40 °C to +125 °C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.2 × 1.0 × 0.35 mm
SOT1116
74LVC2T45GS
74LVCH2T45GS
-40 °C to +125 °C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.35 × 1.0 × 0.35 mm
SOT1203
4. Marking
Table 2. Marking
Type number Marking code [1]
74LVC2T45DC V45
74LVCH2T45DC X45
74LVC2T45GT V45
74LVCH2T45GT X45
74LVC2T45GF V5
74LVCH2T45GF X5
74LVC2T45GM V45
74LVCH2T45GM X45
74LVC2T45GN V5
74LVCH2T45GN X5
74LVC2T45GS V5
74LVCH2T45GS X5
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 2 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
5. Functional diagram
001aag577
DIR
1B
2B
7
6
1A
2A
5
2
3
VCC(A) VCC(B)
Fig. 1. Logic symbol
001aag578
DIR
1B
2B
1A
2A
VCC(A) VCC(B)
Fig. 2. Logic diagram
6. Pinning information
6.1. Pinning
74LVC2T45
74LVCH2T45
VCC(A) VCC(B)
1A 1B
2A 2B
GND DIR
001aai904
1
2
3
4
6
5
8
7
Fig. 3. Pin configuration SOT765-1 (VSSOP8)
74LVC2T45
74LVCH2T45
2B
1B
VCC(B)
DIR
2A
1A
VCC(A)
GND
001aai905
3 6
2 7
1 8
4 5
Transparent top view
Fig. 4. Pin configuration SOT833-1, SOT1089, SOT1116
and SOT1203 (XSON8)
001aai906
1A2B
VCC(A)
V
C
C
(
B
)
2A
1B
GND
DIR
Transparent top view
3
6
4
1
5
8
7
2
terminal 1
index area
74LVC2T45
74LVCH2T45
Fig. 5. Pin configuration SOTSOT902-2 (XQFN8)
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 3 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
6.2. Pin description
Table 3. Pin description
PinSymbol
SOT765-1, SOT833-1, SOT1089,
SOT1116 and SOT1203
SOT902-2
Description
VCC(A) 1 7 supply voltage A (port A and DIR)
1A 2 6 data input or output
2A 3 5 data input or output
GND 4 4 ground (0 V)
DIR 5 3 direction control
2B 6 2 data input or output
1B 7 1 data input or output
VCC(B) 8 8 supply voltage B (port B)
7. Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Supply voltage Input Input/output [1]
VCC(A), VCC(B) DIR nA nB
1.2 V to 5.5 V L nA = nB input
1.2 V to 5.5 V H input nB = nA
GND [2] X Z Z
[1] The input circuit of the data I/O is always active.
[2] When either VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 4 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC(A) supply voltage A -0.5 +6.5 V
VCC(B) supply voltage B -0.5 +6.5 V
IIK input clamping current VI < 0 V -50 - mA
VIinput voltage [1] -0.5 +6.5 V
IOK output clamping current VO < 0 V -50 - mA
Active mode [1][2][3] -0.5 VCCO + 0.5 VVOoutput voltage
Suspend or 3-state mode [1] -0.5 +6.5 V
IOoutput current VO = 0 V to VCCO [2] - ±50 mA
ICC supply current ICC(A) or ICC(B) - 100 mA
IGND ground current -100 - mA
Tstg storage temperature -65 +150 °C
Ptot total power dissipation Tamb = -40 °C to +125 °C [4] - 250 mW
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] VCCO is the supply voltage associated with the output port.
[3] VCCO + 0.5 V should not exceed 6.5 V.
[4] For VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6. Recommended operating conditions
Symbol Parameter Conditions Min Max Unit
VCC(A) supply voltage A 1.2 5.5 V
VCC(B) supply voltage B 1.2 5.5 V
VIinput voltage 0 5.5 V
Active mode [1] 0 VCCO VVOoutput voltage
Suspend or 3-state mode 0 5.5 V
Tamb ambient temperature -40 +125 °C
VCCI = 1.2 V [2] - 20 ns/V
VCCI = 1.4 V to 1.95 V - 20 ns/V
VCCI = 2.3 V to 2.7 V - 20 ns/V
VCCI = 3 V to 3.6 V - 10 ns/V
Δt/ΔV input transition rise and fall rate
VCCI = 4.5 V to 5.5 V - 5 ns/V
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the input port.
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 5 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
10. Static characteristics
Table 7. Typical static characteristics at Tamb = 25 °C
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
VOH HIGH-level output voltage VI = VIH or VIL; IO = -3 mA; VCCO = 1.2 V [1] - 1.09 - V
VOL LOW-level output voltage VI = VIH or VIL; IO = 3 mA; VCCO = 1.2 V [1] - 0.07 - V
IIinput leakage current DIR input; VI = 0 V to 5.5 V;
VCCI = 1.2 V to 5.5 V
[2] - - ±1 μA
IBHL bus hold LOW current A or B port; VI = 0.42 V; VCCI = 1.2 V [2] - 19 - μA
IBHH bus hold HIGH current A or B port; VI = 0.78 V; VCCI = 1.2 V [2] - -19 - μA
IBHLO bus hold LOW overdrive current A or B port; VCCI = 1.2 V [2][3] - 19 - μA
IBHHO bus hold HIGH overdrive current A or B port; VCCI = 1.2 V [2][3] - -19 - μA
IOZ OFF-state output current A or B port; VO = 0 V or VCCO;
VCCO = 1.2 V to 5.5 V
[1] - - ±1 μA
A port; VI or VO = 0 V to 5.5 V;
VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V
- - ±1 μAIOFF power-off leakage current
B port; VI or VO = 0 V to 5.5 V;
VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V
- - ±1 μA
CIinput capacitance DIR input; VI = 0 V or 3.3 V;
VCC(A) = VCC(B) = 3.3 V
- 2.2 - pF
CI/O input/output capacitance A and B port; suspend mode;
VO = 3.3 V or 0 V; VCC(A) = VCC(B) = 3.3 V
- 6.0 - pF
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the data input port.
[3] To guarantee the node switches, an external driver must source/sink at least IBHLO/IBHHO when the input is in the range VIL to VIH.
Table 8. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions
Min Max Min Max
Unit
data input [1]
VCCI = 1.2 V 0.8VCCI - 0.8VCCI - V
VCCI = 1.4 V to 1.95 V 0.65VCCI - 0.65VCCI - V
VCCI = 2.3 V to 2.7 V 1.7 - 1.7 - V
VCCI = 3.0 V to 3.6 V 2.0 - 2.0 - V
VCCI = 4.5 V to 5.5 V 0.7VCCI - 0.7VCCI - V
DIR input
VCCI = 1.2 V 0.8VCC(A) - 0.8VCC(A) - V
VCCI = 1.4 V to 1.95 V 0.65VCC(A) - 0.65VCC(A) - V
VCCI = 2.3 V to 2.7 V 1.7 - 1.7 - V
VCCI = 3.0 V to 3.6 V 2.0 - 2.0 - V
VIH HIGH-level
input voltage
VCCI = 4.5 V to 5.5 V 0.7VCC(A) - 0.7VCC(A) - V
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 6 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions
Min Max Min Max
Unit
data input [1]
VCCI = 1.2 V - 0.2VCCI - 0.2VCCI V
VCCI = 1.4 V to 1.95 V - 0.35VCCI - 0.35VCCI V
VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V
VCCI = 3.0 V to 3.6 V - 0.8 - 0.8 V
VCCI = 4.5 V to 5.5 V - 0.3VCCI - 0.3VCCI V
DIR input
VCCI = 1.2 V - 0.2VCC(A) - 0.2VCC(A) V
VCCI = 1.4 V to 1.95 V - 0.35VCC(A) - 0.35VCC(A) V
VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V
VCCI = 3.0 V to 3.6 V - 0.8 - 0.8 V
VIL LOW-level input
voltage
VCCI = 4.5 V to 5.5 V - 0.3VCC(A) - 0.3VCC(A) V
VI = VIH
IO = -100 μA;
VCCO = 1.2 V to 4.5 V
[2] VCCO - 0.1 - VCCO - 0.1 - V
IO = -6 mA; VCCO = 1.4 V 1.0 - 1.0 - V
IO = -8 mA; VCCO = 1.65 V 1.2 - 1.2 - V
IO = -12 mA; VCCO = 2.3 V 1.9 - 1.9 - V
IO = -24 mA; VCCO = 3.0 V 2.4 - 2.4 - V
VOH HIGH-level
output voltage
IO = -32 mA; VCCO = 4.5 V 3.8 - 3.8 - V
VI = VIL [2]
IO = 100 μA;
VCCO = 1.2 V to 4.5 V
- 0.1 - 0.1 V
IO = 6 mA; VCCO = 1.4 V - 0.3 - 0.3 V
IO = 8 mA; VCCO = 1.65 V - 0.45 - 0.45 V
IO = 12 mA; VCCO = 2.3 V - 0.3 - 0.3 V
IO = 24 mA; VCCO = 3.0 V - 0.55 - 0.55 V
VOL LOW-level
output voltage
IO = 32 mA; VCCO = 4.5 V - 0.55 - 0.55 V
IIinput leakage
current
DIR input; VI = 0 V to 5.5 V;
VCCI = 1.2 V to 5.5 V
- ±2 - ±10 μA
A or B port [1]
VI = 0.49 V; VCCI = 1.4 V 15 - 10 - μA
VI = 0.58 V; VCCI = 1.65 V 25 - 20 - μA
VI = 0.70 V; VCCI = 2.3 V 45 - 45 - μA
VI = 0.80 V; VCCI = 3.0 V 100 - 80 - μA
IBHL bus hold LOW
current
VI = 1.35 V; VCCI = 4.5 V 100 - 100 - μA
A or B port [1]
VI = 0.91 V; VCCI = 1.4 V -15 - -10 - μA
VI = 1.07 V; VCCI = 1.65 V -25 - -20 - μA
VI = 1.60 V; VCCI = 2.3 V -45 - -45 - μA
VI = 2.00 V; VCCI = 3.0 V -100 - -80 - μA
IBHH bus hold HIGH
current
VI = 3.15 V; VCCI = 4.5 V -100 - -100 - μA
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 7 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions
Min Max Min Max
Unit
A or B port [1][3]
VCCI = 1.6 V 125 - 125 - μA
VCCI = 1.95 V 200 - 200 - μA
VCCI = 2.7 V 300 - 300 - μA
VCCI = 3.6 V 500 - 500 - μA
IBHLO bus hold LOW
overdrive
current
VCCI = 5.5 V 900 - 900 - μA
A or B port [1][3]
VCCI = 1.6 V -125 - -125 - μA
VCCI = 1.95 V -200 - -200 - μA
VCCI = 2.7 V -300 - -300 - μA
VCCI = 3.6 V -500 - -500 - μA
IBHHO bus hold HIGH
overdrive
current
VCCI = 5.5 V -900 - -900 - μA
IOZ OFF-state
output current
A or B port; VO = 0 V or VCCO;
VCCO = 1.2 V to 5.5 V
[2] - ±2 - ±10 μA
A port; VI or VO = 0 V to 5.5 V;
VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V
- ±2 - ±10 μAIOFF power-off
leakage current
B port; VI or VO = 0 V to 5.5 V;
VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V
- ±2 - ±10 μA
A port; VI = 0 V or VCCI; IO = 0 A [1]
VCC(A), VCC(B) = 1.2 V to 5.5 V - 8 - 8 μA
VCC(A), VCC(B) = 1.65 V to 5.5 V - 3 - 3 μA
VCC(A) = 5.5 V; VCC(B) = 0 V - 2 - 2 μA
VCC(A) = 0 V; VCC(B) = 5.5 V -2 - -2 - μA
B port; VI = 0 V or VCCI; IO = 0 A
VCC(A), VCC(B) = 1.2 V to 5.5 V - 8 - 8 μA
VCC(A), VCC(B) = 1.65 V to 5.5 V - 3 - 3 μA
VCC(B) = 0 V; VCC(A) = 5.5 V -2 - -2 - μA
VCC(B) = 5.5 V; VCC(A) = 0 V - 2 - 2 μA
A plus B port (ICC(A) + ICC(B));
IO = 0 A; VI = 0 V or VCCI
VCC(A), VCC(B) = 1.2 V to 5.5 V - 16 - 16 μA
ICC supply current
VCC(A), VCC(B) = 1.65 V to 5.5 V - 4 - 4 μA
per input;
VCC(A), VCC(B) = 3.0 V to 5.5 V
A port; A port at VCC(A) - 0.6 V;
DIR at VCC(A); B port = open
[4] - 50 - 75 μA
DIR input; DIR at VCC(A) - 0.6 V;
A port at VCC(A) or GND;
B port = open
- 50 - 75 μA
ΔICC additional
supply current
B port; B port at VCC(B) - 0.6 V;
DIR at GND; A port = open
[4] - 50 - 75 μA
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
[3] To guarantee the node switches, an external driver must source/sink at least IBHLO/IBHHO when the input is in the range VIL to VIH.
[4] For non bus hold parts only (74LVC2T45).
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 8 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
11. Dynamic characteristics
Table 9. Typical dynamic characteristics at VCC(A) = 1.2 V and Tamb = 25 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8; for waveforms see Fig. 6 and Fig. 7.
VCC(B)
Symbol Parameter Conditions
1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V
Unit
A to B 10.6 8.1 7.0 5.8 5.3 5.1 nstPLH LOW to HIGH
propagation delay B to A 10.6 9.5 9.0 8.5 8.3 8.2 ns
A to B 10.1 7.1 6.0 5.3 5.2 5.4 nstPHL HIGH to LOW
propagation delay B to A 10.1 8.6 8.1 7.8 7.6 7.6 ns
DIR to A 9.4 9.4 9.4 9.4 9.4 9.4 nstPHZ HIGH to OFF-state
propagation delay DIR to B 12.0 9.4 9.0 7.8 8.4 7.9 ns
DIR to A 7.1 7.1 7.1 7.1 7.1 7.1 nstPLZ LOW to OFF-state
propagation delay DIR to B 9.5 7.8 7.7 6.9 7.6 7.0 ns
DIR to A [1] 20.1 17.3 16.7 15.4 15.9 15.2 nstPZH OFF-state to HIGH
propagation delay DIR to B [1] 17.7 15.2 14.1 12.9 12.4 12.2 ns
DIR to A [1] 22.1 18.0 17.1 15.6 16.0 15.5 nstPZL OFF-state to LOW
propagation delay DIR to B [1] 19.5 16.5 15.4 14.7 14.6 14.8 ns
[1] tPZH and tPZL are calculated values using the formula shown in Section 13.4.
Table 10. Typical dynamic characteristics at VCC(B) = 1.2 V and Tamb = 25 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8; for waveforms see Fig. 6 and Fig. 7.
VCC(A)
Symbol Parameter Conditions
1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V
Unit
A to B 10.6 9.5 9.0 8.5 8.3 8.2 nstPLH LOW to HIGH
propagation delay B to A 10.6 8.1 7.0 5.8 5.3 5.1 ns
A to B 10.1 8.6 8.1 7.8 7.6 7.6 nstPHL HIGH to LOW
propagation delay B to A 10.1 7.1 6.0 5.3 5.2 5.4 ns
DIR to A 9.4 6.5 5.7 4.1 4.1 3.0 nstPHZ HIGH to OFF-state
propagation delay DIR to B 12.0 6.1 5.4 4.6 4.3 4.0 ns
DIR to A 7.1 4.9 4.5 3.2 3.4 2.5 nstPLZ LOW to OFF-state
propagation delay DIR to B 9.5 7.3 6.6 5.9 5.7 5.6 ns
DIR to A [1] 20.1 15.4 13.6 11.7 11.0 10.7 nstPZH OFF-state to HIGH
propagation delay DIR to B [1] 17.7 14.4 13.5 11.7 11.7 10.7 ns
DIR to A [1] 22.1 13.2 11.4 9.9 9.5 9.4 nstPZL OFF-state to LOW
propagation delay DIR to B [1] 19.5 15.1 13.8 11.9 11.7 10.6 ns
[1] tPZH and tPZL are calculated values using the formula shown in Section 13.4.
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 9 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
Table 11. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C
Voltages are referenced to GND (ground = 0 V).
VCC(A) and VCC(B)
Symbol Parameter Conditions
1.8 V 2.5 V 3.3 V 5.0 V
Unit
A port: (direction A to B);
B port: (direction B to A)
2 3 3 4 pFCPD power dissipation
capacitance[1] [2]
A port: (direction A to B);
B port: (direction B to A)
15 16 16 18 pF
[1] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC
2 × fi × N + Σ(CL × VCC
2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC
2 × fo) = sum of the outputs.
[2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω.
Table 12. Dynamic characteristics for temperature range -40 °C to +85 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8; for waveforms see Fig. 6 and Fig. 7.
VCC(B)
1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V
Symbol Parameter Conditions
Min Max Min Max Min Max Min Max Min Max
Unit
VCC(A) = 1.4 V to 1.6 V
A to B 2.8 21.3 2.4 17.6 2.0 13.5 1.7 11.8 1.6 10.5 nstPLH LOW to HIGH
propagation delay B to A 2.8 21.3 2.6 19.1 2.3 14.9 2.3 12.4 2.2 12.0 ns
A to B 2.6 19.3 2.2 15.3 1.8 11.8 1.7 10.9 1.7 10.8 nstPHL HIGH to LOW
propagation delay B to A 2.6 19.3 2.4 17.3 2.3 13.2 2.2 11.3 2.3 11.0 ns
DIR to A 3.0 18.7 3.0 18.7 3.0 18.7 3.0 18.7 3.0 18.7 nstPHZ HIGH to OFF-state
propagation delay DIR to B 3.5 24.8 3.5 23.6 3.0 11.0 3.3 11.3 2.8 10.3 ns
DIR to A 2.4 11.4 2.4 11.4 2.4 11.4 2.4 11.4 2.4 11.4 nstPLZ LOW to OFF-state
propagation delay DIR to B 2.8 18.3 3.0 17.2 2.5 9.4 3.0 10.1 2.5 9.4 ns
DIR to A [1] - 39.6 - 36.3 - 24.3 - 22.5 - 21.4 nstPZH OFF-state to HIGH
propagation delay DIR to B [1] - 32.7 - 29.0 - 24.9 - 23.2 - 21.9 ns
DIR to A [1] - 44.1 - 40.9 - 24.2 - 22.6 - 21.3 nstPZL OFF-state to LOW
propagation delay DIR to B [1] - 38.0 - 34.0 - 30.5 - 29.6 - 29.5 ns
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 10 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
VCC(B)
1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V
Symbol Parameter Conditions
Min Max Min Max Min Max Min Max Min Max
Unit
VCC(A) = 1.65 V to 1.95 V
A to B 2.6 19.1 2.2 17.7 2.2 9.3 1.7 7.2 1.4 6.8 nstPLH LOW to HIGH
propagation delay B to A 2.4 17.6 2.2 17.7 2.3 16.0 2.1 15.5 1.9 15.1 ns
A to B 2.4 17.3 2.0 14.3 1.6 8.5 1.8 7.1 1.7 7.0 nstPHL HIGH to LOW
propagation delay B to A 2.2 15.3 2.0 14.3 2.1 12.9 2.0 12.6 1.8 12.2 ns
DIR to A 2.9 17.1 2.9 17.1 2.9 17.1 2.9 17.1 2.9 17.1 nstPHZ HIGH to OFF-state
propagation delay DIR to B 3.2 24.1 3.2 21.9 2.7 11.5 3.0 10.3 2.5 8.2 ns
DIR to A 2.4 10.5 2.4 10.5 2.4 10.5 2.4 10.5 2.4 10.5 nstPLZ LOW to OFF-state
propagation delay DIR to B 2.5 17.6 2.6 16.0 2.2 9.2 2.7 8.4 2.4 7.1 ns
DIR to A [1] - 35.2 - 33.7 - 25.2 - 23.9 - 22.2 nstPZH OFF-state to HIGH
propagation delay DIR to B [1] - 29.6 - 28.2 - 19.8 - 17.7 - 17.3 ns
DIR to A [1] - 39.4 - 36.2 - 24.4 - 22.9 - 20.4 nstPZL OFF-state to LOW
propagation delay DIR to B [1] - 34.4 - 31.4 - 25.6 - 24.2 - 24.1 ns
VCC(A) = 2.3 V to 2.7 V
A to B 2.3 17.9 2.3 16.0 1.5 8.5 1.3 6.2 1.1 4.8 nstPLH LOW to HIGH
propagation delay B to A 2.0 13.5 2.2 9.3 1.5 8.5 1.4 8.0 1.0 7.5 ns
A to B 2.3 15.8 2.1 12.9 1.4 7.5 1.3 5.4 0.9 4.6 nstPHL HIGH to LOW
propagation delay B to A 1.8 11.8 1.9 8.5 1.4 7.5 1.3 7.0 0.9 6.2 ns
DIR to A 2.1 8.1 2.1 8.1 2.1 8.1 2.1 8.1 2.1 8.1 nstPHZ HIGH to OFF-state
propagation delay DIR to B 3.0 22.5 3.0 21.4 2.5 11.0 2.8 9.3 2.3 6.9 ns
DIR to A 1.7 5.8 1.7 5.8 1.7 5.8 1.7 5.8 1.7 5.8 nstPLZ LOW to OFF-state
propagation delay DIR to B 2.3 14.6 2.5 13.2 2.0 9.0 2.5 8.4 1.8 5.8 ns
DIR to A [1] - 28.1 - 22.5 - 17.5 - 16.4 - 13.3 nstPZH OFF-state to HIGH
propagation delay DIR to B [1] - 23.7 - 21.8 - 14.3 - 12.0 - 10.6 ns
DIR to A [1] - 34.3 - 29.9 - 18.5 - 16.3 - 13.1 nstPZL OFF-state to LOW
propagation delay DIR to B [1] - 23.9 - 21.0 - 15.6 - 13.5 - 12.7 ns
VCC(A) = 3.0 V to 3.6 V
A to B 2.3 17.1 2.1 15.5 1.4 8.0 0.8 5.6 0.7 4.4 nstPLH LOW to HIGH
propagation delay B to A 1.7 11.8 1.7 7.2 1.3 6.2 0.7 5.6 0.6 5.4 ns
A to B 2.2 15.6 2.0 12.6 1.3 7.0 0.8 5.0 0.7 4.0 nstPHL HIGH to LOW
propagation delay B to A 1.7 10.9 1.8 7.1 1.3 5.4 0.8 5.0 0.7 4.5 ns
DIR to A 2.3 7.3 2.3 7.3 2.3 7.3 2.3 7.3 2.7 7.3 nstPHZ HIGH to OFF-state
propagation delay DIR to B 2.9 18.0 2.9 16.5 2.3 10.1 2.7 8.6 2.2 6.3 ns
DIR to A 2.0 5.6 2.0 5.6 2.0 5.6 2.0 5.6 2.0 5.6 nstPLZ LOW to OFF-state
propagation delay DIR to B 2.3 13.6 2.4 12.5 1.9 7.8 2.3 7.1 1.7 4.9 ns
DIR to A [1] - 25.4 - 19.7 - 14.0 - 12.7 - 10.3 nstPZH OFF-state to HIGH
propagation delay DIR to B [1] - 22.7 - 21.1 - 13.6 - 11.2 - 10.0 ns
DIR to A [1] - 28.9 - 23.6 - 15.5 - 13.6 - 10.8 nstPZL OFF-state to LOW
propagation delay DIR to B [1] - 22.9 - 19.9 - 14.3 - 12.3 - 11.3 ns
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 11 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
VCC(B)
1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V
Symbol Parameter Conditions
Min Max Min Max Min Max Min Max Min Max
Unit
VCC(A) = 4.5 V to 5.5 V
A to B 2.2 16.6 1.9 15.1 1.0 7.5 0.7 5.4 0.5 3.9 nstPLH LOW to HIGH
propagation delay B to A 1.6 10.5 1.4 6.8 1.0 4.8 0.7 4.4 0.5 3.9 ns
A to B 2.3 15.3 1.8 12.2 1.0 6.2 0.7 4.5 0.5 3.5 nstPHL HIGH to LOW
propagation delay B to A 1.7 10.8 1.7 7.0 0.9 4.6 0.7 4.0 0.5 3.5 ns
DIR to A 1.7 5.4 1.7 5.4 1.7 5.4 1.7 5.4 1.7 5.4 nstPHZ HIGH to OFF-state
propagation delay DIR to B 2.9 17.3 2.9 16.1 2.3 9.7 2.7 8.0 2.5 5.7 ns
DIR to A 1.4 3.7 1.4 3.7 1.3 3.7 1.0 3.7 0.9 3.7 nstPLZ LOW to OFF-state
propagation delay DIR to B 2.3 13.1 2.4 12.1 1.9 7.4 2.3 7.0 1.8 4.5 ns
DIR to A [1] - 23.6 - 18.9 - 12.2 - 11.4 - 8.4 nstPZH OFF-state to HIGH
propagation delay DIR to B [1] - 20.3 - 18.8 - 11.2 - 9.1 - 7.6 ns
DIR to A [1] - 28.1 - 23.1 - 14.3 - 12.0 - 9.2 nstPZL OFF-state to LOW
propagation delay DIR to B [1] - 20.7 - 17.6 - 11.6 - 9.9 - 8.9 ns
[1] tPZH and tPZL are calculated values using the formula shown in Section 13.4.
Table 13. Dynamic characteristics for temperature range -40 °C to +125 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8; for waveforms see Fig. 6 and Fig. 7.
VCC(B)
1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V
Symbol Parameter Conditions
Min Max Min Max Min Max Min Max Min Max
Unit
VCC(A) = 1.4 V to 1.6 V
A to B 2.5 23.5 2.1 19.4 1.8 14.9 1.5 13.0 1.4 11.6 nstPLH LOW to HIGH
propagation delay B to A 2.5 23.5 2.3 21.1 2.0 16.4 2.0 13.7 1.9 13.2 ns
A to B 2.3 21.3 1.9 16.9 1.6 13.0 1.5 12.0 1.5 11.9 nstPHL HIGH to LOW
propagation delay B to A 2.3 21.3 2.1 19.1 2.0 14.6 1.9 12.5 2.0 12.1 ns
DIR to A 2.7 20.6 2.7 20.6 2.7 20.6 2.7 20.6 2.7 20.6 nstPHZ HIGH to OFF-state
propagation delay DIR to B 3.1 27.3 3.1 26.0 2.7 12.1 2.9 12.5 2.5 11.4 ns
DIR to A 2.1 12.6 2.1 12.6 2.1 12.6 2.1 12.6 2.1 12.6 nstPLZ LOW to OFF-state
propagation delay DIR to B 2.5 20.2 2.7 19.0 2.2 10.4 2.7 11.2 2.2 10.4 ns
DIR to A [1] - 43.7 - 40.1 - 26.8 - 24.9 - 23.6 nstPZH OFF-state to HIGH
propagation delay DIR to B [1] - 36.1 - 32.0 - 27.5 - 25.6 - 24.2 ns
DIR to A [1] - 48.6 - 45.1 - 26.7 - 25.0 - 23.5 nstPZL OFF-state to LOW
propagation delay DIR to B [1] - 41.9 - 37.5 - 33.6 - 32.6 - 32.5 ns
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 12 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
VCC(B)
1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V
Symbol Parameter Conditions
Min Max Min Max Min Max Min Max Min Max
Unit
VCC(A) = 1.65 V to 1.95 V
A to B 2.3 21.1 1.9 19.5 1.9 10.3 1.5 8.0 1.2 7.5 nstPLH LOW to HIGH
propagation delay B to A 2.1 19.4 1.9 19.5 2.0 17.6 1.8 17.1 1.7 16.7 ns
A to B 2.1 19.1 1.8 15.8 1.4 9.4 1.6 7.9 1.5 7.7 nstPHL HIGH to LOW
propagation delay B to A 1.9 16.9 1.8 15.8 1.8 14.2 1.8 13.9 1.6 13.5 ns
DIR to A 2.6 18.9 2.6 18.9 2.6 18.9 2.6 18.9 2.6 18.9 nstPHZ HIGH to OFF-state
propagation delay DIR to B 2.8 26.6 2.8 24.1 2.4 12.7 2.7 11.4 2.2 9.1 ns
DIR to A 2.1 11.6 2.1 11.6 2.1 11.6 2.1 11.6 2.1 11.6 nstPLZ LOW to OFF-state
propagation delay DIR to B 2.2 19.4 2.3 17.6 1.9 10.2 2.4 9.3 2.1 7.9 ns
DIR to A [1] - 38.8 - 37.1 - 27.8 - 26.4 - 24.6 nstPZH OFF-state to HIGH
propagation delay DIR to B [1] - 32.7 - 31.1 - 21.9 - 19.6 - 19.1 ns
DIR to A [1] - 43.5 - 39.9 - 26.9 - 25.3 - 22.6 nstPZL OFF-state to LOW
propagation delay DIR to B [1] - 38.0 - 34.7 - 28.3 - 26.8 - 26.6 ns
VCC(A) = 2.3 V to 2.7 V
A to B 2.0 19.7 2.0 17.6 1.3 9.4 1.1 6.9 0.9 5.3 nstPLH LOW to HIGH
propagation delay B to A 1.8 14.9 1.9 10.3 1.3 9.4 1.2 8.8 0.9 8.3 ns
A to B 2.0 17.4 1.8 14.2 1.2 8.3 1.1 6.0 0.8 5.1 nstPHL HIGH to LOW
propagation delay B to A 1.6 13.0 1.7 9.4 1.2 8.3 1.1 7.7 0.8 6.9 ns
DIR to A 1.8 9.0 1.8 9.0 1.8 9.0 1.8 9.0 1.8 9.0 nstPHZ HIGH to OFF-state
propagation delay DIR to B 2.7 24.8 2.7 23.6 2.2 12.1 2.5 10.3 2.0 7.6 ns
DIR to A 1.5 6.4 1.5 6.4 1.5 6.4 1.5 6.4 1.5 6.4 nstPLZ LOW to OFF-state
propagation delay DIR to B 2.0 16.1 2.2 14.6 1.8 9.9 2.2 9.3 1.6 6.4 ns
DIR to A [1] - 31.0 - 24.9 - 19.3 - 18.1 - 14.7 nstPZH OFF-state to HIGH
propagation delay DIR to B [1] - 26.1 - 24.0 - 15.8 - 13.3 - 11.7 ns
DIR to A [1] - 37.8 - 33.0 - 20.4 - 18.0 - 14.5 nstPZL OFF-state to LOW
propagation delay DIR to B [1] - 26.4 - 23.2 - 17.3 - 15.0 - 14.1 ns
VCC(A) = 3.0 V to 3.6 V
A to B 2.0 18.9 1.8 17.1 1.2 8.8 0.7 6.2 0.6 4.9 nstPLH LOW to HIGH
propagation delay B to A 1.5 13.0 1.5 8.0 1.1 6.9 0.6 6.2 0.5 6.0 ns
A to B 1.9 17.2 1.8 13.9 1.1 7.7 0.7 5.5 0.6 4.4 nstPHL HIGH to LOW
propagation delay B to A 1.5 12.0 1.6 7.9 1.1 6.0 0.7 5.5 0.6 5.0 ns
DIR to A 2.0 8.1 2.0 8.1 2.0 8.1 2.0 8.1 2.4 8.1 nstPHZ HIGH to OFF-state
propagation delay DIR to B 2.6 19.8 2.6 18.2 2.0 11.2 2.4 9.5 1.9 7.0 ns
DIR to A 1.8 6.2 1.8 6.2 1.8 6.2 1.8 6.2 1.8 6.2 nstPLZ LOW to OFF-state
propagation delay DIR to B 2.0 15.0 2.1 13.8 1.7 8.6 2.0 7.9 1.5 5.4 ns
DIR to A [1] - 28.0 - 21.8 - 15.5 - 14.1 - 11.4 nstPZH OFF-state to HIGH
propagation delay DIR to B [1] - 25.1 - 23.3 - 15.0 - 12.4 - 11.1 ns
DIR to A [1] - 31.8 - 26.1 - 17.2 - 15.0 - 12.0 nstPZL OFF-state to LOW
propagation delay DIR to B [1] - 25.3 - 22.0 - 15.8 - 13.6 - 12.5 ns
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 13 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
VCC(B)
1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V
Symbol Parameter Conditions
Min Max Min Max Min Max Min Max Min Max
Unit
VCC(A) = 4.5 V to 5.5 V
A to B 1.9 18.3 1.7 16.7 0.9 8.3 0.6 6.0 0.4 4.3 nstPLH LOW to HIGH
propagation delay B to A 1.4 11.6 1.2 7.5 0.9 5.3 0.6 4.9 0.4 4.3 ns
A to B 2.0 16.9 1.6 13.5 0.9 6.9 0.6 5.0 0.4 3.9 nstPHL HIGH to LOW
propagation delay B to A 1.5 11.9 1.5 7.7 0.8 5.1 0.6 4.4 0.4 3.9 ns
DIR to A 1.5 6.0 1.5 6.0 1.5 6.0 1.5 6.0 1.5 6.0 nstPHZ HIGH to OFF-state
propagation delay DIR to B 2.6 19.1 2.6 17.8 2.0 10.7 2.4 8.8 2.2 6.3 ns
DIR to A 1.2 4.1 1.2 4.1 1.1 4.1 0.9 4.1 0.8 4.1 nstPLZ LOW to OFF-state
propagation delay DIR to B 2.0 14.5 2.1 13.4 1.7 8.2 2.0 7.7 1.6 5.0 ns
DIR to A [1] - 26.1 - 20.9 - 13.5 - 12.6 - 9.3 nstPZH OFF-state to HIGH
propagation delay DIR to B [1] - 22.4 - 20.8 - 12.4 - 10.1 - 8.4 ns
DIR to A [1] - 31.0 - 25.5 - 15.8 - 13.2 - 10.2 nstPZL OFF-state to LOW
propagation delay DIR to B [1] - 22.9 - 19.5 - 12.9 - 11.0 - 9.9 ns
[1] tPZH and tPZL are calculated values using the formula shown in Section 13.4.
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 14 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
11.1. Waveforms and test circuit
001aaj644
nA, nB input
nB, nA output
tPLH
tPHL
GND
VI
VOH
VM
VM
VOL
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 6. The data input (A, B) to output (B, A) propagation delay times
001aae968
tPZL
tPZH
tPHZ
tPLZ
GND
GND
VI
VCCO
VOL
VOH
VM
VM
VM
VX
VY
outputs
disabled
outputs
enabled
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
DIR input
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 7. Enable and disable times
Table 14. Measurement points
Supply voltage Input [1] Output [2]
VCC(A), VCC(B) VMVMVXVY
1.2 V to 1.6 V 0.5VCCI 0.5VCCO VOL + 0.1 V VOH - 0.1 V
1.65 V to 2.7 V 0.5VCCI 0.5VCCO VOL + 0.15 V VOH - 0.15 V
3.0 V to 5.5 V 0.5VCCI 0.5VCCO VOL + 0.3 V VOH - 0.3 V
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 15 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
Test data is given in Table 15.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance.
VEXT = External voltage for measuring switching times.
Fig. 8. Test circuit for measuring switching times
Table 15. Test data
Supply voltage Input Load VEXT
VCC(A), VCC(B) VI [1] Δt/ΔV [2] CLRLtPLH, tPHL tPZH, tPHZ tPZL, tPLZ [3]
1.2 V to 5.5 V VCCI ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2VCCO
[1] VCCI is the supply voltage associated with the data input port.
[2] dV/dt ≥ 1.0 V/ns.
[3] VCCO is the supply voltage associated with the output port.
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 16 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
12. Typical propagation delay characteristics
CL (pF)
0 35
001aai907
14
tPHL
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(2)
(3)
(4)
(5)
(6)
a. HIGH to LOW propagation delay (A to B)
CL (pF)
0 35
001aai908
14
tPLH
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(2)
(3)
(4)
(5)
(6)
b. LOW to HIGH propagation delay (A to B)
CL (pF)
0 35
001aai909
14
tPHL
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(3)
(4)
(5)
(6)
(2)
c. HIGH to LOW propagation delay (B to A)
CL (pF)
0 35
001aai910
14
tPLH
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(6)
(3)
(4)
(2)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig. 9. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 1.2 V
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 17 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
CL (pF)
0 35
001aai911
14
tPHL
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(6)
(3)
(4)
(2)
a. HIGH to LOW propagation delay (A to B)
CL (pF)
0 35
001aai912
14
tPLH
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(6)
(3)
(4)
(2)
b. LOW to HIGH propagation delay (A to B)
CL (pF)
0 35
001aai913
14
tPHL
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(6)
(3)
(4)
(2)
c. HIGH to LOW propagation delay (B to A)
CL (pF)
0 35
001aai914
14
tPLH
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(6)
(3)
(4)
(2)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig. 10. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 1.5 V
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 18 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
CL (pF)
0 35
001aai915
14
tPHL
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(6)
(3)
(4)
(2)
a. HIGH to LOW propagation delay (A to B)
CL (pF)
0 35
001aai916
14
tPLH
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(6)
(3)
(4)
(2)
b. LOW to HIGH propagation delay (A to B)
CL (pF)
0 35
001aai917
14
tPHL
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(6)
(4)
(2)
(3)
c. HIGH to LOW propagation delay (B to A)
CL (pF)
0 35
001aai918
14
tPLH
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(6)
(4)
(2)
(3)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig. 11. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 1.8 V
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 19 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
CL (pF)
0 35
001aai919
14
tPHL
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(4)
(2)
(3)
(6)
a. HIGH to LOW propagation delay (A to B)
CL (pF)
0 35
001aai920
14
tPLH
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(4)
(2)
(3)
(6)
b. LOW to HIGH propagation delay (A to B)
CL (pF)
0 35
001aai921
14
tPHL
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(4)
(2)
(3)
(6)
c. HIGH to LOW propagation delay (B to A)
CL (pF)
0 35
001aai922
14
tPLH
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(4)
(2)
(3)
(6)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig. 12. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 2.5 V
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 20 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
CL (pF)
0 35
001aai923
14
tPHL
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(4)
(2)
(3)
(6)
a. HIGH to LOW propagation delay (A to B)
CL (pF)
0 35
001aai924
14
tPLH
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(4)
(2)
(3)
(6)
b. LOW to HIGH propagation delay (A to B)
CL (pF)
0 35
001aai925
14
tPHL
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(4)
(2)
(3)
(6)
c. HIGH to LOW propagation delay (B to A)
CL (pF)
0 35
001aai926
14
tPLH
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(4)
(2)
(3)
(6)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig. 13. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 3.3 V
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 21 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
CL (pF)
0 35
001aai927
14
tPHL
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(4)
(2)
(3)
(6)
a. HIGH to LOW propagation delay (A to B)
CL (pF)
0 35
001aai928
14
tPLH
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(4)
(2)
(3)
(6)
b. LOW to HIGH propagation delay (A to B)
CL (pF)
0 35
001aai929
14
tPHL
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(4)
(2)
(3)
(6)
c. HIGH to LOW propagation delay (B to A)
CL (pF)
0 35
001aai930
14
tPLH
(ns)
0
2
4
6
8
10
12
5 10 15 20 25 30
(1)
(5)
(4)
(2)
(3)
(6)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig. 14. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 5.0 V
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 22 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
13. Application information
13.1. Unidirectional logic level-shifting application
The circuit given in Fig. 15 is an example of the 74LVC2T45; 74LVCH2T45 being used in a
unidirectional logic level-shifting application.
001aai931
system-1
VCC(A)
1A
2A
GND
1
2
3
4
8
7
6
5
VCC(B)
1B
2B
DIR
74LVC2T45
74LVCH2T45
VCC1
VCC1
VCC2
VCC2
VCC1 VCC2
system-2
Pin numbers not applicable for SOT902-2 package.
Fig. 15. Unidirectional logic level-shifting application
Table 16. Description of unidirectional logic level-shifting application
Pin Name Function Description
1 VCC(A) VCC1 supply voltage of system-1 (1.2 V to 5.5 V)
2 1A OUT output level depends on VCC1 voltage
3 2A OUT output level depends on VCC1 voltage
4 GND GND device GND
5 DIR DIR the GND (LOW level) determines B port to A port
direction
6 2B IN input threshold value depends on VCC2 voltage
7 1B IN input threshold value depends on VCC2 voltage
8 VCC(B) VCC2 supply voltage of system-2 (1.2 V to 5.5 V)
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Product data sheet Rev. 9 — 13 August 2018 23 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
13.2. Bidirectional logic level-shifting application
Fig. 16 shows the 74LVC2T45; 74LVCH2T45 being used in a bidirectional logic level-shifting
application. Since the device does not have an output enable pin, the system designer should take
precautions to avoid bus contention between system-1 and system-2 when changing directions.
001aai932
PULL-UP/DOWN
system-1
VCC(A)
1A
2A
GND
1
2
3
4
8
7
6
5
VCC(B)
1B
2B
DIR
74LVC2T45
74LVCH2T45
PULL-UP/DOWNI/O-1
DIR CTRL
VCC1
I/O-2
DIR CTRL
VCC2
VCC1 VCC2
system-2
Pull-up or pull-down only needed for 74LVC2T45.
Fig. 16. Bidirectional logic level-shifting application
Table 17 gives a sequence that will illustrate data transmission from system-1 to system-2 and then
from system-2 to system-1.
Table 17. Description of bidirectional logic level-shifting application
H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
State DIR CTRL I/O-1 I/O-2 Description
1 H output input system-1 data to system-2
2 H Z Z system-2 is getting ready to send data to
system-1. I/O-1 and I/O-2 are disabled.
The bus-line state depends on bus hold
3 L Z Z DIR bit is set LOW.
I/O-1 and I/O-2 still are disabled.
The bus-line state depends on bus hold
4 L input output system-2 data to system-1
13.3. Power-up considerations
The device is designed such that no special power-up sequence is required other than GND being
applied first.
Table 18. Typicaltotal supply current (ICC(A) + ICC(B))
VCC(B)
VCC(A)
0 V 1.8 V 2.5 V 3.3 V 5.0 V
Unit
0 V 0 < 1 < 1 < 1 < 1 μA
1.8 V < 1 < 2 < 2 < 2 2 μA
2.5 V < 1 < 2 < 2 < 2 < 2 μA
3.3 V < 1 < 2 < 2 < 2 < 2 μA
5.0 V < 1 2 < 2 < 2 < 2 μA
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Product data sheet Rev. 9 — 13 August 2018 24 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
13.4. Enable times
Calculate the enable times for the 74LVC2T45; 74LVCH2T45 using the following formulas:
tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR
bit is switched until an output is expected. For example, if the 74LVC2T45; 74LVCH2T45 initially
is transmitting from A to B, then the DIR bit is switched, the B port of the device must be disabled
before presenting it with an input. After the B port has been disabled, an input signal applied to it
appears on the corresponding A port after the specified propagation delay.
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 25 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
14. Package outline
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT765-1 MO-187
sot765-1_po
07-06-02
16-05-31
Unit
mm
max
nom
min
0.15 0.27 0.23 2.1
0.5
0.4
A
max.
Dimensions (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1
A1A2
0.85
A3bpc D(1) E(2) e HEL
0.4
LpQ v w
1 0.12 0.10.2 0.08
y Z(1)
3.0 0.152.2 0.190.00 0.17 0.08 1.9 0.10.60
3.2 0.402.4 0.21
θ
0
scale
5 mm
detail X
A
y
e
X
v A
bp
w
D
Z
1 4
85
θ
A2
A1
Q
Lp
(A3)
A
L
HE
E
c
pin 1 index
Fig. 17. Package outline SOT765-1 (VSSOP8)
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 26 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
terminal 1
index area
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT833-1 - - -
MO-252
- - -
SOT833-1
07-11-14
07-12-07
DIMENSIONS (mm are the original dimensions)
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1e1
0 1 2 mm
scale
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
UNIT
mm 0.25
0.17
2.0
1.9
0.35
0.27
A1
max b E
1.05
0.95
D e e1L
0.40
0.32
L1
0.50.6
A(1)
max
0.5 0.04
1
8
2
7
3
6
4
5
(2)
4×
(2)
A
Fig. 18. Package outline SOT833-1 (XSON8)
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 27 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT1089
MO-252
sot1089_po
10-04-09
10-04-12
Unit
mm
max
nom
min
0.5 0.04 1.40
1.35
1.30
1.05
1.00
0.95
0.55 0.35
0.35
0.30
0.27
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1 x 0.5 mm SOT1089
A1b L1
0.40
0.35
0.32
0.20
0.15
0.12
D E e e1L
0 0.5 1 mm
scale
terminal 1
index area
E
D
detail X
A
A1
L
L1
b
e1
e
terminal 1
index area
1
4
8
5
(4×)(2)
(8×)(2)
X
Fig. 19. Package outline SOT1089 (XSON8)
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Product data sheet Rev. 9 — 13 August 2018 28 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT902-2 - - -
MO-255
- - -
sot902-2_po
16-07-14
16-11-08
Unit(1)
mm
max
nom
min
0.5 0.05
0.00
1.65
1.60
1.55
1.65
1.60
1.55
0.55 0.5
0.15
0.10
0.05
0.1 0.05
A
0.2
k
Dimensions
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
XQFN8: plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-2
A1b
0.25
0.20
0.15
D E e e1L
0.35
0.30
0.25
L1
0.25
0.20
0.15
L2
0.35
0.30
0.25
L3v w
0.05
y y1
0.05
0 1 2 mm
scale
terminal 1
index area
B AD
E
X
C
y
C
y1
terminal 1
index area
3
L k
L1
L2
b
e1
e
AC Bv
Cw
2
1
5
6
7
metal area
not for soldering
8
k
4
L
L3
A1
A
detail X
Fig. 20. Package outline SOT902-2 (XQFN8)
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 29 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT1116
sot1116_po
10-04-02
10-04-07
Unit
mm
max
nom
min
0.35 0.04 1.25
1.20
1.15
1.05
1.00
0.95
0.55 0.3
0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.2 x 1.0 x 0.35 mm SOT1116
A1b
0.20
0.15
0.12
D E e e1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
E
D
(4×)(2)
(8×)(2)
A1A
e1e1e1
e
L
L1
b
4321
5678
Fig. 21. Package outline SOT1116 (XSON8)
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 30 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT1203
sot1203_po
10-04-02
10-04-06
Unit
mm
max
nom
min
0.35 0.04 1.40
1.35
1.30
1.05
1.00
0.95
0.55 0.35
0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1.0 x 0.35 mm SOT1203
A1b
0.20
0.15
0.12
D E e e1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
E
D
(4×)(2)
(8×)(2)
A
A1
e
L
L1
b
e1e1e1
1
8
2
7
3
6
4
5
Fig. 22. Package outline SOT1203 (XSON8)
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 31 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
15. Abbreviations
Table 19. Abbreviations
Acronym Description
CDM Charged Device Model
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
16. Revision history
Table 20. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC_LVCH2T45 v.9 20180813 Product data sheet - 74LVC_LVCH2T45 v.8
Modifications: The format of this data sheet has been redesigned to comply with the identity guidelines
of Nexperia.
Legal texts have been adapted to the new company name where appropriate.
Type numbers 74LVC2T45GD and 74LVCH2T45GD (SOT996-2) removed.
Package outline drawing (SOT765-1) modified.
74LVC_LVCH2T45 v.8 20130329 Product data sheet - 74LVC_LVCH2T45 v.7
Modifications: For type numbers 74LVC2T45GD and 74LVCH2T45GD XSON8U has changed to
XSON8.
74LVC_LVCH2T45 v.7 20120619 Product data sheet - 74LVC_LVCH2T45 v.6
Modifications: For type numbers 74LVC2T45GM and 74LVCH2T45GM the SOT code has changed to
SOT902-2.
74LVC_LVCH2T45 v.6 20111209 Product data sheet - 74LVC_LVCH2T45 v.5
Modifications: Legal pages updated.
74LVC_LVCH2T45 v.5 20110927 Product data sheet - 74LVC_LVCH2T45 v.4
74LVC_LVCH2T45 v.4 20100820 Product data sheet - 74LVC_LVCH2T45 v.3
74LVC_LVCH2T45 v.3 20100119 Product data sheet - 74LVC_LVCH2T45 v.2
74LVC_LVCH2T45 v.2 20090205 Product data sheet - 74LVC_LVCH2T45 v.1
74LVC_LVCH2T45 v.1 20081118 Product data sheet - -
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 32 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
17. Legal information
Data sheet status
Document status
[1][2]
Product
status [3]
Definition
Objective [short]
data sheet
Development This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification This document contains data from
the preliminary specification.
Product [short]
data sheet
Production This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 33 / 34
Nexperia 74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................2
4. Marking.......................................................................... 2
5. Functional diagram.......................................................3
6. Pinning information......................................................3
6.1. Pinning.........................................................................3
6.2. Pin description............................................................. 4
7. Functional description................................................. 4
8. Limiting values............................................................. 5
9. Recommended operating conditions..........................5
10. Static characteristics..................................................6
11. Dynamic characteristics.............................................9
11.1. Waveforms and test circuit.......................................15
12. Typical propagation delay characteristics..............17
13. Application information........................................... 23
13.1. Unidirectional logic level-shifting application............23
13.2. Bidirectional logic level-shifting application.............. 24
13.3. Power-up considerations......................................... 24
13.4. Enable times............................................................25
14. Package outline........................................................ 26
15. Abbreviations............................................................ 32
16. Revision history........................................................32
17. Legal information......................................................33
© Nexperia B.V. 2018. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 13 August 2018
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved
Product data sheet Rev. 9 — 13 August 2018 34 / 34

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