CAD | USD

LTC628, LTC6269 Datasheet

Linear Technology/Analog Devices

Download PDF Datasheet

Datasheet

LTC6268/LTC6269
1
62689f
For more information www.linear.com/LTC6268
TYPICAL APPLICATION
FEATURES DESCRIPTION
500MHz Ultra-Low Bias
Current FET Input Op Amp
The LTC
®
6268/LTC6269 is a single/dual 500MHz FET-input
operational amplifier with extremely low input bias current
and low input capacitance. It also features low input-
referred current noise and voltage noise making it an ideal
choice for high speed transimpedance amplifiers, CCD
output buffers, and high-impedance sensor amplifiers.
Its low distortion makes the LTC6268/LTC6269 an ideal
amplifier for driving SAR ADCs.
It operates on 3.1V to 5.25V supply and consumes 16.5mA
per amplifier. A shutdown feature can be used to lower
power consumption when the amplifier is not in use.
The LTC6268 single op amp is available in 8-lead SOIC and
6-lead SOT-23 packages. The SOIC package includes two
unconnected pins which can be used to create an input pin
guard ring to protect against board leakage currents. The
LTC6269 dual op amp is available in 8-lead MSOP with
exposed pad and 3mm × 3mm 10-lead DFN packages.
They are fully specified over the –40°C to 85°C and the
–40°C to 125°C temperature ranges.
20kΩ TIA Frequency Response
20kΩ Gain 65MHz Trans-Impedance Amplifier
APPLICATIONS
n Gain Bandwidth Product: 500MHz
n –3dB Bandwidth (A = 1): 350MHz
n Low Input Bias Current:
±3fA Typ. Room Temperature
4pA Max at 125°C
n Current Noise (100kHz): 5.5fA/√Hz
n Voltage Noise (1MHz): 4.3nV/√Hz
n Extremely Low CIN 450fF
n Rail-to-Rail Output
n Slew Rate: 400V/µs
n Supply Range: 3.1V to 5.25V
n Quiescent Current: 16.5mA
n Harmonic Distortion (2VP-P):
–100dB at 1MHz
–80dB at 10MHz
n Operating Temp Range: –40°C to 125°C
n Single in 8-Lead SO-8, 6-Lead TSOT-23 Packages
n Dual in 8-Lead MS8, 3mm × 3mm 10-Lead DFN 10 Packages
n Trans-Impedance Amplifiers
n ADC Drivers
n CCD Output Buffer
n Photomultiplier Tube Post-Amplifier
n Low IBIAS Circuits
L, LT, LT C , LT M, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
+
LTC6268
6268 TA01
2.5V
PARASITIC
FEEDBACK C
2.5V
PD
–2.5V
VOUT = –IPD • 20k
BW = 65MHz
PD = OSI OPTOELECTRONICS, FCI-125G-006
*TWO 40.2kΩ 0603 PACKAGE RESISTORS IN PARALLEL
20kΩ*
IPD
FREQUENCY (MHz)
0.01
40
GAIN (dBΩ)
90
80
70
60
50
100
10 100 10000.1 1
6268 TA02
LTC6268/LTC6269
2
62689f
For more information www.linear.com/LTC6268
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Supply Voltage V+ to V ...........................................5.5V
Input Voltage ...............................V – 0.2V to V+ + 0.2V
Input Current (+IN, –IN)(Note 2) ............................ ±1mA
Input Current (SHDN) ............................................ ±1mA
Output Current (IOUT) (Note 8, 9) ......................... 135mA
Output Short-Circuit Duration (Note 3) ... Thermally Limited
Operating Temperature Range
LTC6268I/LTC6269I .............................40°C to 8C
LTC6268H/LTC6269H ........................ 40°C to 125°C
(Note 1)
1
2
3
4
8
7
6
5
TOP VIEW
SHDN
V+
OUT
V
NC
–IN
+IN
NC
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 120°C/W (NOTE 5)
1
2
3
6
5
4
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
V+
SHDN
–IN
OUT
V
+IN
TJMAX = 150°C, θJA = 192°C/W (NOTE 5)
1
2
3
4
OUTA
–INA
+INA
V
8
7
6
5
V+
OUTB
–INB
+INB
TOP VIEW
MS8E PACKAGE
8-LEAD PLASTIC MSOP
9
V
TJMAX = 150°C, θJA = 40°C/W (NOTE 5)
EXPOSED PAD (PIN 9) IS V, IT IS RECOMMENDED TO SOLDER TO PCB
TOP VIEW
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
10
9
6
7
8
4
5
3
2
1V+
OUTB
–INB
+INB
SDB
OUTA
–INA
+INA
V
SDA
11
V
TJMAX = 150°C, θJA = 43°C/W (NOTE 5)
EXPOSED PAD (PIN 11) IS V, IT IS RECOMMENDED TO SOLDER TO PCB
Specified Temperature Range (Note 4)
LTC6268I/LTC6269I .............................40°C to 8C
LTC6268H/LTC6269H ........................ 40°C to 125°C
Maximum Junction Temperature .......................... 150°C
Storage Temperature Range .................. 6C to 150°C
Lead Temperature (Soldering, 10 sec) ...................30C
LTC6268/LTC6269
3
62689f
For more information www.linear.com/LTC6268
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6268IS6#TRMPBF LTC6268IS6#TRPBF LTGFS 6-Lead Plastic TSOT-23 40°C to 85°C
LTC6268HS6#TRMPBF LTC6268HS6#TRPBF LTGFS 6-Lead Plastic TSOT-23 40°C to 125°C
LTC6268IS8#PBF LTC6268IS8#TRPBF 6268 8-Lead Plastic SOIC 40°C to 85°C
LTC6268HS8#PBF LTC6268HS8#TRPBF 6268 8-Lead Plastic SOIC 40°C to 125°C
LTC6269IMS8E#PBF LTC6269IMS8E#TRPBF LTGFP 8-Lead Plastic MSOP 40°C to 85°C
LTC6269HMS8E#PBF LTC6269HMS8E#TRPBF LTGFP 8-Lead Plastic MSOP 40°C to 125°C
LTC6269IDD#PBF LTC6269IDD#TRPBF LGFN 10-Lead Plastic DD 40°C to 85°C
LTC6269HDD#PBF LTC6269HDD#TRPBF LGFN 10-Lead Plastic DD 40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage VCM = 2.75V
l
–0.7
–2.5
0.2 0.7
2.5
mV
mV
VCM = 4.0V
l
–1.0
–4.5
0.2 1.0
4.5
mV
mV
TC VOS Input Offset Voltage Drift VCM = 2.75V 4 μV/°C
IBInput Bias Current
(Notes 6, 8)
VCM = 2.75V
LTC6268I/LTC6269I
LTC6268H/LTC6269H
l
l
–20
–900
–4
±3 20
900
4
fA
fA
pA
VCM = 4.0V
LTC6268I/LTC6269I
LTC6268H/LTC6269H
l
l
–20
–900
–4
±3 20
900
4
fA
fA
pA
IOS Input Offset Current (Notes 6, 8) VCM = 2.75V
LTC6268I/LTC6269I
LTC6268H/LTC6269H
l
l
–40
–450
–2
±6 40
450
2
fA
fA
pA
enInput Voltage Noise Density, VCM = 2.75V f = 1MHz 4.3 nV/√Hz
Input Voltage Noise Density, VCM = 4.0V f = 1MHz 4.9 nV/√Hz
Input Referred Noise Voltage f = 0.1Hz to 10Hz 13 μVP-P
inInput Current Noise Density, VCM = 2.75V f = 100kHz 5.5 fA/√Hz
Input Current Noise Density, VCM = 4.0V f = 100kHz 5.3 fA/√Hz
RIN Input Resistance Differential >1000
Common Mode >1000
CIN Input Capacitance Differential (DC to 200MHz) 100 fF
Common Mode (DC to 100MHz) 450 fF
CMRR Common Mode Rejection Ratio VCM = 0.5V to 3.2V (PNP Side)
l
72
70
90 dB
dB
VCM = 0V to 4.5V
l
64
52
82 dB
dB
IVR Input Voltage Range Guaranteed by CMRR l0 4.5 V
The l denotes specifications that apply over the full operating
temp erature range, otherwise specifications are at TA = 25°C, VSUPPLY = 5.0V (V+ = 5V, V= 0V, VCM = mid-supply), RL = 1kΩ,
CL = 10pF, VSHDN is unconnected.
5.0V ELECTRICAL CHARACTERISTICS
LTC6268/LTC6269
4
62689f
For more information www.linear.com/LTC6268
The l denotes specifications that apply over the full operating
temp erature range, otherwise specifications are at TA = 25°C, VSUPPLY = 5.0V (V+ = 5V, V= 0V, VCM = mid-supply), RL = 1kΩ,
CL = 10pF, VSHDN is unconnected.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PSRR Power Supply Rejection Ratio VCM = 1.0V, VSUPPLY Ranges from 3.1V to 5.25V
l
78
75
95 dB
dB
Supply Voltage Range l3.1 5.25
AVOpen Loop Voltage Gain VOUT = 0.5V to 4.5V RLOAD = 10k
l
125
40
250 V/mV
V/mV
RLOAD = 100
l
10
2
21 V/mV
V/mV
VOL Output Swing Low (Input Overdrive 30mV)
Measured from VISINK = 10mA
l
80 140
200
mV
mV
ISINK = 25mA
l
130 200
260
mV
mV
VOH Output Swing High (Input Overdrive 30mV)
Measured from V+ISOURCE = 10mA
l
70 140
200
mV
mV
ISOURCE = 25mA
l
160 270
370
mV
mV
ISC Output Short Circuit Current (Note 9)
l
60
40
90 mA
mA
ISSupply Current Per Amplifier
l
15
9
16.5 18
23
mA
mA
Supply Current in Shutdown
(Per Amplifier)
l
0.39 0.85
1.2
mA
mA
ISHDN Shutdown Pin Current VSHDN = 0.75V
VSHDN =1.50V
l
l
–12
–12
2
2
12
12
µA
µA
VIL SHDN Input Low Voltage Disable l0.75 V
VIH SHDN Input High Voltage Enable. If SHDN is Unconnected, Amp is Enabled l1.5 V
tON Turn On Time, Delay from SHDN Toggle to
Output Reaching 90% of Target
SHDN Toggle from 0V to 2V, AV = 1 580 ns
tOFF Turn Off Time, Delay from SHDN Toggle to
Output High Z
SHDN Toggle from 2V to 0V, AV = 1 480 ns
BW –3dB Closed Loop Bandwidth AV = 1 350 MHz
GBW Gain-Bandwidth Product f = 10MHz 400 500 MHz
tSSettling Time, 1V to 4V, Unity Gain 0.1% 17 ns
SR+ Slew Rate+ AV = 6 (RF = 499, RG = 100)
VOUT = 0.5V to 4.5V, Measured 20% to 80%,
CLOAD = 10pF
l
300
200
400
V/µs
V/µs
SR– Slew Rate– AV = 6 (RF = 499, RG = 100)
VOUT = 4.5V to 0.5V, Measured 80% to 20%,
CLOAD = 10pF
l
180
130
260
V/µs
V/µs
FPBW Full Power Bandwidth (Note 7) 4VP-P 21 MHz
HD Harmonic Distortion(HD2/HD3) A = 1, 10MHz. 2VP-P, VCM = 1.75V, RL = 1k –81/–90 dB
THD+N Total Harmonic Distortion and Noise A = 1, 10MHz. 2VP-P, VCM = 1.75V, RL = 1k 0.01
–79.6
%
dB
ILEAK Output Leakage Current in Shutdown VSHDN = 0V, VOUT = 0V
VSHDN = 0V, VOUT = 5V
400
400
nA
nA
5.0V ELECTRICAL CHARACTERISTICS
LTC6268/LTC6269
5
62689f
For more information www.linear.com/LTC6268
3.3V ELECTRICAL CHARACTERISTICS
The l denotes specifications that apply over the full operating
temp erature range, otherwise specifications are at TA = 25°C, VSUPPLY = 3.3V (V+ = 3.3V, V = 0V, VCM = mid-supply), RL = 1kΩ,
CL = 10pF, VSHDN is unconnected.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage VCM = 1.0V
l
–0.7
–2.5
0.2 0.7
2.5
mV
mV
VCM = 2.3V
l
–1.0
–4.5
0.2 1.0
4.5
mV
mV
TC VOS Input Offset Voltage Drift VCM = 1.0V 4 µV/C
IBInput Bias Current (Notes 6, 8) VCM = 1.0V
LTC6268I/LTC6269I
LTC6268H/LTC6269H
l
l
–20
–900
–4
±3 20
900
4
fA
fA
pA
VCM = 2.3V
LTC6268I/LTC6269I
LTC6268H/LTC6269H
l
l
–20
–900
–4
±3 20
900
4
fA
fA
pA
IOS Input Offset Current (Notes 6, 8) VCM = 1.0V
LTC6268I/LTC6269I
LTC6268H/LTC6269H
l
l
–40
–450
–2
±6 40
450
2
fA
fA
pA
enInput Voltage Noise Density, VCM =1.0V f = 1MHz 4.3 nV/√Hz
Input Voltage Noise Density, VCM = 2.3V f = 1MHz 4.9 nV/√Hz
Input Referred Noise Voltage f = 0.1Hz to 10Hz 13 μVP-P
inInput Current Noise Density, VCM = 1.0V f = 100kHz 5.6 fA/√Hz
Input Current Noise Density, VCM = 2.3V f = 100kHz 5.3 fA/√Hz
RIN Input Resistance Differential
Common Mode
>1000
>1000
CIN Input Capacitance Differential (DC to 200MHz)
Common Mode (DC to 100MHz)
100
450
fF
fF
CMRR Common Mode Rejection Ratio VCM = 0.5V to 1.2V (PNP Side)
l
63
60
100 dB
dB
VCM = 0V to 2.8V (Full Range)
l
60
50
77 dB
dB
IVR Input Voltage Range Guaranteed by CMRR l0 2.8 V
AVOpen Loop Voltage Gain VOUT = 0.5V to 2.8V RLOAD = 10k
l
80
40
200 V/mV
V/mV
RLOAD = 100
l
10
2
18 V/mV
V/mV
VOL Output Swing Low
(Input Overdrive 30mV).
Measured from V
ISINK = 10mA
l
80 140
200
mV
mV
ISINK = 25mA
l
140 200
260
mV
mV
VOH Output Swing High
(Input Overdrive 30mV).
Measured from V+
ISOURCE = 10mA
l
80 140
200
mV
mV
ISOURCE = 25mA
l
170 270
370
mV
mV
ISC Output Short Circuit Current (Note 9)
l
50
35
80 mA
mA
ISSupply Current per Amplifier
l
14.5
9
16 17.5
23
mA
mA
LTC6268/LTC6269
6
62689f
For more information www.linear.com/LTC6268
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply Current in Shutdown
(Per Amplifier)
l
0.23 0.6
0.8
mA
mA
ISHDN Shutdown Pin Current VSHDN = 0.75V
VSHDN = 1.5V
l
l
–12
–12
2
2
12
12
µA
µA
VIL SHDN Input Low Voltage Disable l0.75 V
VIH SHDN Input High Voltage Enable. If SHDN is Unconnected, Amp Is Enabled l1.5 V
tON Turn On Time, Delay from SHDN Toggle
to Output Reaching 90% of Target
SHDN Toggle from 0V to 2V 710 ns
tOFF Turn Off Time, Delay from SHDN Toggle
to Output High Z
SHDN Toggle from 2V to 0V 620 ns
BW –3dB Closed Loop Bandwidth AV = 1 350 MHz
GBW Gain-Bandwidth Product f = 10MHz 370 420 MHz
SR+ Slew Rate+ AV = 6 (RF = 499, RG = 100),
VOUT = 0.5V to 2.8V, Measured 20% to 80%,
CLOAD = 10pF
l
300
200
400
V/µs
V/µs
SR– Slew Rate– AV = 6 (RF = 499, RG = 100),
VOUT = 2.8V to 0.5V, Measured 80% to 20%,
CLOAD = 10pF
l
180
130
260
V/µs
V/µs
FPBW Full Power Bandwidth (Note 7) 2VP-P 40 MHz
HD Harmonic Distortion(HD2/HD3) A = 1, 10MHz. 1VP-P, VCM = 1.65V, RL = 1k –81/–90 dB
THD+N Total Harmonic Distortion and Noise A = 1, 10MHz. 1VP-P, VCM = 1.65V, RL = 1k 0.01
–78
%
dB
3.3V ELECTRICAL CHARACTERISTICS
The l denotes specifications that apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VSUPPLY = 3.3V (V+ = 3.3V, V = 0V, VCM = mid-supply) RL = 1kΩ,
CL = 10pF, VSHDN is unconnected.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The inputs are protected by two series connected ESD protection
diodes to each power supply. The input current should be limited to less
than 1mA. The input voltage should not exceed 200mV beyond the power
supply.
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely.
Note 4: The LTC6268I/LTC6269I is guaranteed to meet specified
performance from –40°C to 85°C. The LTC6268H/LTC6269H is guaranteed
to meet specified performance from –40°C to 125°C.
Note 5: Thermal resistance varies with the amount of PC board metal
connected to the package. The specified values are for short traces
connected to the leads.
Note 6: The input bias current is the average of the currents into the
positive and negative input pins. Typical measurement is for S8 package.
Note 7: Full Power Bandwidth is calculated from slew rate using the
following equation: FPBW = SR/(2π • VPEAK)
Note 8: This parameter is specified by design and/or characterization and
is not tested in production.
Note 9: The LTC6268/LTC6269 is capable of producing peak output
currents in excess of 135mA. Current density limitations within the
IC require the continuous current supplied by the output (sourcing or
sinking) over the operating lifetime of the part be limited to under 135mA
(Absolute Maximum).
LTC6268/LTC6269
7
62689f
For more information www.linear.com/LTC6268
TYPICAL PERFORMANCE CHARACTERISTICS
Input Offset Drift Distribution
Input Offset Voltage
vs Common Mode Voltage
Input Offset Voltage
vs Supply Voltage
Input Offset Voltage
vs Output Current PSRR vs Frequency CMRR vs Frequency
Input Offset Voltage Distribution Input Offset Voltage Distribution
Input Offset Voltage
vs Temperature
TA = 25°C, unless otherwise noted.
TEMPERATURE (°C)
–50
–1
VOS (mV)
1.5
1
0.5
0
–0.5
2
–30 –10 90 110 130 15010 5030 70
6268 G03
VS = ±2.5V VCM = 1.0V
VCM = 0.25V
DISTRIBUTION (µV/°C)
NUMBER OF UNITS
0
6268 G04
–8 –6 –4 –2 2 4 6 8 10
0
2
1
4
3
6
5
9
8
7
11
10 H-GRADE
I-GRADE
VS = ±2.5V
VCM = 0.25V
VCM (V)
–2.5
–1
VOS (mV)
0.8
0.4
0.6
0
0.2
–0.8
–0.6
–0.4
–0.2
1
–1.25 1.25 2.50
6268 G05
VS = ±2.5V
VS (V)
3
–1
VOS (mV)
0.6
0.8
0
–0.8
–0.6
–0.4
–0.2
0.2
0.4
1
3.5 5 5.54 4.5
6268 G06
VS = 0V, VS+ = 3.1V to 5.25V
VCM = 1V
OUTPUT CURRENT (mA)
–100
–0.20
VOS (mV)
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
–80 –60 40 60 80 10040 0–20 20
6268 G07
VCM = 1.5V
VS = ±2.5V
VCM = 0.25V
FREQUENCY (MHz)
0.01
–20
PSRR (dB)
80
60
40
20
0
100
0.1 100 10001 10
6268 G08
VS = ±2.5V
VCM = 0.25V
–PSRR
+PSRR
FREQUENCY (MHz)
0.01
0
CMRR (dB)
100
80
60
40
20
120
0.1 10 100 10001
6268 G09
VS = ±2.5V
VCM = 0.25V
0
250
200
150
100
50
300
6268 G01
VS = ±2.5V
VCM = 0.25V
–0.4 –0.3 0.2 0.3 0.4 0.5 0.6–0.2 –01 00.1
VOS (mV)
0
200
150
100
50
250
6268 G02
VS = ±2.5V
VCM = 1.5V
–0.4 –0.3 0.2 0.3 0.4 0.5 0.6–0.2 –01 00.1
VOS (mV)
LTC6268/LTC6269
8
62689f
For more information www.linear.com/LTC6268
TYPICAL PERFORMANCE CHARACTERISTICS
Output Saturation Voltage
vs Load Current (Output Low)
Output Saturation Voltage
vs Load Current (Output High)
Output Short Circuit Current
vs Supply Voltage
Input Referred Voltage Noise
Wide Band Input Referred
Voltage Noise
Input Bias Current vs Common
Mode Voltage
Input Bias Current vs Supply
Voltage Input Bias Current vs Temperature
TA = 25°C, unless otherwise noted.
0.1Hz to 10Hz
Output Voltage Noise
–IN
+IN
COMMON MODE VOLTAGE (V)
0.0
–300
INPUT BIAS CURRENT (fA)
INPUT BIAS CURRENT (fA)
300
200
VS = 5V
100
0
–100
–200
–10.0
10.0
8.0
6.0
4.0
2.0
0.0
–2.0
–4.0
–6.0
–8.0
1.0 4.0 5.02.0 3.0
6268 G10
SUPPLY VOLTAGE (V)
3.0
–10
INPUT BIAS CURRENT (fA)
–2
–1
–4
–3
–5
–7
–6
–9
–8
0
3.5 5.0 5.54.0 4.5
6268 G11
VS = 3.1V TO 5.25V
VCM = 1.0V
+IN
–IN
TEMPERATURE (°C)
25
–200
CURRENT (fA)
1400
1000
1200
800
400
600
0
200
1600
45 105 12565 85
6268 G12
–IN
+IN
VS = ±2.5V
VCM = 0.25V
LOAD CURRENT (mA)
0.0
0
OUTPUT SATURATION VOLTAGE (mV)
160
120
40
80
200
10.05.0 20.0 25.015.0
6268 G13
VS = ±2.5V
VCM = 0.25V
TA = –55°C
TA = 25°C
TA = 125°C
LOAD CURRENT (mA)
0.0
–280
OUTPUT SATURATION VOLTAGE (mV)
–40
–120
–200
–240
–80
–160
0
5.0 20.0 25.010.0 15.0
6268 G14
VS = ±2.5V
VCM = 0.25V
TA = –55°C
TA = 25°C
TA = 125°C VS = ±2.5V
VCM = 0.25V
VS (V)
3.0
–200
ISC (mA)
150
0
–100
–150
50
100
–50
200
3.5 5.0 5.54.0 4.5
6268 G15
SINKING
SOURCING
TA = –55°C
TA = 25°C
TA = 125°C
FREQUENCY (Hz)
10k
0
VOLTAGE NOISE (nV/√Hz)
9
8
7
6
5
4
3
2
1
10
1M100k
6268 G16
VS = ±2.5V
VCM = 0.25V
FREQUENCY (MHz)
0 20 40 60 80
0
VOLTAGE NOISE (nV/√Hz)
5
4
3
2
1
6
100
6268 G17
VS = ±2.5V
VCM = 0.25V
TIME (s)
0123456789
–20
VOLTAGE NOISE (µV)
16
12
8
4
–16
–12
–8
–4
0
20
10
6268 G18
VS = ±2.5V
VCM = 0.25V
LTC6268/LTC6269
9
62689f
For more information www.linear.com/LTC6268
0.1Hz to 10Hz Output Voltage
Noise
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Output Impedance vs Frequency Harmonic Distortion vs Frequency
Harmonic Distortion vs Amplitude
Harmonic Distortion vs Amplitude
50mV Step Response 50mV Step Response
Input Referred Current Noise Gain and Phase vs Frequency
TIME (s)
0123456789
–20
VOLTAGE NOISE (µV)
16
12
8
4
–16
–12
–8
–4
0
20
10
6268 G19
VS = ±2.5V
VCM = 1.5V
FREQUENCY (MHz)
1 10
0.1
CURRENT NOISE (pA/√Hz)
10
1
100
100
6268 G20
VS = ±2.5V
VCM = 0.25V
FREQUENCY (MHz)
0.1
–30
GAIN (dB)
PHASE
50
30
20
10
0
40
–10
–20
60
–180
–20
–60
–80
–100
–120
–40
–140
–160
0
1 100 100010
6268 G21
VS = ±2.5V
VCM = 0.25V
A = 1000
RL = 1k, CL = 0pF
RL = 1k, CL = 10pF
GAIN
PHASE
FREQUENCY (MHz)
0.001
0.001
OUTPUT IMPEDANCE (Ω)
1
0.1
10
0.01
1000
100
0.01 10 100 10000.1 1
6268 G22
VS = ±2.5V
VCM = 0.25V
AV = 1
AV = 10
AV = 100
FREQUENCY (MHz)
0.1
–140
DISTORTION (dB)
–40
–60
–80
–100
–120
–20
101
6268 G23
VS = ±2.5V
VOUT = 2VP-P
RL = 1k
AV = 1
VCM = –0.75V
2ND
3RD
AMPLITUDE (VP-P)
0.5
–140
DISTORTION (dB)
–40
–60
–80
–100
–120
–20
21 1.5
6268 G24
VS = ±2.5V
VCM = –0.75V
RL = 1k
AV = 1
fO = 1MHz
2ND HD
3RD HD
AMPLITUDE (VP-P)
0.25
–140
DISTORTION (dB)
–40
–60
–80
–100
–120
–20
21 1.51.250.750.5 1.75
6268 G25
2ND HD
3RD HD
VS = ±2.5V
VCM = –0.75V
RL = 1k
AV = 1
fO = 10MHz
AV = 1
VS = 0, 5V
VCM = 0.5V, 2.5V, 4.5V
RLOAD = 1k
TIME (nS)
0
–30
–20
–10
0
VOUT (mV)
70
40
20
10
50
60
30
80
105454035 50252015 30
6268 G26
VCM = 0.5V
VCM = 2.5V
VCM = 4.5V
AV = 1
VS = 0, 5V
VCM = 0.5V, 2.5V, 4.5V
RLOAD = 1k, CLOAD = 10pF
TIME (nS)
0
–30
–20
–10
0
VOUT (mV)
70
40
20
10
50
60
30
80
105454035 50252015 30
6268 G26a
VCM = 0.5V
VCM = 2.5V
VCM = 4.5V
LTC6268/LTC6269
10
62689f
For more information www.linear.com/LTC6268
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Supply Voltage
Supply Current vs Shutdown
Voltage
Supply Current vs Shutdown
Voltage
TA = 25°C, unless otherwise noted.
SUPPLY VOLTAGE (V)
3.0
0
SUPPLY CURRENT (mA)
30
15
18
21
24
27
12
9
6
3
3.5 5.0 5.54.0 4.5
6268 G28
TA = –55°C
TA = 25°C
TA = 125°C
VS = 0V
VCM = 1V
AV = 1
SHUT DOWN VOLTAGE (V)
0.0
0
SUPPLY CURRENT (mA)
25
15
20
10
5
1.5 2.00.5 1.0
6268 G29
VS = 0V, 5V
VCM = 2.75V
AV = 1
TA = –55°C
TA = 25°C
TA = 125°C
SHUT DOWN VOLTAGE (V)
0.0
0
SUPPLY CURRENT (mA)
25
15
20
10
5
1.5 2.00.5 1.0
6268 G30
VS = 0V, 3.1V
VCM = 1V
AV = 1
TA = –55°C
TA = 25°C
TA = 125°C
Large Signal Response
TIME (nS)
0
–2.5
–3.0
VOUT (V)
2.0
1.5
1.0
0.5
0.0
–0.5
–1.0
–2.0
–1.5
3.0
2.5
20 80 10040 60
6268 G27
VS = ±2.5V, AV = 1, RLOAD = 1k
CLOAD = 0pF CLOAD = 10pF
LTC6268/LTC6269
11
62689f
For more information www.linear.com/LTC6268
PIN FUNCTIONS
–IN: Inverting Input of the Amplifier. The voltage range of
this pin is from V to V+ –0.5V.
+IN: Non-Inverting Input. The voltage range of this pin is
from V to V+ –0.5V.
V+: Positive Power Supply. Total supply (V+V) voltage
is from 3.1V to 5.25V. Split supplies are possible as long
as the total voltage between V+ and V is between 3.1V and
5.25. A bypass capacitor of 0.1µF should be used between
V+ to ground as close to the pin as possible.
V: Negative Power Supply. Normally tied to ground, it
can also be tied to a voltage other than ground as long
as the voltage difference between V+ and V is between
3.1V and 5.25V. If it is not connected to ground, bypass
it to ground with a capacitor of 0.1µF as close to the pin
as possible.
SHDN, SDA, SDB: Active Low op amp shutdown, threshold
is 0.75V above the negative supply, V. If left unconnected,
the amplifier is enabled.
OUT: Amplifier Output.
NC: Not connected. May be used to create a guard ring
around the input to guard against board leakage currents.
See Applications Information section for more details.
V
V+
D7
D6 Q7
Q5 Q6
Q3 Q4
BUFFER
I0
C0
Q1
D4
Q2 D5
OUT
Q9
Q8
–IN
+IN
SD
ESD_D2
ESD_D0
ESD_D1
ESD_D3
INPUT REPLICA
INPUT REPLICA
CMOS INPUT
BUFFER
REFERENCE
GENERATION
COMPLEMENTARY
INPUT STAGE
CASCODE STAGE
6268 BD
SIMPLIFIED SCHEMATIC
LTC6268 Simplified Schematic Diagram
LTC6268/LTC6269
12
62689f
For more information www.linear.com/LTC6268
OPERATION
The LTC6268 input signal range is specified from the
negative supply to 0.5V below the positive power supply,
while the output can swing from rail-to-rail. The schematic
above depicts a simplified schematic of the amplifier.
The input pins drive a CMOS buffer stage. The CMOS buffer
stage creates replicas of the input voltages to boot strap
the protection diodes. In turn, the buffer stage drives a
complementary input stage consisting of two differential
amplifiers, active over different ranges of input common
mode voltage. The main differential amplifier is active with
input common mode voltages from the negative power
supply to approximately 1.55V below the positive supply,
with the second amplifier active over the remaining range
to 0.5V below the positive supply rail. The buffer and
output bias stage uses a special compensation technique
ensuring stability of the op amp. The common emitter
topology of output transistors Q1/Q2 enables the output
to swing from rail-to-rail.
APPLICATIONS INFORMATION
Figure 1. Simplified TIA Schematic
For a trans-impedance amplifier (TIA) application such as
shown in Figure 1, all three of these op amp parameters,
plus the value of feedback resistance RF, contribute to noise
behavior in different ways, and external components and
traces will add to CIN. It is important to understand the
impact of each parameter independently. Input referred
voltage noise (eN) consists of flicker noise (or 1/f noise),
which dominates at lower frequencies, and thermal noise
which dominates at higher frequencies. For LTC6268, the
1/f corner, or transition between 1/f and thermal noise,
is at 80kHz. The iN and RF contributions to input referred
noise current at the minus input are relatively straight
forward, while the eN contribution is amplified by the noise
gain. Because there is no gain resistor, the noise gain is
calculated using feedback resistor(RF) in conjunction
with impedance of CIN as (1 + 2π RF • CIN • Freq), which
increases with frequency. All of the contributions will be
limited by the closed loop bandwidth. The equivalent input
current noise is shown in Figures 2-5, where eN represents
contribution from input referred voltage noise (eN), iN
represents contribution from input referred current noise
(iN), and RF represents contribution from feedback resistor
(RF). TIA gain (RF) and capacitance at input (CIN) are also
shown on each figure. Comparing Figures 2 & 3, and 4 &
5 for higher frequencies, eN dominates when CIN is high
(5pF) due to the amplification mentioned above while iN
dominates when CIN is low (1pF). At lower frequencies, the
+
CF
RF
CIN
GND
IN
OUT
6268 F01
Noise
To minimize the LTC6268’s noise over a broad range of
applications, careful consideration has been placed on
input referred voltage noise (eN), input referred current
noise (iN) and input capacitance CIN.
LTC6268/LTC6269
13
62689f
For more information www.linear.com/LTC6268
RF contribution dominates for 10k and 100k. Since wide
band eN is 4.3nV/√Hz (see typical performance characterit-
ics), RF contribution will become a lesser factor at lower
frequencies if RF is less than 1.16kΩ as indicated by the
following equation:
eN/R
F
4kT /RF
1
FREQUENCY (MHz)
0
0
NOISE DENSITY (pA/√Hz)
4
3
2
1
5
60 80 10020 40
6268 F02
TOTAL
RF
iN
eN
RF = 10k
CIN = 1pF
CF = 0.28pF
APPLICATIONS INFORMATION
Figure 2
Figure 3
Figure 4
Figure 5
FREQUENCY (Hz)
0
0
NOISE DENSITY (pA/√Hz)
4
3
2
1
5
60 80 10020 40
6268 F04
RF = 100k
CIN = 1pF
CF = 0.08pF
TOTAL
RF
iN
eN
FREQUENCY (MHz)
0
0
NOISE DENSITY (pA/√Hz)
4
3
2
1
5
60 80 10020 40
6268 F05
RF = 100k
CIN = 5pF
CF = 0.18pF
TOTAL
RF
iN
eN
RF = 10k
CIN = 5pF
CF = 0.56pF
FREQUENCY (MHz)
0
0
NOISE DENSITY (pA/√Hz)
4
3
2
1
5
60 80 10020 40
6268 F03
TOTAL
RF
iN
eN
Optimizing the Bandwidth for TIA Application
The capacitance at the inverting input node can cause
amplifier stability problems if left unchecked. When the
feedback around the op amp is resistive (RF), a pole will
be created with RF||CIN. This pole can create excessive
phase shift and possibly oscillation. Referring to Figure
1, the response at the output is:
R
F
1+2ζs
ω
+S2
ω
2
LTC6268/LTC6269
14
62689f
For more information www.linear.com/LTC6268
APPLICATIONS INFORMATION
Where RF is the DC gain of the TIA, ω is the natural fre-
quency of the closed loop, which can be expressed as:
ω=2πGBW
RF(CIN +CF)
ζ is the damping factor of the loop, which can be ex-
pressed as
ζ=1
2
1
2πGBW RF(CIN +CF)
+RFCF+CIN +CF
1+AO
+2πGBW
RFCIN +CF
( )
Where CIN is the total capacitance at the inverting input
node of the op amp, and GBW is the gain bandwidth of
the op amp. There are two regions that the system will be
stable regardless of CF. The first region is when RF is less
than 1/(4π∙CIN∙GBW). In this region, the pole produced
by the feedback resistor and CIN is at a high frequency
which does not cause stability problems. The second
region is where:
RF>AO2
πGBW •C
Where AO is the DC open loop gain of the op amp, and the
pole formed by RF CIN is the dominant pole.
For RF between these two regions, the small capacitor
CF in parallel with RF can introduce enough damping to
stabilize the loop. By assuming CIN >> CF, the following
condition needs to be met for CF,
CF>CIN
πGBW RF
The above condition implies that higher GBW will require
lower feedback capacitance CF, which will have higher loop
bandwidth. Table 1 shows the optimal CF for RF of 10
and 100kΩ and CIN of 1pF and 5pF.
Table 1. Min CF
RFCIN = 1pF CIN = 5pF
10kΩ 0.25pF 0.56pF
100kΩ 0.08pF 0.18pF
Achieving Higher Bandwidth with Higher Gain TIAs
Good layout practices are essential to achieving best re-
sults from a TIA circuit. The following two examples show
drastically different results from an LTC6268 in a 499
TIA. (See Figure 6.) The first example is with an 0603 re-
sistor in a basic circuit layout. In a simple layout, without
expending a lot of effort to reduce feedback capacitance,
the bandwidth achieved is about 2.5MHz. In this case,
the bandwidth of the TIA is limited not by the GBW of the
LTC6268, but rather by the fact that the feedback capaci-
tance is reducing the actual feedback impedance (the TIA
gain itself) of the TIA. Basically, it’s a resistor bandwidth
limitation. The impedance of the 499is being reduced
by its own parasitic capacitance at high frequency. From
the 2.5MHz bandwidth and the 499 low frequency
gain, we can estimate the total feedback capacitance as
C = 1/(2π • 2.5MHz • 499kΩ) = 0.13pF. That’s fairly low,
but it can be reduced further.
Figure 6. LTC6268 and Low Capacitance Photodiode in a 499kΩ TIA
PARASITIC
FEEDBACK C
499k
–2.5
6268 F06
K
A
PD
CASE
–2.5
PD: OSI FCI-125G-006
+2.5
IPD
VOUT
+
LTC6268
LTC6268/LTC6269
15
62689f
For more information www.linear.com/LTC6268
With some extra layout techniques to reduce feedback
capacitance, the bandwidth can be increased. Note that
we are increasing the effectivebandwidth” of the 499
resistance. One of the main ways to reduce capacitance is
to increase the distance between the plates, in this case the
plates being the two endcaps of the component resistor.
For that reason, it will serve our purposes to go to a longer
resistor. An 0805 is longer than an 0603, but its endcaps are
also larger in area, increasing capacitance again. However,
increasing distance between the endcaps is not the only way
to decrease capacitance, and the extra distance between
the resistor endcaps also allows the easy application of
another technique to reduce feedback capacitance. A very
powerful method to reduce plate to plate capacitance is to
shield the E field paths that give rise to the capacitance. In
this particular case, the method is to place a short ground
trace between the resistor pads, near the TIA output end.
APPLICATIONS INFORMATION
Figure 8. A Normal Layout at Left and a Field-Shunting Layout at Right. Simply Adding a Ground Trace Under the Feedback Resistor
Does Much to Shunt Field Away from the Feedback Side and Dumps It to Ground. Note That the Dielectric Constant of Fr4 and Ceramic
Is Typically 4, so Most of the Capacitance Is in the Solids and Not Through the Air. (Reduced Pad Size On Right Is Not Shown.)
CERAMIC R SUBSTRATE RESISTIVE
ELEMENT
E FIELD C
ENDCAP
K
A
G
–2.5
FR4
IPD
VOUT
+
LTC6268
E E
CERAMIC R SUBSTRATE RESISTIVE
ELEMENT
EXTRA GND
TRACE UNDER
RESISTOR
TAKE E FIELD TO GND,
MUCH LOWER C
ENDCAP
6268 F08
K
A
G
–2.5
FR4
IPD
VOUT
+
LTC6268
Such a ground trace shields the output field from getting
to the summing node end of the resistor and effectively
shunts the field to ground instead. Keeping the trace close
to the output end increases the output load capacitance
very slightly. See Figure 8 for a pictorial representation.
Figure 9 shows the dramatic increase in bandwidth simply
by careful attention to low capacitance methods around
the feedback resistance. Bandwidth was raised from
2.5MHz to 11.2MHz, a factor greater than 4. Methods
implemented were two:
1) Minimal pad sizing. Check with your board assembler
for minimum acceptable pad sizing, or assemble this
resistor using other means, and
2) Shield the feedback capacitance using a ground trace
under the feedback resistor near the output side.
Figure 7. Frequency Response of 499kΩ TIA without
Extra Effort to Reduce Feedback Capacitance is 2.5MHz
Figure 9. LTC6268 in a 499kΩ TIA with extra Layout Effort
to Reduce Feedback Capacitance Achieves 11.2MHz BW
LTC6268/LTC6269
16
62689f
For more information www.linear.com/LTC6268
APPLICATIONS INFORMATION
High Impedance Buffer
The very high input impedance of the LTC6268 makes it
ideal for buffering high impedance or capacitive sources.
The circuit of Figure 10 shows the LTC6268 applied as a
buffer, after a simple RC filter. The RLC network after the
buffer acts as an absorptive filter to avoid excessive time
domain reflections of the ADC glitches. The 2.048V refer-
ence establishes a midpoint inputzero” reference voltage.
The LT1395 high speed current feedback amplifier and its
associated resistor network attenuate the buffered signal
and render it differential by forcing the common mode
to virtual ground (the VCM voltage provided by the ADC).
Figure 10. LTC6268 as a High-Z Buffer Driving an LT1395 as
a Single-Ended to Differential Converter Into a 16-Bit ADC
AIN+
AIN
LTC2269
1.8V
D15
D0
VDD
1.8V
OVDD
• • •
LTC2269 16-BIT 20 Msps ADC
6268 F10
VCM
10MHz
CLOCK
CLOCK
CONTROL
OUTPUT
DRIVERS
OGNDGND
S/H 16-BIT
ADC CORE
LTC6655-2.048
VIN
VOUT_s
VOUT_F
GND
SHDN
VIN
VIN = 2.048V
±1.7V FS
VREF
R2
75Ω
R1
49.9Ω
R6
100Ω
R7
100Ω
R4
49.9Ω
R10
75Ω
R16
49.9Ω
R17
49.9Ω
R15
402Ω
R13
825Ω
R18
49.9Ω
R11
75Ω
R8
200Ω
L4
100nH
L3
100nH
C5
.01µF
R14
402Ω
R12
825Ω
R5
49.9Ω
R9
200Ω
C2
10pF
C3
10pF
C4
100µF
CIN
0.1µF C4
0.1µF
L1
100nH
L2
100nH
+V
+V
R3
10M
C1
22pF
U1
+
LTC6268
LT1395
U2
+V
+V = 5V
–V = –5V –V
+
+
+
LTC6268/LTC6269
17
62689f
For more information www.linear.com/LTC6268
Figure 11. Sampled Time Domain
Response of the Circuit of Figure 10
APPLICATIONS INFORMATION
Figure 11 shows the time domain response of a 10.101MHz
3VP-P input square wave, sampled at 10Msps, just 1ns
slower than the waveform rate. At this rate, the waveform
appears reconstructed at a rate of 1ns per sample, allowing
for a more immediate view of the settling characteristics,
even though each sample is really 100ns later.
Maintaining Ultralow Input Bias Current
Leakage currents into high impedance signal nodes can
easily degrade measurement accuracy of fA signals. High
temperature applications are especially susceptible to these
issues. For humid environments, surface coating may be
necessary to provide a moisture barrier.
There are several factors to consider in a low input bias
current circuit. At the femtoamp level, leakage sources can
come from unexpected sources including adjacent signals
on the PCB, both on the same layer and from internal
layers, any form of contamination on the board from the
assembly process or the environment, other components
on the signal path and even the plastic of the device pack-
age. Care taken in the design of the system can mitigate
these sources and achieve excellent performance.
Figure 12. Example Layout of Inverting Amplifier
(or Trans-Impedance) with Leakage Guard Ring
(a)
(b)
HIGH-Z
SENSOR
(R
IN
)
LOW IMPEDANCE
NODE ABSORBS
LEAKAGE CURRENT
GUARD RING
LEAKAGE
CURRENT
NC
+IN
NC
–IN V
+
V
SD
OUT
NO LEAKAGE CURRENT. V
–IN
= V
GRD
§
AVOID DISSIPATING SIGNIFICANT AMOUNTS OF POWER IN THIS RESISTOR.
IT WILL GENERATE THERMAL GRADIENTS WITH RESPECT TO THE INPUT PINS
AND LEAD TO THERMOCOUPLE-INDUCED ERROR.
V
BIAS
V
–IN
R
F§
6268 F12
LTC6268
S8
NO SOLDER
MASK OVER
GUARD RING
+
GUARD RING
LTC6268
LEAKAGE
CURRENT
LEAKAGE CURRENT IS ABSORBED BY GROUND INSTEAD OF
CAUSING A MEASUREMENT ERROR.
V
OUT
V
+
V
HIGH-Z SENSOR
R
F
V
BIAS
+
V
IN
R
IN
The choice of device package should be considered because
although each has the same die internally, the pin spacing
and adjacent signals influence the input bias current. The
LTC6268/LTC6269 is available in SOIC, MSOP, DFN and
SOT-23 packages. Of these, the SOIC has been designed
as the best choice for low input bias current. It has the
largest lead spacing which increases the impedance of
the package plastic and the pinout is such that the two
input pins are isolated on the far side of the package from
the other signals. The gull-wing leads on this package
also allow for better cleaning of the PCB and reduced
contamination-induced leakage. The other packages have
advantages in size and pin count but do so by reducing
the input isolation. Leadless packages such as the DFN
offer the minimum size but have the smallest pin spacing
and may trap contaminants under the package.
TIME (10ns/DIV)
6268 F11
fS = 10Msps
fIN = 10.101MHz
0
ADC OUTPUTS (COUNTS)
60k
52k
56k
36k
44k
48k
40k
4k
8k
12k
16k
20k
24k
28k
32k
64k
440 460 480 520 540 560 580500
LTC6268/LTC6269
18
62689f
For more information www.linear.com/LTC6268
APPLICATIONS INFORMATION
The material used in the construction of the PCB can
sometimes influence the leakage characteristics of the
design. Exotic materials such as Teflon can be used to
improve leakage performance in specific cases but they
are generally not necessary if some basic rules are applied
in the design of conventional FR4 PCBs. It is important to
keep the high impedance signal path as short as possible
on the board. A node with high impedance is susceptible
to picking up any stray signals in the system so keeping it
as short as possible reduces this effect. In some cases, it
may be necessary to have a metallic shield over this por-
tion of the circuit. However, metallic shielding increases
capacitance. Another technique for avoiding leakage paths
is to cut slots in the PCB. High impedance circuits are also
susceptible to electrostatic as well as electromagnetic ef-
fects. The static charge carried by a person walking by the
circuit can induce an interference on the order of 100’s of
femtoamps. A metallic shield can reduce this effect as well.
The layout of a high impedance input node is very important.
Other signals should be routed well away from this signal
path and there should be no internal power planes under
it. The best defense from coupling signals is distance and
this includes vertically as well as on the surface. In cases
where the space is limited, slotting the board around the
high impedance input nodes can provide additional isola-
tion and reduce the effect of contamination. In electrically
noisy environments the use of driven guard rings around
these nodes can be effective (see Figure 12). Adding any
additional components such as filters to the high imped-
ance input node can increase leakage. The leakage current
of a ceramic capacitor is orders of magnitude larger than
the bias current of this device. Any filtering will need to
be done after this first stage in the signal chain.
Low Input Offset Voltage
The LTC6268 has a maximum offset voltage of ±2.5mV
(PNP region) over temperature. The low offset voltage is
essential for precision applications. There are 2 different
input stages that are used depending on the input common
mode voltage. To increase the versatility of the LTC6268, the
offset voltages are trimmed for both regions of operation.
Rail-to-Rail Output
The LTC6268 has a rail-to-rail output stage that has ex-
cellent output drive capability. It is capable of delivering
over ±40mA of output drive current over temperature.
Furthermore, the output can reach within 200mV of either
rail while driving ±10mA. Attention must be paid to keep
the junction temperature of the IC below 150°C.
Input Protection
To prevent breakdown of internal devices in the input stage,
the two op amp inputs should NOT be separated by more
than 2.0V. To help protect the input stage, internal circuitry
will engage automatically if the inputs are separated by
>2.0V and input currents will begin to flow. In all cases,
care should be taken so that these currents remain less
than 1mA. Additionally, if only one input is driven, inter-
nal circuitry will prevent any breakdown condition under
transient conditions. The worst-case differential input
voltage usually occurs when the +input is driven and the
output is accidentally shorted to ground while in a unity
gain configuration.
LTC6268/LTC6269
19
62689f
For more information www.linear.com/LTC6268
APPLICATIONS INFORMATION
ESD
ESD Protection devices can be seen in the simplified sche-
matic. The +IN andIN pins use a sophisticated method
of ESD protection that incorporates a total of 4 reverse-
biased diodes connected as 2 series diodes to each rail.
To maintain extremely low input bias currents, the center
node of each of these series diode chains is driven by a
buffered copy of the input voltage. This maintains the two
diodes connected directly to the input pins at low reverse
bias, minimizing leakage current of these ESD diodes to
the input pins.
The remaining pins have traditional ESD protection, using
reverse-biased ESD diodes connected to each power supply
rail. Care should be taken to make sure that the voltages
on these pins do not exceed the supply voltages by more
than 100mV or these diodes will begin to conduct large
amounts of current.
Shutdown
The LTC6268S6, LTC6268S8, and LTC6269DD have SHDN
pins that can shut down the amplifier to less than 1.2mA
supply current per amplifier. The SHDN pin voltage needs
to be within 0.75V of V for the amplifier to shut down.
During shutdown, the output will be in a high output re-
sistance state, so the LTC6268 is suitable for multiplexer
applications. The internal circuitry is kept in a low current
active state for fast recovery. When left floating, the SHDN
pin is internally pulled up to the positive supply and the
amplifier is enabled.
LTC6268/LTC6269
20
62689f
For more information www.linear.com/LTC6268
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) S6 TSOT-23 0302
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
LTC6268/LTC6269
21
62689f
For more information www.linear.com/LTC6268
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 REV G 0212
.053 – .069
(1.346 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610 Rev G)
LTC6268/LTC6269
22
62689f
For more information www.linear.com/LTC6268
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSOP (MS8E) 0213 REV K
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
1 2 34
4.90 ±0.152
(.193 ±.006)
8
8
1
BOTTOM VIEW OF
EXPOSED PAD OPTION
765
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.52
(.0205)
REF
1.68
(.066)
1.88
(.074)
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
1.68 ±0.102
(.066 ±.004)
1.88 ±0.102
(.074 ±.004) 0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.65
(.0256)
BSC
0.42 ±0.038
(.0165 ±.0015)
TYP
0.1016 ±0.0508
(.004 ±.002)
DETAIL “B”
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.05 REF
0.29
REF
MS8E Package
8-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1662 Rev K)
LTC6268/LTC6269
23
62689f
For more information www.linear.com/LTC6268
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.125
TYP
2.38 ±0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD) DFN REV C 0310
0.25 ±0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.70 ±0.05
3.55 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
LTC6268/LTC6269
24
62689f
For more information www.linear.com/LTC6268
LINEAR TECHNOLOGY CORPORATION 2014
LT 0914 • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC6268
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
Op Amps
LTC6244 Dual 50MHz, Low Noise, Rail-to-Rail, CMOS Op Amp Unity Gain Stable, 1pA Input Bias Current, 100μV Max Offset.
LTC6240/LTC6241/
LTC6242
18MHz, Low Noise, Rail-to-Rail Output, CMOS Op Amp 18MHz GBW, 0.2pA Input Current, 125μV Max Offset.
LTC6252/LTC6253/
LTC6254
720MHz, 3.5mA Power Efficient Rail-to-Rail I/O Op Amp 720MHz GBW, Unity Gain Stable, Low Noise
LTC6246/LTC6247/
LTC6248
180MHz, 1mA Power Efficient Rail-to-Rail I/O Op Amps 180MHz GBW, Unity Gain Stable, Low Noise
LT1818 400MHz, 2500V/µs, 9mA Single Operational Amplifier Unity Gain Stable, 6nV/√Hz Unity Gain Stable
LT6230 215MHz, Rail-to-Rail Output, 1.1nV/√Hz, 3.5mA Op Amp Family 350μV Max Offset Voltage, 3V to 12.6V Supply
LT6411 650MHz Differential ADC Driver/Dual Selectable Amplifier SR 3300V/µs, 6ns 0.1% Settling.
SAR ADC
LTC2376-18/
LTC2377-18/
LTC2378-18/
LTC2379-18
18-Bit, 250ksps to 1.6Msps, Low Power SAR ADC, 102dB SNR 18mW at 1.6Msps, 3.4μW at 250sps, –126dB THD.
LTC6268 as a High-Z Buffer Driving an LT1395 as a
Single-Ended to Differential Converter Into a 16-Bit ADC
Reconstructed Sampled Time Domain
Response of Above Circuit
AIN+
AIN
LTC2269
1.8V
D15
D0
VDD
1.8V
OVDD
• • •
LTC2269 16-BIT 20 Msps ADC
6268 TA03
VCM
10MHz
CLOCK
CLOCK
CONTROL
OUTPUT
DRIVERS
OGNDGND
16-BIT
ADC CORE
LTC6655-2.048
VIN
VOUT_s
VOUT_F
GND
SHDN
VIN
VIN = 2.048V
±1.7V FS
VREF
R2
75Ω
R1
49.9Ω
R6
100Ω
R7
100Ω
R4
49.9Ω
R10
75Ω
R16
49.9Ω
R17
49.9Ω
R15
402Ω
R13
825Ω
R18
49.9Ω
R11
75Ω
R8
200Ω
L4
100nH
L3
100nH
C5
.01µF
R14
402Ω
R12
825Ω
R5
49.9Ω
R9
200Ω
C2
10pF
C3
10pF
C4
100µF
CIN
0.1µF C4
0.1µF
L1
100nH
L2
100nH
+V
+V
R3
10M
C1
22pF
U1
+
LTC6268
LT1395
U2
+V
+V = 5V
–V = –5V –V
+
+
+S/H
TIME (10ns/DIV)
6268 F11
fS = 10Msps
fIN = 10.101MHz
0
ADC OUTPUTS (COUNTS)
60k
52k
56k
36k
44k
48k
40k
4k
8k
12k
16k
20k
24k
28k
32k
64k
440 460 480 520 540 560 580500

Products

IC OPAMP GP 1 CIRCUIT TSOT23-6
Available Quantity5386
Unit Price12.91
IC OPAMP GP 1 CIRCUIT 8SO
Available Quantity234
Unit Price12.44
IC OPAMP GP 2 CIRCUIT 10DFN
Available Quantity1385
Unit Price18.17
IC OPAMP GP 2 CIRCUIT 8MSOP
Available Quantity803
Unit Price18.17
IC OPAMP GP 2 CIRCUIT 10DFN
Available Quantity1122
Unit Price20.91
IC OPAMP GP 2 CIRCUIT 8MSOP
Available Quantity106
Unit Price20.91
IC OPAMP GP 1 CIRCUIT TSOT23-6
Available Quantity335
Unit Price14.78
IC OPAMP GP 1 CIRCUIT 8SO
Available Quantity0
Unit Price14.4
IC OPAMP GP 1 CIRCUIT TSOT23-6
Available Quantity0
Unit Price6.46332
IC OPAMP GP 1 CIRCUIT 8SO
Available Quantity0
Unit Price6.46332
IC OPAMP GP 1 CIRCUIT 8SO
Available Quantity0
Unit Price7.43778
IC OPAMP GP 2 CIRCUIT 10DFN
Available Quantity0
Unit Price9.34695
IC OPAMP GP 2 CIRCUIT 8MSOP
Available Quantity0
Unit Price9.34695
IC OPAMP GP 2 CIRCUIT 10DFN
Available Quantity0
Unit Price10.75893
IC OPAMP GP 2 CIRCUIT 8MSOP
Available Quantity0
Unit Price10.75893