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LT3086 Datasheet

Linear Technology/Analog Devices

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Datasheet

LT3086
1
3086fb
For more information www.linear.com/LT3086
Typical applicaTion
FeaTures DescripTion
40V, 2.1A Low Dropout
Adjustable Linear Regulator with Monitoring
and Cable Drop Compensation
The LT
®
3086 is a multi-feature, low dropout, low noise
2.1A linear regulator that operates over a 1.4V to 40V
input supply range. Dropout voltage at 2.1A is typically
330mV. One resistor sets output voltage from 0.4V to 32V.
Output voltage tolerance is guaranteed to ±2% over line,
load and temperature. The LT3086 is stable with ceramic
output capacitors, requiring a minimum of 10µF.
The LT 3086’s programmable cable drop compensation
cancels output voltage errors caused by resistive connec-
tions to the load. A master/slave configuration allows paral-
leling of multiple devices for higher load current and heat
spreading without external ballast resistor requirements.
Output current and temperature monitoring along with
a power good flag provide system diagnostic and debug
capability. Internal fault circuitry includes thermal shutdown
and current limit with foldback. Thermal limit and current
limit are also externally programmable.
Packages include the thermally enhanced 16-lead
(5mm × 4mm) DFN, 16-lead TSSOP, 7-lead DD-Pak and
7-lead TO-220.
L, LT, LT C , LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
5V, 2.1A USB Supply with Cable Drop Compensation
Transient Response with Cable
Drop Compensation (CDC)
applicaTions
n Wide Input Voltage Range: 1.4V to 40V
n 1 Resistor Sets Output Voltage: 0.4V to 32V
n Output Current: 2.1A
n ±2% Tolerance Over Line, Load and Temperature
n Output Current Monitor: IMON = IOUT/1000
n Temperature Monitor with Programmable
Thermal Limit
n Programmable Cable Drop Compensation
n Parallel Multiple Devices for Higher Current
n Dropout Voltage: 330mV
n 1 Capacitor Soft-Starts Output and Decreases Noise
n Low Output Noise: 40µVRMS (10Hz to 100kHz)
n Precision, Programmable External Current Limit
n Power Good Flag with Programmable Threshold
n Ceramic Output Capacitors: 10µF Minimum
n Quiescent Current in Shutdown: <1µA
n Reverse-Battery, -Current and -Output Protection
n Available in 5mm × 4mm 16-Lead DFN,
16-Lead TSSOP, 7-Lead DD-Pak and 7-Lead TO-220.
n Programmable Linear Regulator
n Post Regulator for Switching Supplies
n USB Power Supplies
n High Reliability Power Supplies
3086 TA01
IN
SHDN
TRACK
TEMP
IMON
ILIM
OUT
SET
CDC
PWRGD
RPWRGD
VPWRGD
*SEE APPLICATIONS INFORMATION
FOR INDUCTANCE EFFECTS ASSOCIATED
WITH RWIRE
GND
LT3086
VIN
6V TO
15V
TO ADC
0.8V AT 2.24A
FULL-SCALE
VTEMP
10mV/°C
25°C = 250mV
VOUT
10µF 10µF
RSET
90.9k + 1.1k
1%
RCDC
1%
RCDC 1%
RLINE1
CABLE
RLINE2
RMON
357Ω
1%
82.5k
1%
100k VLOAD
5V AT 2.1A
LOAD
RCDC =
R
MON
R
SET
3000RWIRE
RWIRE =RLINE1 +RLINE2 *
0 80 160 560 640 720
800
240 320 400 480
TIME (µs)
OUTPUT VOLTAGE (V)
LOAD
CURRENT (A)
3060 TA04b
5.8
5.6
5.2
4.8
4.4
2
5.4
5.0
4.6
4.2
1
0
VIN = 6V
RMON = 357Ω
RWIRE = 0.24Ω
RCDC = 46.4k
VOUT WITH CDC
VLOAD WITHOUT CDC
VLOAD WITH CDC
∆ILOAD = 0.5A TO 1.5A
LT3086
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absoluTe MaxiMuM raTings
IN Pin Voltage .........................................................±45V
OUT Pin Voltage ......................................................±36V
Input-to-Output Differential Voltage (Note 2) ..........±45V
SET Pin Voltage ...............................................0.3, 36V
SHDN Pin Voltage ...................................................±45V
CDC Pin (Internally Clamped, Current into Pin) .......<8mA
IMON Pin Voltage ................................................0.3, 7V
ILIM Pin Voltage ..................................................0.3, 2V
TRACK Pin Voltage .... 0.3, Internally Clamped at 1.25V
TEMP Pin Voltage .................................................0V, 5V
(Note 1)
16
15
14
13
12
11
10
9
17
GND
1
2
3
4
5
6
7
8
GND
PWRGD
TRACK
TEMP
SHDN
IN
IN
NC
GND
ILIM
IMON
CDC
R
PWRGD
SET
OUT
OUT
TOP VIEW
DHD PACKAGE
16-LEAD (5mm
×
4mm) PLASTIC DFN
TJMAX = 125°C, θJA = 25°C/W TO 33°C/W*, θJC = 4.3°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
FE PACKAGE
16-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
GND
I
MON/ILIM
CDC
RPWRGD
SET
OUT
OUT
GND
GND
PWRGD
TRACK
TEMP
SHDN
IN
IN
GND
17
GND
TJMAX = 150°C, θJA = 25°C/W TO 33°C/W*, θJC = 10°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
R PACKAGE
7-LEAD PLASTIC DD
FRONT VIEW
TEMP
SHDN
IN
GND
OUT
SET
IMON/I
LIM
7
6
5
4
3
2
1
TAB
IS
GND
TJMAX = 125°C, θJA = 15°C/W TO 19°C/W*, θJC = 3°C/W
T7 PACKAGE
7-LEAD PLASTIC TO-220
TEMP
SHDN
IN
GND
OUT
SET
IMON/I
LIM
FRONT VIEW
TAB
IS
GND
7
6
5
4
3
2
1
TJMAX = 125°C, θJA = 34°C/W, θJC = 3°C/W
*See Applications Information section.
pin conFiguraTion
PWRGD Pin Voltage .........................................0.3, 36V
RPWRGD Pin Voltage .........................................0.3, 36V
Output Short-Circuit Duration .......................... Indefinite
Operating Junction Temperature (Notes 3, 5, 12)
E-Grade, I-Grade ................................ 40°C to 125°C
MP-Grade .......................................... 5C to 125°C
H-Grade ............................................. 40°C to 150°C
Storage Temperature Range ......................65 to 150°C
Lead Temperature (Soldering, 10 sec)
(TSSOP, DD-Pak, TO-220 Only) ...........................30C
LT3086
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For more information www.linear.com/LT3086
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum Input Voltage (Note 4) ILOAD = 2.1A, ∆VOUT = –1% l1.4 1.55 V
Reference Voltage VSET
(Notes 3, 5) VIN = 1.55V, ILOAD = 1mA
1.55V < VIN < 40V, 1mA < ILOAD < 2.1A (TJ < 125°C)
1.55V < VIN < 40V, 1mA < ILOAD < 2.1A (H-Grade, TJ > 125°C)
l
396
392
388
400
400
400
404
408
408
mV
mV
mV
Reference Current ISET VIN = 1.55V, ILOAD = 1mA
1.55V < VIN < 40V, 1mA < ILOAD < 2.1A
l
49.5
49 50
50 50.5
51 µA
µA
Line Regulation VSET
VSET
ISET
VIN = 1.55V to 40V, ILOAD = 1mA (TJ < 125°C)
VIN = 1.55V to 40V, ILOAD = 1mA (H-Grade, TJ > 125°C)
VIN = 1.55V to 40V, ILOAD = 1mA
l
l
–0.12
0.1
–0.03
0.8
1mV
mV
µA
Load Regulation VSET
(Notes 6, 7) VSET
ISET
ISET
ILOAD = 1mA to 2.1A, VIN = VOUT + 0.55V (TJ < 125°C)
ILOAD = 1mA to 2.1A, VIN = VOUT + 0.55V (H-Grade, TJ > 125°C)
ILOAD = 1mA to 2.1A, VIN = VOUT + 0.55V (TJ < 125°C)
ILOAD = 1mA to 2.1A, VIN = VOUT + 0.55V (H-Grade, TJ > 125°C)
l
l
–8
–0.16
0.25
0.02
1
1
0.08
0.08
mV
mV
µA
µA
Minimum Load Current (Note 16) l1 mA
Dropout Voltage
VIN = VOUT(NOMINAL), (Notes 7, 8) ILOAD = 1mA
l
10 65
100 mV
mV
ILOAD = 100mA
l
100 135
160 mV
mV
ILOAD = 500mA
l
150 195
235 mV
mV
ILOAD = 1.5A
l
260 335
425 mV
mV
ILOAD = 2.1A
l
330 415
540 mV
mV
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3086EDHD#PBF LT3086EDHD#TRPBF 3086 16-Lead (5mm × 4mm) Plastic DFN –40°C to 125°C
LT3086IDHD#PBF LT3086IDHD#TRPBF 3086 16-Lead (5mm × 4mm) Plastic DFN –40°C to 125°C
LT3086EFE#PBF LT3086EFE#TRPBF 3086FE 16-Lead Plastic TSSOP –40°C to 125°C
LT3086IFE#PBF LT3086IFE#TRPBF 3086FE 16-Lead Plastic TSSOP –40°C to 125°C
LT3086MPFE#PBF LT3086MPFE#TRPBF 3086FE 16-Lead Plastic TSSOP –55°C to 125°C
LT3086HFE#PBF LT3086HFE#TRPBF 3086FE 16-Lead Plastic TSSOP –40°C to 150°C
LT3086ER#PBF LT3086ER#TRPBF LT3086R 7-Lead Plastic DD-Pak –40°C to 125°C
LT3086IR#PBF LT3086IR#TRPBF LT3086R 7-Lead Plastic DD-Pak –40°C to 125°C
LT3086MPR#PBF LT3086MPR#TRPBF LT3086R 7-Lead Plastic DD-Pak –55°C to 125°C
LT3086ET7#PBF N/A LT3086T7 7-Lead Plastic TO-220 –40°C to 125°C
LT3086IT7#PBF N/A LT3086T7 7-Lead Plastic TO-220 –40°C to 125°C
LT3086MPT7#PBF N/A LT3086T7 7-Lead Plastic TO-220 –55°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
orDer inForMaTion
http://www.linear.com/product/LT3086#orderinfo
LT3086
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For more information www.linear.com/LT3086
PARAMETER CONDITIONS MIN TYP MAX UNITS
GND Pin Current
VIN = VOUT(NOMINAL) + 0.55V, (Notes 7,
9)
ILOAD = 0µA
ILOAD = 1mA
ILOAD = 100mA
ILOAD = 500mA
ILOAD = 1.5A
ILOAD = 2.1A
l
l
l
l
l
l
1.2
1.3
1.8
4.5
23
44
2.4
2.6
3.6
9
46
88
mA
mA
mA
mA
mA
mA
Quiescent Current in Shutdown VIN = 40V, VSHDN = 0V 0.1 1 µA
Output Voltage Noise CSET = 0.01µF , COUT = 10µF, ILOAD = 2.1A
VOUT = 5V, BW = 10Hz to 100kHz 40 µVRMS
Shutdown Threshold VOUT = Off to On
VOUT = On to Off
l
l
1.12
0.85 1.22
1.03 1.32 V
V
SHDN Pin Current (Note 10)
1.55V < VIN < 40V VSHDN = 0V
VSHDN = 40V
l
l
15 1
35 µA
µA
TEMP Voltage (Note 13) TJ = 25°C
TJ = 125°C 0.25
1.25 V
V
TEMP Error (Note 13) 0°C < TJ < 125°C, ITEMP = 0
0°C < TJ < 125°C, ITEMP = 0µA to 80µA –0.09
–0.1 0.09 V
V
ITEMP Thermal Limit Current Threshold 25°C < TJ < 125°C 95 100 105 µA
IMON Output Current
VIN = VOUT(NOMINAL) + 0.55V (Note 15) ILOAD = 20mA, RMON = 1kΩ
ILOAD = 500mA, RMON = 330Ω
ILOAD = 1A, RMON = 330Ω
ILOAD = 1.5A, RMON = 330Ω
ILOAD = 2.1A, RMON = 330Ω
l
l
l
l
l
5
440
0.95
1.43
2.02
20
500
1.00
1.50
2.10
75
560
1.05
1.57
2.18
µA
µA
mA
mA
mA
Output Current Sharing Error (Note 14) RMON = 330Ω, IOUT(MASTER) = 2.1A –10 0 10 %
TRACK Pin Pull-Up Current VTRACK = 750mV l7 15 25 µA
RPWRGD Reference Voltage 1.55V < VIN < 40V l390 400 410 mV
RPWRGD Reference Current 1.55V < VIN < 40V l48.75 50 51.25 µA
RPWRGD Reference Voltage Hysteresis 1.55V < VIN < 40V 2.4 mV
RPWRGD Reference Current Hysteresis 1.55V < VIN < 40V 300 nA
PWRGD VOL IPWRGD = 200µA (Fault Condition) l55 200 mV
PWRGD Internal Time Delay VOL TO VOH (Rising Edge) l8 17 25 µs
PWRGD Pin Leakage Current VPWGRD = 32V, VRPWGRD = 500mV l1 µA
CDC Reference Voltage 1.55V < VIN < 40V, IMON = 0V l390 400 410 mV
CDC/VIMON Voltage Gain 1.55V < VIN < 40V, 0 < ICDC < 20µA, VIMON = 800mV to 0 l0.320 0.333 0.343 V/V
Ripple Rejection VIN = 1.9V (AVG), VRIPPLE = 0.5VP-P, VOUT = 1V
fRIPPLE = 120Hz, ILOAD = 2.1A 65 80 dB
Internal Current Limit VIN = 1.55V
VIN = VOUT(NOMINAL) + 0.55V (Notes 7, 12), ∆VOUT = –5%
l
l
2.2
2.2 2.4 2.9 A
A
ILIM Threshold Voltage 1.55V < VIN < 40V l775 800 825 mV
Input Reverse-Leakage Current VIN = –40V, VOUT = 0 l2 mA
Reverse-Output Current (Note 11) VOUT = 32V, VIN = 0, VSHDN = 0 1 10 µA
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Absolute maximum input-to-output differential voltage is not
achievable with all combinations of rated IN pin and OUT pin voltages.
With the IN pin at 45V, the OUT pin may not be pulled below 0V. The total
IN to OUT differential voltage must not exceed ±45V.
Note 3: The LT3086 is tested and specified under pulse load conditions
such that TJ TA. The LT3086E is 100% production tested at TA = 25°C
and performance is guaranteed from 0°C to 125°C. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LT3086I is guaranteed over the full –40°C to 125°C operating junction
temperature range. The LT3086MP is 100% tested over the –55°C to
125°C operating junction temperature range. The LT3086H is 100% tested
LT3086
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For more information www.linear.com/LT3086
at the 150°C operating junction temperature. High junction temperatures
degrade operating lifetimes. Operating lifetime is derated at junction
temperatures greater than 125°C.
Note 4: The LT3086 is tested and specified for these conditions with the
SET pin connected to the OUT pin, VOUT = 0.4V.
Note 5: Maximum junction temperature limits operating conditions. The
regulated output voltage specification does not apply for all possible
combinations of input voltage and output current. Limit the output current
range if operating at large input-to-output voltage differentials. Limit
the input-to-output voltage differential if operating at maximum output
current. Current limit foldback limits the maximum output current as a
function of input-to-output voltage. See Current Limit vs VIN – VOUT in the
Typical Performance Characteristics section.
Note 6: Load regulation is Kelvin-sensed at the package.
Note 7: To satisfy minimum input voltage requirements, the LT3086 is
tested and specified for these conditions with a 32k resistor between OUT
and SET for a 2V output voltage.
Note 8: Dropout voltage is the minimum input-to-output voltage
differential needed to maintain regulation at a specified output current.
In dropout, the output voltage equals: (VIN – VDROPOUT). For low output
voltages and certain load conditions, minimum input voltage requirements
limit dropout voltage. See the Minimum Input Voltage curve in the Typical
Performance Characteristics section.
Note 9: GND pin current is tested with VIN = VOUT(NOMINAL) + 0.55V and
PWRGD pin floating. GND pin current increases in dropout. See GND pin
current curves in the Typical Performance Characteristics section.
Note 10: SHDN pin current flows into the SHDN pin.
Note 11: Reverse-output current is tested with the IN pin grounded and
the OUT pin forced to a voltage. The current flows into the OUT pin and out
of the GND pin.
Note 12: The IC includes overtemperature protection circuitry that protects
the device during momentary overload conditions. Junction temperature
exceeds 125°C (LT3086E, LT3086I, LT3086MP) or 150°C (LT3086H)
when the overtemperature circuitry is active unless thermal limit is
externally set by loading the TEMP pin. Continuous operation above the
specified maximum junction temperature may impair device reliability.
Note 13: The TEMP output voltage represents the average die temperature
next to the power transistor while the center of the transistor can be
significantly hotter during high power conditions. Due to power dissipation
and temperature gradients across the die, the TEMP output voltage
measurement does not guarantee that absolute maximum junction
temperature is not exceeded.
Note 14: Output current sharing error is the difference in output currents
of a slave relative to its master when two LT3086 regulators are paralleled.
The device is tested as a slave with VTRACK = 0.693V, RMON = 330Ω
and VSET = 0.4V, conditions when an ideal master is outputting 2.1A.
The specification limits account for the slave output tracking error from
2.1A and the worst-case error that can be contributed by a master: the
maximum deviation of VSET from 0.4V and IMON from 2.1mA.
Note 15: The LT3086 is tested and specified for these conditions with the
IMON and ILIM pins tied together.
Note 16: The LT3086 requires a minimum load current to ensure proper
regulation and stability.
Typical Dropout Voltage Guaranteed Dropout Voltage Dropout Voltage
Typical perForMance characTerisTics
elecTrical characTerisTics
TA = 25°C, unless otherwise noted.
OUTPUT CURRENT (A)
0
DROPOUT VOLTAGE (mV)
550
500
400
300
200
100
450
350
250
150
50
01.20.6
3086 G01
2.1
0.90.3 1.5 1.8
TJ = 125°C
TJ = 25°C
OUTPUT CURRENT (A)
0
GUARANTEED DROPOUT VOLTAGE (mV)
550
500
400
300
200
100
450
350
250
150
50
01.20.6
3086 G02
2.1
0.90.3 1.5 1.8
TJ ≤ 125°C
TJ ≤ 25°C
= TEST POINTS
TEMPERATURE (°C)
–75
DROPOUT VOLTAGE (mV)
550
500
400
300
200
100
450
350
250
150
50
0100–25
3086 G03
175
0–50 125 1507525 50
IL = 2.1A
IL = 1.5A
IL = 1A
IL = 500mA
IL = 100mA
IL = 1mA
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Typical perForMance characTerisTics
GND Pin Current, VOUT = 0.4V
(Heavy Load)
GND Pin Current, VOUT = 5V
(Light Load)
GND Pin Current, VOUT = 5V
(Heavy Load)
Quiescent Current, VOUT = 0.4V Quiescent Current, VOUT = 5V
GND Pin Current, VOUT = 0.4V
(Light Load)
TA = 25°C, unless otherwise noted.
INPUT VOLTAGE (V)
0
QUIESCENT CURRENT (mA)
2.0
1.8
1.4
1.0
0.2
1.6
1.2
0.8
0.6
0.4
025
3086 G07
40
5 30 352010 15
TJ = 25°C
RSET = 0
IL = 0
VSHDN = VIN
VSHDN = 0
INPUT VOLTAGE (V)
GND PIN CURRENT (mA)
90
70
50
10
80
60
40
30
20
0
3086 G10
TJ = 25°C
VSHDN = VIN
RSET = 0
0 72
10
31 8 964 5
RL = 0.4Ω, IL = 1A
RL = 0.267Ω, IL = 1.5A
RL = 0.19Ω, IL = 2.1A
INPUT VOLTAGE (V)
GND PIN CURRENT (mA)
10
9
7
5
1
8
6
4
3
2
0
3086 G11
TJ = 25°C
VSHDN = VIN
RSET = 92k
0 72
10
31 8 964 5
RL = 10Ω
IL = 500mA
RL = 50Ω
IL = 100mA
RL = 5k, IL = 1mA
INPUT VOLTAGE (V)
GND PIN CURRENT (mA)
3086 G12
TJ = 25°C
VSHDN = VIN
RSET = 92k
0 72
10
31 8 964 5
RL = 2.381Ω
IL = 2.1A
RL = 3.333Ω
IL = 1.5A
RL = 5Ω, IL = 1A
90
70
50
10
80
60
40
30
20
0
INPUT VOLTAGE (V)
QUIESCENT CURRENT (mA)
2.0
1.8
1.4
1.0
0.2
1.6
1.2
0.8
0.6
0.4
0
3086 G08
TJ = 25°C
RSET = 92k
IL = 0
VSHDN = VIN
VSHDN = 0
0 72
10
31 8 964 5
INPUT VOLTAGE (V)
GND PIN CURRENT (mA)
10
9
7
5
1
8
6
4
3
2
0
3086 G09
TJ = 25°C
VSHDN = VIN
RSET = 0
0 72
10
31 8 964 5
RL = 0.8Ω
IL = 500mA
RL = 4Ω
IL = 100mA
RL = 400Ω, IL = 1mA
SET Pin Reference Voltage SET Pin Reference Current Quiescent Current
TEMPERATURE (°C)
–75
SET PIN REFERENCE VOLTAGE (mV)
408
406
402
398
394
404
400
396
392 100–25
3086 G04
175
0–50 125 1507525 50
IL = 1mA
TEMPERATURE (°C)
–75
SET PIN REFERENCE CURRENT (µA)
51.0
50.8
50.4
50.0
49.2
50.6
50.2
49.8
49.6
49.4
49.0 100–25
3086 G05
175
0–50 125 1507525 50
IL = 1mA
TEMPERATURE (°C)
–75
QUIESCENT CURRENT (mA)
2.0
1.8
1.4
1.0
0.2
1.6
1.2
0.8
0.6
0.4
0100–25
3086 G06
175
0–50 125 1507525 50
VIN = 6V
VOUT = 5V
IL = 0
VSHDN = VIN
VSHDN = 0
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For more information www.linear.com/LT3086
Typical perForMance characTerisTics
RPWRGD Pin Input Current
SHDN Pin Input Current OUT Over IN Shutdown Threshold
RPWRGD Pin Threshold
GND Pin Current vs ILOAD GND Pin Current vs Temperature SHDN Pin Threshold
SHDN Pin Input Current
TA = 25°C, unless otherwise noted.
OUTPUT CURRENT (A)
0
GND PIN CURRENT (mA)
70
60
40
20
50
30
10
01.20.6
3086 G13
2.1
0.90.3 1.5 1.8
VIN = VOUT(NOMINAL) + 0.55V
125°C
–40°C
25°C
TEMPERATURE (°C)
–75
SHDN PIN THRESHOLD (V)
1.40
1.35
1.25
1.15
0.95
1.30
1.20
1.10
1.05
1.00
0.90 100–25
3086 G14
175
0–50 125 1507525 50
SHDN TIED TO VIN
VSHDN ≤ VIN – 0.3V, VIN > VIN(MIN)
OFF TO ON
ON TO OFF
SHDN PIN VOLTAGE (V)
SHDN PIN INPUT CURRENT (µA)
20
18
14
10
2
16
12
8
6
4
0
3086 G15
VIN = VSHDN
0 25
40
5 30 352010 15
R
PWRGD
PIN INPUT CURRENT (µA)
51.0
50.8
50.4
50.0
49.2
50.6
50.2
49.8
49.6
49.4
49.0
TEMPERATURE (°C)
–75 100–25
3086 G19
175
0–50 125 1507525 50
IL = 0
OUTPUT RISING
OUTPUT FALLING
TEMPERATURE (°C)
–75
SHDN PIN INPUT CURRENT (µA)
20
18
14
10
2
16
12
8
6
4
0100–25
3086 G16
175
0–50 125 1507525 50
VSHDN = 40V
VSHDN = 6V
TEMPERATURE (°C)
–75
OUT OVER IN SHUTDOWN THRESHOLD (mV)
300
275
225
175
150
100
50
250
200
125
75
25
0100–25
3086 G17
175
0–50 125 1507525 50
ON TO OFF
OFF TO ON
TEMPERATURE (°C)
–75
R
PWRGD
PIN THRESHOLD (mV)
408
406
402
398
394
404
400
396
392 100–25
3086 G18
175
0–50 125 1507525 50
IL = 0
OUTPUT RISING
OUTPUT FALLING
GND PIN CURRENT (mA)
70
60
40
20
50
30
10
0
3086 G13a
TEMPERATURE (°C)
–75 100–25 1750–50 125 1507525 50
VIN = VOUT(NOMINAL) + 0.55V
IL = 2.1A
IL = 1.5A
IL = 1A
IL = 500mA
LT3086
8
3086fb
For more information www.linear.com/LT3086
Typical perForMance characTerisTics
TRACK Pin Pull-Up Current
ILIM Pin Input Current
TRACK Amplifier Input Offset TRACK Amplifier Gain
TA = 25°C, unless otherwise noted.
ILIM PIN VOLTAGE (mV)
I
LIM
PIN CURRENT (µA)
10
8
4
0
–8
6
2
–2
–6
–4
–10
3086 G25
0 500 800100 600 700400200 300
TRACK PIN VOLTAGE (V)
0
TRACK PIN PULL-UP CURRENT (µA)
30
25
15
5
20
10
00.80.4
3086 G28
1.4
0.60.2 1.0 1.2
TRACK AMPLIFIER INPUT OFFSET (mV)
10
8
4
0
–8
6
2
–2
–6
–4
–10
3086 G26
TEMPERATURE (°C)
–75 100–25
175
0–50 125 1507525 50
TRACK = 750mV
TRACK = 0mV
TRACK = 400mV
TRACK AMPLIFIER GAIN (V/V)
3086 G27
TEMPERATURE (°C)
–75 100–25
175
0–50 125 1507525 50
TRACK = 750mV
TRACK = 0mV
TRACK = 400mV
0.25
0.24
0.22
0.20
0.16
0.23
0.21
0.19
0.18
0.17
0.15
PWRGD Output Low Voltage PWRGD Internal Time Delay IOUT/IMON Ratio
Current Monitor at Light Load ILIM Pin Threshold Voltage
OUTPUT CURRENT (A)
0
I
OUT
/I
MON
RATIO (A/A)
1060
1050
1030
1010
1000
980
960
1040
1020
990
970
950
940 1.2
3086 G22
2.1
1.5 1.80.90.3 0.6
IMON = VIMON/RMON
IMON TIED TO ILIM
RMON = 330Ω
VIN = VOUT + 0.55V
TJ = 25°C
TJ = –40°C
TJ = 125°C
TEMPERATURE (°C)
–75
CURRENT MONITOR (V
IMON
/R
MON
) (µA)
40
35
25
15
5
30
20
10
0100–25
3086 G23
175
0–50 125 1507525 50
IL = 20mA
IL = 0
IMON TIED TO ILIM
RMON = 1kΩ
VIN = VOUT + 0.55V
TEMPERATURE (°C)
–75
I
LIM
PIN THRESHOLD (mV)
825
820
810
805
795
785
815
800
790
780
775 100–25
3086 G24
175
0–50 125 1507525 50
TEMPERATURE (°C)
–75
PWRGD OUTPUT LOW VOLTAGE (mV)
200
180
140
100
20
160
120
80
60
40
0100–25
3086 G20
175
0–50 125 1507525 50
IPWRGD = 200µA
TEMPERATURE (°C)
–75
PWRGD INTERNAL TIME DELAY (µs)
22
21
19
17
16
14
12
20
18
15
13
11
10 100–25
3086 G21
175
0–50 125 1507525 50
IPWRGD = 200µA
VOL TO VOH
LT3086
9
3086fb
For more information www.linear.com/LT3086
Typical perForMance characTerisTics
Internal Current Limit
vs Temperature
TEMP Pin Error
ITEMP Thermal Limit Threshold
Internal Current Limit
vs VIN – VOUT
TRACK Pin Pull-Up Current CDC Pin Reference Voltage CDC Amplifier Gain
CDC Amplifier Gain
CDC Pin Internal Clamp Fault
Current
TA = 25°C, unless otherwise noted.
TEMPERATURE (°C)
–75
CDC/V
IMON
VOLTAGE GAIN (V/V)
0.343
0.341
0.337
0.333
0.327
0.325
0.339
0.335
0.331
0.329
0.323 100–25
3086 G31
175
0–50 125 1507525 50
VIMON = 800mV TO 0mV
RCDC = ∞
RCDC (kΩ)
0
CDC/V
IMON
VOLTAGE GAIN (V/V)
0.343
0.341
0.337
0.333
0.327
0.325
0.339
0.335
0.331
0.329
0.323 7020
3086 G32
100
3010 80 906040 50
VIMON = 800mV TO 0mV
TJ = 125°C
TJ = 25°C
TJ = –40°C
CDC PIN VOLTAGE (V)
0
CDC PIN CURRENT (mA)
8
7
5
3
6
4
2
1
072
3086 G33
10
31 8 964 5
TJ = 125°C
TJ = 25°C
TJ = –40°C
VOUT > VOUT(NOMINAL)
TRACK PIN PULL-UP CURRENT (µA)
30
25
15
5
20
10
0
TEMPERATURE (°C)
–75 100–25
3086 G29
175
0–50 125 1507525 50
TRACK = 750mV
TRACK = 0
TEMPERATURE (°C)
–75
CDC PIN REFERENCE VOLTAGE (mV)
408
406
402
400
396
404
398
394
392 100–25
3086 G30
175
0–50 125 1507525 50
RCDC = ∞
RMON = 0
IL = 0
TEMPERATURE (°C)
–75
CURRENT LIMIT (A)
3.0
2.7
2.1
1.5
0.6
0.3
2.4
1.8
1.2
0.9
0100–25
3086 G37
175
0–50 125 1507525 50
VIN = 1.55V
VOUT = 0V
TEMPERATURE (°C)
TEMP PIN ERROR (°C)
2.5
2.0
1.0
0
–2.0
1.5
0.5
–0.5
–1.5
–1.0
–2.5
3086 G34
25 75
150
100 12550
TEMP = VTEMP/(10mV/°C)
ITEMP = 80µA
ITEMP = 0
TEMPERATURE (°C)
THERMAL LIMIT THRESHOLD (µA)
105
104
102
100
96
103
101
99
97
98
95
3086 G35
25 75
150
100 12550
TEMP = VTEMP/(10mV/°C)
RISING
FALLING
INPUT/OUTPUT DIFFERENTIAL (V)
CURRENT LIMIT (A)
3.0
2.7
2.1
1.5
0.3
2.4
1.8
1.2
0.6
0.9
0
3086 G36
0 25
40
5 30 352010 15
TJ = 125°C
∆VOUT = –5%
TJ = –40°C
TJ = 25°C
LT3086
10
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For more information www.linear.com/LT3086
FREQUENCY (Hz)
RIPPLE REJECTION (dB)
100
90
70
50
10
80
60
40
30
20
0
3086 G42
10 100 100k 1M
10M
10k1k
CSET = 0
CSET = 10nF
COUT = 22µF
VTEMP = 0.25V
VIN = 5.7V + 50mVRMS RIPPLE
COUT = 10µF
FREQUENCY (Hz)
RIPPLE REJECTION (dB)
100
90
70
50
10
80
60
40
30
20
0
3086 G41
IL = 2.1A, CSET = 0, VTEMP = 0.25V,
VIN = 1.6V + 50mVRMS RIPPLE (FOR VOUT
= 0.4V)
V
IN
= 5.7V + 50mV
RMS
RIPPLE (FOR V
OUT
= 5V)
10 100 100k 1M 10M10k1k
VOUT = 5V
VOUT = 0.4V
COUT = 10µF
COUT = 22µF
Typical perForMance characTerisTics
Ripple Rejection vs Temperature
5V, 2.1A Ripple Rejection
vs VIN – VOUT
5V, 1A Ripple Rejection
vs VIN – VOUT
TA = 25°C, unless otherwise noted.
–75 100–25 1750–50 125 1507525 50
RIPPLE REJECTION (dB)
100
90
70
50
10
80
60
40
30
20
0
3086 G43
IL = 2.1A, CSET = 0, VTEMP = 0.25V,
VIN = 1.9V + 0.5VP-P RIPPLE (FOR VOUT
= 0.4V, 1V)
VIN = 5.9V + 0.5VP-P RIPPLE (FOR VOUT = 5V)
RIPPLE AT f = 120Hz
VOUT = 1V
VOUT = 5V
VOUT = 0.4V
TEMPERATURE (°C)
0.2 0.3 1.00.5
1.2
0.60.4 1.10.90.7 0.8
RIPPLE REJECTION (dB)
100
90
70
50
10
80
60
40
30
20
0
3086 G44
RIPPLE AT f = 1MHz
50mVRMS RIPPLE ON VIN
IL = 2.1A
COUT = 10µF
CSET = 10nF
VTEMP = 0.25V
RIPPLE AT f = 100kHz
RIPPLE AT f = 10kHz
AVERAGE INPUT-TO-OUTPUT DIFFERENTIAL (V)
5V, 2.1A Input Ripple Rejection 5V, 1A Input Ripple Rejection
Reverse-Output Current Reverse-Output Current Overshoot Pull-Down Current
Input Ripple Rejection
OUTPUT VOLTAGE (V)
3086 G40
0 20 36324 24 28168 12
OUTPUT OVERSHOOT PULL-DOWN (mA)
30
25
15
5
20
10
0
VIN > VOUT
VSET = 500mV
CURRENT FLOWS THROUGH
OUT PIN TO GND
OUTPUT VOLTAGE (V)
3086 G38
0 20
32
4 24 28168 12
REVERSE OUTPUT CURRENT (mA)
0.6
0.5
0.3
0.1
0.4
0.2
0
TJ = 25°C
VIN = 0V
VOUT = VSET = VRPWRGD
CURRENT FLOWS THROUGH
PINS TO GROUND
OUT, RPWRGD
SET
TEMPERATURE (°C)
–75
REVERSE OUTPUT CURRENT (µA)
70
60
40
20
50
30
10
0100–25
3086 G39
175
0–50 125 1507525 50
VIN = 0V
VSHDN = 0V
VOUT = 5V
RSET = 92k
RPWRGD = 82k
RPWRGD
SET
OUT
FREQUENCY (Hz)
RIPPLE REJECTION (dB)
100
90
70
50
10
80
60
40
30
20
0
3086 G42a
10 100 100k 1M 10M10k1k
CSET = 0
CSET = 10nF
VTEMP = 0.25V
VIN = 5.5V + 50mVRMS RIPPLE
COUT = 10µF
COUT = 22µF
0.2 0.3 1.00.5 1.20.60.4 1.10.90.7 0.8
RIPPLE REJECTION (dB)
100
90
70
50
10
80
60
40
30
20
0
3086 G44a
RIPPLE AT f = 100kHz
50mVRMS RIPPLE ON VIN
COUT = 10µF
CSET = 10nF
VTEMP = 0.25V
RIPPLE AT f = 1MHz
RIPPLE AT f = 10kHz
AVERAGE INPUT/OUTPUT DIFFERENTIAL (V)
LT3086
11
3086fb
For more information www.linear.com/LT3086
Reference Current Load
Regulation
Reference Current Line
Regulation
Reference Voltage Line
Regulation
Minimum Input Voltage
Output Noise Spectral Density,
CSET = 0
Output Noise Spectral Density
vs CSET
RMS Output Noise vs Load
Current, CSET = 0
RMS Output Noise vs Load
Current, CSET = 10nF
Reference Voltage Load
Regulation
CHANGE IN SET PIN REFERENCE VOLTAGE (mV)
1.0
0.8
0.4
0
–0.8
0.6
0.2
–0.2
–0.6
–0.4
–1.0
3086 G45
TEMPERATURE (°C)
–75 100–25
175
0–50 125 1507525 50
VIN = VOUT(NOMINAL) + 0.55V
IL = 1mA TO 2.1A
IL = 1mA TO 1.5A
CHANGE IN SET PIN REFERENCE CURRENT (nA)
80
70
50
30
60
40
20
10
0
3086 G46
TEMPERATURE (°C)
–75 100–25
175
0–50 125 1507525 50
VIN = VOUT(NOMINAL) + 0.55V
IL = 1mA TO 2.1A
IL = 1mA TO 1.5A
FREQUENCY (Hz)
OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz)
3086 G49
10 100
100k
10k1k
CSET = 100pF
CSET = 100nF
CSET = 10nF CSET = 1nF
10
1
0.1
0.01
VOUT = 5V
IL = 2.1A
COUT = 10µF
VTEMP = 0.25V
LOAD CURRENT (A)
OUTPUT NOISE VOLTAGE (µV
RMS
)
350
300
200
100
250
150
50
0
3086 G50
VOUT = 5V
VOUT = 1.2V
VOUT = 3.3V
VOUT = 2.5V
VOUT = 0.4V
100µ 1m 1
10
100m10m
COUT = 10µF
COUT = 22µF
f = 10Hz TO 100kHz
VTEMP = 0.25V
LOAD CURRENT (A)
OUTPUT NOISE VOLTAGE (µV
RMS
)
70
60
40
20
50
30
10
0
3086 G51
VOUT = 5V
VOUT = 0.4V
100µ 1m 1
10
100m10m
COUT = 10µF
COUT = 22µF
f = 10Hz TO 100kHz
VTEMP = 0.25V
MINIMUM INPUT VOLTAGE (V)
1.8
1.6
1.2
0.8
0.2
1.4
1.0
0.6
0.4
0
3086 G47
TEMPERATURE (°C)
–75 100–25
175
0–50 125 1507525 50
IL = 2.1A
IL = 100mA
FREQUENCY (Hz)
OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz)
3086 G48
10 100
100k
10k1k
VOUT = 5V
VOUT = 1.2V
VOUT = 3.3V
VOUT = 2.5V
10
1
0.1
0.01
IL = 2.1A
COUT = 10µF
VTEMP = 0.25V
VOUT = 0.4V
Typical perForMance characTerisTics
TEMPERATURE (°C)
–75
CHANGE IN SET PIN REFERENCE VOLTAGE (mV)
1.0
0.9
0.7
0.5
0.1
0.8
0.6
0.4
0.3
0.2
0100–25
3086 G046a
1750–50 125 1507525 50
VIN = 1.55V TO 40V
IL = 1mA
TEMPERATURE (°C)
–75
CHANGE IN SET PIN REFERENCE CURRENT (nA)
0
–10
–30
–50
–20
–40
–60
–70
–80 100–25
3086 G046b
1750–50 125 1507525 50
VIN = 1.55V TO 40V
IL = 1mA
DD-PAK/TO-220
DFN/TSSOP
LT3086
12
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For more information www.linear.com/LT3086
Typical perForMance characTerisTics
Output Voltage Noise Load Transient Response Load Transient Response
RMS Output Noise vs Load
Current
RMS Output Noise vs
Feedforward Capacitor (CSET)
TA = 25°C, unless otherwise noted.
LOAD CURRENT (A)
OUTPUT NOISE VOLTAGE (µV
RMS
)
60
40
20
50
30
10
0
3086 G52
100µ 1m 1
10
100m10m
f = 10Hz TO 100kHz
VOUT = 0.4V
VTEMP = 0.25V
COUT = 100µF
COUT = 10µF
COUT = 22µF
COUT = 47µF
FEEDFORWARD CAPACITOR CSET (F)
10p 100p
100n
10n1n
OUTPUT NOISE VOLTAGE (µV
RMS
)
250
225
175
125
25
200
150
100
75
50
0
3086 G53
f = 10Hz TO 100kHz
IL = 2.1A
COUT = 10µF
VTEMP = 0.25V
VOUT = 5V
VOUT = 1.2V
VOUT = 2.5V
VOUT = 0.4V
VOUT = 3.3V
VOUT = 5V
RSET = 92k
CSET = 10nF
COUT = 10µF
IL = 2.1A
f = 10Hz TO 100kHz
3086 G54
VOUT
100µV/DIV
TIME 1ms/DIV
TIME (µs)
0
OUTPUT VOLTAGE
DEVIATION (mV)
LOAD
CURRENT (A)
200
50
–50
150
–150
2
100
0
–100
3
1
0100
3086 G55
160
20 120 1408040 60
VIN = 5.5V
VOUT = 5V
COUT = 10µF
CSET = 0
CSET = 10nF
∆IL = 500mA TO 1.5A
TIME (µs)
0
OUTPUT VOLTAGE
DEVIATION (mV)
LOAD
CURRENT (A)
300
200
–200
2
100
0
–100
3
1
0200
3086 G56
320
40 240 28016080 120
VIN = 5.5V
VOUT = 5V
CSET = 10nF
∆IL = 210mA TO 2.1A
COUT = 10µF CERAMIC +
100µF TANTALUM
COUT = 10µF CERAMIC
TIME (ms)
0
OUTPUT VOLTAGE
DEVIATION (mV)INPUT VOLTAGE (V)
15
0
–10
10
12
8
5
–5
10
6
40.5 0.6 0.7
3086 G57
1.0
0.1 0.8 0.90.40.2 0.3
IL = 2.1A
VOUT = 5V
COUT = 10µF
∆VIN = 5.55V TO 12V
TIME (µs)
0
OUTPUT VOLTAGE (V)
SHDN PIN
VOLTAGE (V)
6
3
1
5
0
1.0
4
2
1.5
0.5
060 80 90
3086 G58
140
100 1204020
COUT = 10µF
RSET = 92k
CSET = 0 RL = 2.38Ω (IL = 2.1A)
RL = 5kΩ (IL = 1mA)
FEEDFORWARD CAPACITOR, CSET (F)
START-UP TIME (ms)
3086 G59
10p 100p
100n
10n1n
VOUT = 5V
VOUT = 1.2V
VOUT = 3.3V
VOUT = 2.5V
100
10
1
0.1
0.01
IL = 1mA
SETTLING TO 1%
Start-Up Response Start-Up Time vs CSET
Line Transient Response
LT3086
13
3086fb
For more information www.linear.com/LT3086
pin FuncTions
(DFN/TSSOP/DD-Pak/TO-220)
GND (Pins 1, 16, Exposed Pad Pin 17/Pins 1, 8, 9, 16,
Exposed Pad Pin 17/Pin 4/Pin 4): Ground. The exposed
pad of the DFN and TSSOP packages as well as the Tab
of the DD-Pak and TO-220 packages is an electrical con-
nection to GND. To ensure proper electrical and thermal
performance, tie the exposed pad or tab directly to the
remaining GND pins of the relevant package and the PCB
ground. GND pin current is typically 1.2mA at zero load
and increases to about 44mA at full load.
ILIM (Pin 2/Pin 2/Pin 1/Pin 1): External Current Limit
Programming. This pin externally programs current limit
if connected to IMON and a resistor to GND. Current limit
activates if the voltage at ILIM equals 0.8V. Current limit
equals: 1000 (0.8V/RMON). An internal clamp typically
limits the ILIM voltage to 1V. If external current limit is set to
less than 1A, connect a series 1k-10nF network in parallel
with the RMON resistor for stability. Internal current limit
foldback overrides externally programmed current limit if
VINVOUT differential voltage is excessive. If external cur-
rent limit programming is not used, then ground this pin.
IMON (Pin 3/Pin 2/Pin 1/Pin 1): Output Current Monitor.
This pin sources a current equal to 1/1000 of output load
current. Connecting a resistor from IMON to GND programs
a load current dependent voltage for monitoring by an
ADC. If IMON connects to ILIM, current limit is externally
programmable.
CDC (Pin 4/Pin 3/NA/NA): Cable Drop Compensation.
Connecting a single resistor (RCDC) between the CDC and
SET pins provides programmable cable drop compensa-
tion that cancels output voltage errors caused by resistive
connections to the load. A resistor (RMON) from IMON to
GND is also required to enable Cable Drop Compensation.
Choose RMON first based on required current limit.
RMON = 0.8V • 1000/ILIM
Calculate the value of RCDC with this formula:
RCDC = (RMONRSET)/(3000 • RWIRE)
where RWIRE is the total cable or wire resistance to and
from the load. From a practical application standpoint,
LTC recommends limiting cable drop compensation to
20% of VOUT for applications needing good regulation.
The limiting factor is variations in wire temperature as
copper wire resistance changes about 19% for a 50°C
temperature change. If output regulation requirements
are loose (e.g., when using a secondary regulator), cable
drop compensation of up to 50% may be used.
RPWRGD (Pin 5/Pin 4/NA/NA): Power Good Threshold
Voltage Programming. This pin is the input to the power
good comparator. Connecting a resistor between OUT and
RPWRGD programs an adjustable power good threshold
voltage. The threshold voltage is 0.4V on the RPWRGD pin,
and a 50µA current source is connected from RPWRGD
to GND. If the voltage at RPWRGD is less than 0.4V, the
PWRGD flag asserts and pulls low. If the voltage at RP-
WRGD is greater than 0.4V, the PWRGD flag de-asserts
and becomes high impedance. For most applications,
PWRGD is pulled high with a pull-up resistor. Calculate
the value of RPWRGD with this formula:
RPWRGD = (XVOUT(NOMINAL) – 0.4V)/50µA
where X is normally in the 85% to 95% range.
A 17µs deglitching filter suppresses false tripping of the
PWRGD flag at the rising edge of PWRGD with instant
reset. Hysteresis at the RPWRGD pin is typically 0.6% on
the 0.4V threshold and the 50µA current source.
SET (Pin 6/Pin 5/Pin 2/Pin 2): Output Voltage Program-
ming. This pin is the error amplifier’s inverting terminal. It
regulates to 0.4V and a 50µA current source is connected
from SET to GND. Connecting a single resistor from OUT
to SET programs output voltage. Calculate the value of
the required resistor from the formula:
RSET = (VOUT – 0.4V)/50µA
Connecting a capacitor in parallel with RSET provides output
voltage soft-start capability, improves transient response
and decreases output voltage noise.
The LT3086 error amplifier design is configured so that
the regulator always operates in unity-gain.
OUT (Pins 7, 8/Pins 6, 7/Pin 3/Pin 3): Output. These
pin(s) supply power to the load. Connect all OUT pins
together on the DHD and FE packages for proper operation.
Stability requirements demand a minimum 10µF ceramic
output capacitor with an ESR less than 100to prevent
oscillations. Large load transients require larger output
capacitance to limit peak voltage transients. Permissible
LT3086
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pin FuncTions
(DFN/TSSOP/DD-Pak/TO-220)
output voltage range is 0.4V to 32V. The LT3086 requires
a 1mA minimum load current to ensure proper regula-
tion and stability.
IN (Pins 10, 11/Pins 10, 11/Pin 5/Pin 5): Input. These
pin(s) supply power to the device. Connect all IN pins
together on the DHD and FE packages for proper opera-
tion. The LT3086 requires a local IN bypass capacitor if
it is located more than a few inches from the main input
filter capacitor. In general, battery output impedance rises
with frequency, so adding a bypass capacitor in battery
powered circuits is advisable. A 10µF minimum input
capacitor generally suffices. The IN pin(s) withstand a
reverse voltage of 45V. The device limits current flow and
no negative voltage appears at OUT. The device protects
itself and the load against batteries that are plugged in
backwards.
SHDN (Pin 12/Pin 12/Pin 6/Pin 6): Shutdown/UVLO.
Pulling the SHDN pin typically below 1V puts the LT3086
into a low power state and turns the output off. Quiescent
current in shutdown is typically less thanA. The SHDN
pin turn-on threshold is typically 1.22V. This pin may either
be used as a shutdown function or as an undervoltage
lockout function. If using this pin as an undervoltage
lockout function, use a resistor divider between IN and
GND with the tap point tied to SHDN. If using the pin as
a shutdown function, drive the pin with either logic or an
open-collector/drain with a pull-up resistor. The resistor
supplies the pull-up current to the open-collector/drain
logic, normally several microamperes, and the SHDN pin
current, typically less than 10µA at 6V. If unused, connect
the SHDN pin to IN.
TEMP (Pin 13/Pin 13/Pin 7/Pin 7): Die Junction Tem-
perature. This pin outputs a voltage indicating the LT3086
average die junction temperature. At 25°C, this pin typically
outputs 250mV. The TEMP pin slope equals 10mV/°C so
that at 125°C, this pin typically outputs 1.25V. This pin
does not read temperatures less thanC. The TEMP pin
is not meant to be an accurate temperature sensor, but
is useful for debug, monitoring and calculating thermal
resistance of the package mounted to the PCB. The TEMP
pin also incorporates the ability to program a thermal
limit temperature lower than the internal typical thermal
shutdown temperature of 165°C. Tying a resistor from
TEMP to GND programs the thermal limit temperature
with a 100µA trip point. Calculate the value of the resistor
from the formula:
RTEMP =
TSHDN 10mV
°C
100µA
where TSHDN is the desired die thermal limit temperature.
There are several degrees of hysteresis in the thermal
shutdown that cycles the regulator output on and off. Limit
the capacitance on the TEMP pin to less than 100pF. To
prevent saturation in the TEMP output device, ensure that
VIN is higher than VTEMP by 250mV.
TRACK (Pin 14/Pin 14/NA/NA): Track pin for paralleling.
The TRACK pin allows multiple LT3086s to be paralleled
in a master/slave(s) configuration for higher output cur-
rent applications. This also allows heat to be spread out
on the PCB. This circuit technique does not require ballast
resistors and does not degrade load regulation. Tying the
TRACK pin of the slave device(s) to the IMON/ILIM pins
of the master device enables this function. If the TRACK
function is unused, TRACK is in a default clamped high
state. A TRACK pin voltage below 1.2V on slave device (s)
shuts off the internal 50µA reference current at SET such
that only the 50µA reference current of the master device
is active. All SET pins must be tied together in a master/
slave configuration.
PWRGD (Pin 15/Pin 15/NA/NA): Power Good Flag. The
PWRGD pin is an open-collector logic pin connected to
the output of the power good comparator. PWRGD asserts
low if the RPWRGD pin is less than 400mV. The maximum
low output level of 200mV over temperature is defined for
200μA of sink current. If RPWRGD is greater than 400mV,
the PWRGD pin de-asserts and becomes high impedance.
The PWRGD pin may be pulled to 36V without damaging
any internal circuitry regardless of the input voltage.
LT3086
15
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For more information www.linear.com/LT3086
block DiagraM
0.05Ω QPOWER
50Ω 120mV
40k
3086 BD
IN
GND
100k100k
900mV900mV
IMON
ILIM
OUT
CDC
EN
EN
300mV
+
120k
CABLE
DROP COMP
+
CURRENT
MONITOR
+
INTERNAL
ILIMIT
+
+
TEMP
+
+
EXTERNAL
ILIMIT
+
TRACK
ENABLE
300mV
1.2V
+
ERROR
AMP
SET
RPWRGD
25k
50µA
50µA
75k
125k
TRACK +
TRACK
gm = 8µ
13µA
1.3V
VREF
400mV
SHUTDOWN
CONTROL
17µs DELAY
RPWRGD RISING EDGE
IN
VTEMP
10mV/°C
25°C = 250mV
SHDN
1.22V
100µA
PWRGD
TEMP
IMON = IOUT
1000
LT3086
16
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For more information www.linear.com/LT3086
applicaTions inForMaTion
The LT3086 is a multifunction, low dropout, low noise,
linear regulator with shutdown, and adjustable power
good. The device supplies 2.1A with a typical dropout
voltage of 330mV and operates over a wide 1.4V to 40V
input supply range.
The operating quiescent current is 1.2mA and drops to less
thanA in shutdown. The LT3086 regulator optimizes
stability and transient response with a minimum low ESR
10µF ceramic output capacitor. A single resistor sets the
output voltage from 0.4V to 32V. Similarly, a single resis-
tor sets the power good threshold. The regulator typically
provides 0.1% line regulation and 0.1% load regulation.
The LT3086 has convenient programmable diagnostic
features. An output current monitor, that is typically
1/1000 of the output current, can set the current limit
lower than the typical 2.4A internal limit. A temperature
monitor, that is typically 10mV/°C where 250mV = 25°C,
can set the thermal limit lower than the typical 165°C
internal thermal limit.
For applications where the voltage error at the load is
caused by the resistance in the connections between the
LT3086 and the load, programmable cable drop compen-
sation cancels the error with a single resistor. Multiple
LT3086 regulators can be paralleled for higher load cur-
rents and heat spreading without the need for external
ballast resistors.
During load transients where the output overshoots
(regulated output voltages of 0.8V or higher), an internal
pull-down current activates pulling about 15mA from the
OUT pin to ground. The pull-down current is disabled when
the output is at or below regulation. The regulator and
the output overshoot pull-down turn off when the output
voltage is pulled higher than the input by typically 225mV.
Curves of OUT Over IN Shutdown Threshold appear in the
Typical Performance Characteristics section.
Internal protection circuitry includes reverse-battery pro-
tection, reverse-output protection, reverse-current protec-
tion, current limit with foldback and thermal shutdown.
Programming Output Voltage
The LT3086 has an output voltage range of 0.4 to 32V.
The output voltage is programmed with a single resistor,
RSET, connected from OUT to the SET pin, as shown in
Figure 1. The SET pin has an internal 50µA current source
to ground that generates a voltage drop across RSET. The
device servos the output to maintain the SET pin voltage
at 0.4V referenced to ground. Calculate the output voltage
using the formula in Figure 1. Curves of SET Pin Reference
Voltage and Current vs Temperature appear in the Typical
Performance Characteristics section.
3086 F01
IN
SHDN
IMON
ILIM
OUT
SET
GND
LT3086
VIN
VIMON
VOUT
RSET
RMON
V
OUT
=I
SET
R
SET
+0.4V
I
SET =50µA
R
SET =VOUT 0.4V
50µA
OUTPUT RANGE = 0.4V TO 32V
Figure 1. Programming Output Voltage
Table 1. Output Voltage RSET Values
VOUT (V)
RSET (Ω) VOUT ERROR FOR
SINGLE 1%IDEAL SINGLE 1% DUAL 1%
1 12k 12.1k 11.8k + 200 0.5%
1.2 16k 16.2k 15.8k + 200 0.8%
1.5 22k 22.1k 21.5k + 511 0.3%
1.8 28k 28k N/A 0%
2 32k 32.4 31.6k + 383 1.0%
2.5 42k 42.2k 41.2k + 825 0.4%
3.3 58k 57.6k 57.6k + 383 –0.6%
5 92k 90.9k 90.9k + 1.1k –1.1%
12 232k 232k N/A 0%
Table 1 shows the nearest 1% resistor values for some
common output voltages, along with the output error
caused by not using the ideal resistance value. These
errors can be as high as 1% because of the 2% spacing
between standard 1% resistors. If tighter output toler-
ance is required, consider using more accurate resistors.
Alternatively, the resistance of RSET can be fine-tuned by
adding a low value 1% resistor in series, see Table 1 dual
1% column.
Programming Power Good
The adjustable power good threshold is programmed
with a single resistor, RPGSET, similar to how the output
voltage is programmed by RSET. Similar to the SET pin,
RPWRGD determines the power good threshold with the
LT3086
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applicaTions inForMaTion
combination of a 0.4V reference voltage and a precision
50µA pull-down current. The power good signal pulls high
if the voltage on RPWRGD increases above 0.4V. Built-in
hysteresis of typically 0.6% exist for both the 0.4V volt-
age threshold and the 50µA current source. Connecting
a resistor between the RPWRGD and PWRGD pins can
increase the power good hysteresis. See the Application
circuits for an example.
based on the voltage at the load rather than the LT3086’s
output voltage. In order for the power good threshold to be
independent of the cable drop compensation’s modulation
of the LT3086’s output voltage as a function of load cur-
rent, connect a resistor between CDC and RPWRGD with the
same value as RCDC, the resistor between CDC and SET.
This technique avoids connecting the RPGSET resistor to
the load voltage through a long trace/wire and eliminates
potential stray signal coupling into the RPWRGD pin. See
the front page Typical Application circuit as an example.
Output Voltage Noise and Transient Response
The LT3086 regulator provides low output voltage noise
over a 10Hz to 100kHz bandwidth while operating at full
load. Output voltage noise is approximately 65nV/√Hz
over this frequency bandwidth at the unity gain output
voltage of 0.4V at 2.1A.
To lower output voltage noise for higher output voltages,
include a feedforward capacitor, CSET, from OUT to the
SET pin, as shown in Figure 3. A good quality, low leakage
capacitor is recommended. This capacitor bypasses the
voltage setting resistor, RSET, providing a low frequency
noise pole. With the use of 10nF for CSET, output voltage
noise decreases from 280µVRMS to 40µVRMS at 2.1A when
the output voltage is set to 5V.
3086 F03
IN
SHDN
IMON
ILIM
OUT
SET
GND
LT3086
VIN
V
IMON
V
OUT
COUT
RSET
RMON
CSET
Figure 2. Programming Power Good
Figure 3. Feedforward Capacitor for Improved
Transient Response
The PWRGD pin is the power good open-collector logic
output. An internal delay of typically 17µs exists only for
the rising edge (when the regulator output voltage rises
above the power good threshold) to reject noise or chatter
during startup. If the power good function is not needed,
leave the RPWRGD and PWRGD pins floating.
The power good threshold is typically programmed to 85%
to 95% of the regulated output voltage. Due to variations in
regulator parameters and resistor variations, it is not practi-
cal to set the power good threshold greater than 95% of the
output voltage. Account for load transients where the output
voltage droops momentarily before recovering. If increasing
output capacitance to reduce output voltage undershoot or
if setting the power good threshold lower is not possible, a
capacitor, CPGSET, from RPWRGD to ground can filter and delay
the output signal. This allows for a configurable deglitching
period before the power good threshold trips. For example,
consider an application with a nominal 1V output using 10µF
of output capacitance and the power good threshold set
for 90% of VOUT(NOMINAL). A 1.5A output load current step
momentarily undershoots VOUT below the 90% threshold
for more thans, thus triggering the PWRGD pin to pull
low. Using a CPGSET of greater than 270pF deglitches the
power good comparator and prevents the PWRGD pin from
pulling low for undershoot events less thans in duration.
For applications using cable drop compensation and re-
quiring a power good signal, calculate the value of RPGSET
3086 F02
IN
SHDN
IMON
ILIM
OUT
SET
GND
LT3086
VIN
VIMON
VOUT
VLOGIC
OR VOUT
RSET
RMON
PWRGD
RPWRGD
VPWRGD
RPGSET
CPGSET
(OPTIONAL)
RPGD
RPGSET =
xV
OUT(NOMINAL)
0.4V
50µA
WHERE 85% x 95% TYPICALLY
Higher values of output voltage noise are often measured
if care is not exercised with regard to circuit layout and
testing. Crosstalk from nearby active signal traces may
induce unwanted noise onto the LT3086’s output. Power
supply ripple rejection must also be considered. The
LT3086 regulator does not have unlimited power supply
rejection and will pass a small portion of the input noise
to the output.
Using a feedforward capacitor, CSET, has the added benefit
of improving transient response for output voltages greater
than 0.4V. With no feedforward capacitor, the settling time
LT3086
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Figure 4. Transient Response vs Feedforward Capacitor
TIME (µs)
0
OUTPUT VOLTAGE
DEVIATION (mV)
LOAD
CURRENT (A)
50
–100
–200
0
–250
2
–50
–150
3
1
050
3086 F04
80
10 60 704020 30
VIN = 5.5V
VOUT = 5V
COUT = 10µF
CSET = 0
CSET = 10nF
CSET = 1nF
CSET = 100pF
∆IL = 210mA TO 2.1A
and output voltage transients increase as the output voltage
is set above 0.4V. See Figure 4 and Transient Response
curves in the Typical Performance Characteristics section.
applicaTions inForMaTion
Figure 5. Output Current Monitor and External Current Limit
3086 F05
IN
SHDN
IMON/ILIM
OUT
SET
GND
LT3086
VIN
TO ADC
VIMON
VOUT
RSET
RMON
IMON =
I
OUT
1000
VIMON =IMON RMON
ILIMIT =1000 0.8V
RMON
rent limit, typically 2.4A, is always active and limits output
current even if the ILIM pin is grounded. In addition, inter-
nal current limit foldback overrides external current limit
if the VIN – VOUT differential voltage becomes excessive.
Note that the output current monitor represents not just
the load current, but the current into the output capacitor
as well. During startup and large load transients, the output
current monitor indicates the current required to charge
the output capacitor in addition to the load current. To
prevent external current limit from engaging prematurely,
set the external current limit above the maximum load
current to allow the output capacitor to recover without
being current limited.
For external current limits set for less than 1A, connect a
series 1k-10nF RC network from ILIM to ground to ensure
current limit loop stability. Adding an RC network from ILIM
to ground also delays the current monitor signal, allowing
output currents higher than the external current limit for a
limited duration. This is useful for applications with large
output capacitance that would otherwise trigger external
current limit during startup and large load transients,
slowing output voltage recovery. To guarantee external
current limit stability, ensure that the RC network from
ILIM to GND has a capacitor value equal to or greater than
10nF and the resistor value is between 0.01• C–0.6 and
1k. C is the capacitor value in units of farads. LTC does
not recommend an RC network other than the 1k-10nF
combination if using the cable drop compensation and
paralleling functions.
To configure the output current monitor and external cur-
rent limit correctly, decide on the necessary current limit
and full-scale monitor output voltage. Voltage is limited to
0.8V if IMON is tied to ILIM. External current limit is typically
set 10% to 20% above maximum load current to allow for
Start-up time is affected by the use of a CSET feedforward
capacitor. Start-up time is directly proportional to the size
of the feedforward capacitor and output voltage. Settling
time to 1% is approximately:
tSETTLE =
4.2V
OUT
C
SET
50µA
See the Start-Up Time vs CSET curve in the Typical Perfor-
mance Characteristics section. If the LT3086 is configured
for cable drop compensation, LT C does not recommend
using a feedforward capacitor because CSET filters the
CDC correction signal and transient response to load
current changes degrades.
Output Current Monitor and External Current Limit
Current out of the IMON pin is typically equal to 1/1000
of the regulator’s output current. The output current
monitor maintains accuracy across the full input voltage
range, even during dropout. A resistor, RMON, placed from
IMON to ground, sets the voltage scale factor for use with
analog-to-digital converters, as shown in Figure 5. For
example, with 442Ω for RMON, VIMON is set for 0.663V
when IOUT = 1.5A.
External current limit activates if the voltage on the ILIM
pin exceeds the typical 0.8V threshold. Tying the IMON and
ILIM pins together allows the user to program a desired
current limit based on the output current. An internal cur-
LT3086
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Figure 7. Equivalent Circuits of IMON and ILIM
Figure 8. Kelvin Sense Connection
Figure 9. Cable Drop Compensation
IN
IMON
ILIM
300mV
IOUT/1000
600mV
67k
IMON NOT TIED TO ILIM
LT3086
R
MON
120k
3086 F07
IN
IMON
ILIM
480mV
IOUT/1000
IMON TIED TO ILIM
LT3086
RMON
43k
applicaTions inForMaTion
large transient events and ILIM threshold variations. For
example, if the maximum load current is 1.5A and both
IMON and ILIM pins are tied together, an RMON scaling
resistor of 442Ω yields an external current limit of 1.8A.
If higher output current monitor voltages are needed, the
DFN package offers the ability to separate the IMON and
ILIM pins with a resistor, as shown in Figure 6. To prevent
saturation in the IMON output device, choose RMON so that
VIMON is at least 0.6V less than VIN. If external current is
not needed, ground the ILIM pin.
Output current monitor accuracy for very low output cur-
rents is limited by the offset in the current monitor amplifier
and parasitic current paths. The equivalent circuit of the
parasitic current paths are shown in Figure 7. With zero
output load current, the current into RMON is typically
11µA when the IMON and ILIM pins are tied together. As
a result, load currents between 0mA and 11mA typically
cannot be measured. See Current Monitor Offset curves
in the Typical Performance Characteristics section.
Load Regulation and Cable Drop Compensation
Output load regulation for the LT3086 is typically 0.1%.
Optimal regulation is obtained when the RSET feedback
resistor is connected to the OUT pin of the regulator. In
high current applications, small voltage drops appear due
to the resistances of PCB traces or wires between the
regulator and the load. These drops may be eliminated
by connecting RSET directly to the output at the load as
shown in Figure 8. Note that the voltage drop across ROUT
and RRTN add to the dropout voltage of the regulator. The
voltage drop across RGND should also be minimized to
reduce output voltage error due to ground pin current.
See GND Pin Current curves in the Typical Performance
Characteristics section.
The LT3086 has cable drop compensation (CDC) func-
tionality that allows delivery of well regulated voltage
to remote loads using only two wires of known fixed
resistance. Compensation is user programmed by con-
necting a resistor, RCDC, between the SET and CDC pins,
as shown in Figure 9.
At zero load current, the CDC pin typically regulates to
the same voltage as the SET pin. The voltage decreases
at a rate equal to 1/3 of the change in IMON voltage. For
example, if VIMON increases from 0 to 0.6V, VCDC decreases
3086 F09
IN
SHDN
IMON
ILIM
OUT
SET
GND
LT3086
VIN
CLOAD
(OPTIONAL)
RSET
RCDC
RMON
CDC COUT
RLINE2
R
LINE1
L
LINE1
RESR
(OPTIONAL)
LLINE2
LOAD
RCDC =
R
MON
R
SET
3000R
WIRE
RWIRE =RLINE1 +RLINE2
3086 F08
IN
SHDN
IMON
ILIM
OUT
SET
GND
LT3086
VIN
RMON RGND
RRTN
R
OUT
RSET
LOAD
Figure 6. Separate IMON and ILIM (DFN Package Only)
3086 F06
IN
SHDN
IMON
ILIM
OUT
SET
GND
LT3086
VIN
VIMON
TO ADC
V
OUT
RSET
RLIM
ROPT
(DFN PACKAGE ONLY)
R
MON
=R
LIM
+R
OPT
I
LIMIT =1000 0.8V
RLIM
LT3086
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Figure 10. Transient Response with Cable Drop Compensation
0 80 160 560 640 720
800
240 320 400 480
TIME (µs)
OUTPUT VOLTAGE (V)
LOAD
CURRENT (A)
3086 F10
5.8
5.6
5.2
4.8
4.4
2
5.4
5.0
4.6
4.2
1
0
VIN = 6V
RMON = 357Ω
RWIRE = 0.24Ω
RCDC = 46.4k
RSET = 92k
COUT = 10µF
CLOAD = 0
VOUT WITH CDC
VLOAD WITHOUT CDC
VLOAD WITH CDC
∆ILOAD = 0.5A TO 1.5A
applicaTions inForMaTion
by 0.2V. As a result, the current that flows through RCDC
is proportional to load current which increases the voltage
across RSET, effectively increasing output voltage. RCDC is
selected using the following equation so that the voltage
at the OUT pin increases to cancel the voltage drop in the
cables connected to the load.
RCDC =
R
MON
R
SET
3000R
WIRE
where RWIRE is the total resistance of the supply and return
cabling connecting the LT3086 to the load.
Figure 10 shows the transient response with cable drop
compensation. With compensation, the output voltage at
the load remains nearly constant. Note that the transient
voltage droop in output voltage is about the same as the
voltage droop with no compensation, but with the output
voltage returning to the correct compensated voltage.
IN SHDN
IMON
ILIM
OUT
SET
GND
LT3086
MASTER
VOUT
V
IN
VTRACK = VILIM(MASTER)
RSET
RMON 3086 F011
IN
SHDN
IMON
ILIM
OUT
SET
TRACK
GND
LT3086
SLAVE(S)
RMON
Figure 11. Master/Slave(s) Configuration for Paralleling
There are limits to the amount of voltage drop that can
be compensated using cable drop compensation. Using
cable drop compensation subjects load regulation to the
variability of the current monitor voltage output and the
cabling resistance. LTC recommends limiting cable drop
compensation to 20% of VOUT for applications needing
good regulation. The limiting factor is variations in wire
temperature as copper wire resistance changes about
19% for a 50°C temperature change. If output regulation
requirements are loose (e.g., when using a secondary
regulator), cable drop compensation of up to 50% may
be used.
Noise from the current monitor output affects noise seen
at the output. Filtering the current monitor output with an
RC network from ILIM to ground is effective at reducing
this noise source, especially at light loads. Consult the
Output Current Monitor and External Current Limit section
for more information
Paralleling Multiple Regulators
The LT3086 has been specifically designed to make paral-
leling multiple regulators together easy. Paralleling enables
applications to increase total output current and to spread
heat dissipated by the regulator over a wider area on the
PCB. The parallel scheme is based on a master/slave
principle, where one LT3086 is designated as master,
and the other regulators act as slaves with active sharing
of total load current, as shown in Figure 11. The slave’s
internal current tracking amplifier compares the current
monitor output from the master with the current monitor
output seen at the slave’s ILIM pin, and servos the slave’s
output current to match the master’s.
If long cables are used, an additional supply bypass
capacitor, CLOAD, should be added directly to the load
to handle large load transient conditions. COUT must still
directly connect to the OUT pin to ensure stable operation
of the LT3086, minimizing output capacitor ESR and ESL.
Long cables have inductance where a resonance forms
between the wire inductance, LWIRE and CLOAD. Damping
is accomplished by adding series resistance, RESR, to
CLOAD. The value of RESR is approximately:
RESR =2LWIRE
CLOAD
LT3086
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applicaTions inForMaTion
The master LT3086 is connected exactly the same as a
single regulator where its output current monitor voltage
seen at its ILIM pin is used as the common current tracking
signal. The slave devices connect this signal to their TRACK
pins to make their output current equal to the master’s.
The TRACK pin has an internal pull-up current that is
typically 15µA at 0.75V. When the TRACK pin is unused,
the pin is pulled up and clamped at 1.25V, disabling the
current tracking amplifier. When the TRACK pin is con-
nected to the master current tracking signal, the TRACK
pin voltage is pulled below the 1.2V threshold, enabling the
current tracking amplifier and disabling the slave’s 50µA
reference current, ISET. Disabling the reference current
ensures that the master is the only device controlling the
output voltage. Set the maximum master current tracking
signal to less than 0.8V to prevent external current limit
from triggering prematurely. To prevent the slave current
tracking amplifier from ever being disabled, the slave
TRACK pin must be tied to the master ILIM pin. The master
ILIM pin has an internal 1V clamp that is below the slave
1.2V current tracking amplifier enable threshold.
When multiple slaves are used, a smaller master RMON
resistor should be used to compensate for the pull-up
currents from all the TRACK pins of the slaves. For ex-
ample, a master sourcing 2.1A typically has 0.697V at its
ILIM pin with an RMON resistor of 332Ω. Referring to the
TRACK pin pull-up current curve in the Typical Perfor-
mance Characteristics, with 0.697V on the TRACK pin,
each slave typically adds 15µA to the master’s 2.1mA
IMON output. For an application with 3 slaves connected,
decrease RMON’s value to:
RMON =
0.697V
[2.1mA +315µA
( )
]=325
The closest 1% resistor value equals 324Ω.
All slave regulators must have their SET pins connected
to the master SET pin. The TRACK amplifier operates by
adjusting the slave internal reference voltage slightly as
a function of the difference in master and slave current
monitor voltages. This has a strong effect on the slave
output current, which forces the slave output current to
match the master.
Mismatch between master and slave internal reference
voltages and current monitor outputs, offset in the slave
TRACK amplifier and TRACK pin pull-up currents all
contribute to output current sharing error. In the case of
negative offset, a slave runs less current than the master.
At very light loads, negative offset enables the slave output
overshoot pull-down circuit, forcing the master to supply
current to keep the output voltage within regulation. As a
result, quiescent current may increase for very light loads
in the master/slave configuration.
In some applications, multiple regulators may be spaced
some distance apart to optimize heat distribution. That
makes the use of low resistance traces important to con-
nect each regulator to the local ground system and to avoid
ground loops created by load currents. Ground currents
can be as high as 30mA at 1.5A and 50mA at 2.1A, for
each regulator. Limiting differential ground pin voltages to
less than 10mV minimizes tracking errors. Ground trace
resistance between master and slaves should be less than
10mV/30mA = 0.33Ω at 1.5A load, and 10mV/50mA =
0.2Ω for 2.1A load.
Output Capacitance
The LT3086 regulator is stable with a wide range of output
capacitors. The ESR of the output capacitor affects stabil-
ity, most notably with small capacitors. Use a minimum
output capacitor of 10µF with an ESR of 0.1Ω or less to
prevent oscillations. The output load transient response is
a function of output capacitance. Larger values of output
capacitance decrease the peak deviations and provide im-
proved transient response for larger load current changes.
For applications with large load current transients, a low
ESR ceramic capacitor in parallel with a bulk tantalum
capacitor often provides an optimally damped response.
For example, a 47µF tantalum capacitor with ESR = 0.1Ω
in parallel with the 10µF ceramic capacitor with ESR <
0.01Ω reduces output deviation by about 2:1 for large
transient loads and increases loop phase margin.
Give extra consideration to the use of ceramic capacitors.
Manufacturers make ceramic capacitors with a variety of
dielectrics, each with different behavior across tempera-
ture and applied voltage. The most common dielectrics
are specified with EIA temperature characteristic codes
of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics
LT3086
22
3086fb
For more information www.linear.com/LT3086
DC BIAS VOLTAGE (V)
CHANGE IN VALUE (%)
3086 F12
20
0
–20
–40
–60
–80
–100 04810
2 6 12 14
X5R
Y5V
16
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
TEMPERATURE (°C)
–50
40
20
0
–20
–40
–60
–80
–100 25 75
3086 F13
–25 0 50 100
125
Y5V
CHANGE IN VALUE (%)
X5R
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
Figure 12. Ceramic Capacitor DC Bias Characteristics
Figure 13. Ceramic Capacitor Temperature Characteristics
applicaTions inForMaTion
provide high C-V products in a small package at low cost,
but exhibit strong voltage and temperature coefficients, as
shown in Figures 12 and 13. When used with a 5V regulator,
a 16V 10µF Y5V capacitor can exhibit an effective value
as low asF toF for the DC bias voltage applied, and
over the operating temperature range. The X5R and X7R
dielectrics yield much more stable characteristics and are
more suitable for use as the output capacitor.
The X7R type works over a wider temperature range and
has better temperature stability, while the X5R is less
expensive and is available in higher values. Care still must
be exercised when using X5R and X7R capacitors; the X5R
and X7R codes only specify operating temperature range
and maximum capacitance change over temperature.
Capacitance changes due to DC bias is less with X5R and
X7R capacitors, but can still be significant enough to drop
capacitor values below appropriate levels. Capacitor DC
bias characteristics tend to improve as component case
size increases, but expected capacitance at operating
voltage should be verified.
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or mi-
crophone works. For a ceramic capacitor, the stress is
induced by vibrations in the system or thermal transients.
The resulting voltages produced can cause appreciable
amounts of noise.
Input Capacitance
Low ESR ceramic input bypass capacitors are acceptable for
applications with short input and ground leads. However,
applications connecting a power supply to the LT3086
using long wires are prone to voltage spikes, reliability
concerns and application-specific board oscillations.
The input wire inductance found in many battery-powered
applications, combined with the low ESR ceramic capacitor,
forms a high-Q LC resonant tank circuit. In some instances
this resonant frequency beats against the output current
dependent LDO bandwidth and interferes with proper
operation. Simple circuit modifications are then required.
This behavior is not indicative of LT3086 instability, but
is a common application issue.
The self-inductance, or isolated inductance, of a wire is
directly proportional to its length. Wire diameter is not a
major factor on its self-inductance. For example, the self-
inductance of a 2-AWG isolated wire (diameter = 0.26") is
about half the self-inductance of a 30-AWG wire (diameter
= 0.01"). One foot of 30-AWG wire has approximately
465nH of self-inductance. Tw o methods can reduce wire
self-inductance. One method divides the current flowing
towards the LT3086 between two parallel conductors. In
this case, the farther apart the wires are from each other,
the more the self-inductance is reduced; up to a 50%
reduction when placed a few inches apart. Splitting the
wires connects two equal inductors in parallel, but placing
them in close proximity creates mutual inductance add-
ing to the self-inductance. The second and most effective
way to reduce overall inductance is to place both forward
LT3086
23
3086fb
For more information www.linear.com/LT3086
applicaTions inForMaTion
and return current conductors (the input and GND wires)
in very close proximity. Tw o 30-AWG wires separated by
only 0.02", used as forward- and return-current conduc-
tors, reduce the overall self-inductance to approximately
one-fifth that of a single isolated wire.
If a battery, mounted in close proximity, powers the LT3086,
a 10μF input capacitor suffices for stability. However, if a
distant supply powers the LT3086, use a larger value input
capacitor. Use a rough guideline of 1μF (in addition to the
10μF minimum) per 8 inches of wire length. The minimum
input capacitance needed to stabilize the application also
varies with power supply output impedance variations.
Placing additional capacitance on the LT3086’s output also
helps. However, this requires an order of magnitude more
capacitance in comparison with additional LT3086 input
bypassing. Series resistance between the supply and the
LT3086 input also helps stabilize the application; as little
as 0.1Ω to 0.5Ω suffices. This impedance dampens the
LC tank circuit at the expense of dropout voltage. A bet-
ter alternative is to add additional input capacitance with
higher ESR at the input, such as tantalum or electrolytic
capacitors, or by adding resistance in series with a low
ESR ceramic capacitor.
Overload Recovery
Like many IC power regulators, the LT3086 has safe
operating area protection. The safe operating area protec-
tion decreases current limit as input-to-output voltage
increases, and keeps the power transistor inside a safe
operating region for all values of input-to-output voltage.
The LT3086 provides some output current at all values of
input-to-output voltage up to the specified 45V operational
maximum. Current limit foldback overrides external current
limit (if used) if VINVOUT voltage differential becomes
excessive.
When power is first applied, the input voltage rises and the
output follows the input; allowing the regulator to start-up
into very heavy loads. During start-up, as the input voltage
is rising, the input-to-output voltage differential is small,
allowing the regulator to supply large output currents.
With a high input voltage, a problem can occur wherein
the removal of an output short will not allow the output
to recover. Other regulators, such as the LT1083/LT1084/
LT1085 family and LT1764A also exhibit this phenomenon,
so it is not unique to the LT3086. The problem occurs with
a heavy output load when the input voltage is high and the
output voltage is low. Common situations are immediately
after the removal of a short-circuit or if the shutdown pin
is pulled high after the input voltage is already turned on.
The load line intersects the output current curve at two
points creating two stable output operating points for the
regulator. With this double intersection, the input power
supply needs to be cycled down to zero and brought up
again for the output to recover.
Thermal Considerations
The power handling capability of the LT3086 is limited
by the maximum rated junction temperature (125°C for
LT3086E, LT3086I, LT3086MP or 150°C for LT3086H).
Three components comprise the power dissipated by the
device:
1. Output current multiplied by the input/output voltage
differential:
IOUT • (VIN − VOUT),
2. GND pin current multiplied by the input voltage:
IGNDVIN, and
3. Current monitor current multiplied by the input/current
monitor voltage differential:
IMON • (VIN − VIMON)
GND pin current is determined using the GND Pin Current
curves in the Typical Performance Characteristics section.
Power dissipation equals the sum of the three components
listed above.
The LT3086 regulator has internal thermal limiting that pro-
tects the device during overload conditions. For continuous
normal conditions, the maximum junction temperature of
125°C (E-grade, I-grade, MP-grade) or 150°C (H-grade)
must not be exceeded. Carefully consider all sources of
thermal resistance from junction-to-ambient including
other heat sources mounted in proximity to the LT3086.
The underside of the LT3086 DFN and TSSOP packages
have exposed metal (10.5mm2) from the lead to the die
attachment. These packages allow heat to directly transfer
from the die junction to the printed circuit board metal.
The dual-in-line pin arrangement allows metal to extend
LT3086
24
3086fb
For more information www.linear.com/LT3086
applicaTions inForMaTion
beyond the ends of the package on the topside (component
side) of a PCB. Connect this metal to GND on the PCB.
The multiple IN and OUT pins of the LT3086 also assist
in spreading heat to the PCB.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes also can spread the heat generated by
power devices.
Tables 2 and 3 list thermal resistance for several topside
copper areas on a fixed board size. All measurements were
taken in still air on a 4-layer FR-4 board with 1oz solid
internal planes and 2oz top/bottom external trace planes
with a total board thickness of 1.6mm. The four layers
were electrically isolated with no thermal vias present.
Achieving low thermal resistance necessitates attention
to detail and careful PCB layout. For more information
on thermal resistance and high thermal conductivity
test boards, refer to JEDEC standard JESD51, notably
JESD51-12 and JESD51-7. The use of thermal vias,
increased copper weight, and air flow, will improve the
resultant thermal resistance.
Table 2. Measured Thermal Resistance for DHD and FE Package
COPPER AREA
BOARD AREA
(mm2)
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
TOPSIDE*
(mm2)
BACKSIDE
(mm2)
2500 2500 2500 25°C/W
1000 2500 2500 26°C/W
225 2500 2500 28°C/W
100 2500 2500 33°C/W
*Device is mounted on topside
Table 3. Measured Thermal Resistance for R Package
COPPER AREA
BOARD AREA
(mm2)
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
TOPSIDE*
(mm2)
BACKSIDE
(mm2)
2500 2500 2500 15°C/W
1000 2500 2500 16°C/W
225 2500 2500 19°C/W
*Device is mounted on topside
Measured Thermal Resistance for T7 Package
Thermal resistance (junction-to-case) = 3°C/W.
The LT3086 has the ability to check thermal performance
by observing the output current and temperature monitor
pins. The effects of heat sinking, the enclosure, and any
air movement can be instantly analyzed without special
instrumentation.
Calculating Junction Temperature
Example: Given an output voltage of 5V, an input voltage
range of 6V ±5%, a maximum output current range of 1A
with 698Ω for RMON, and a maximum ambient temperature
of 75°C, what will the maximum junction temperature be?
The power dissipated by the device equals:
IOUT(MAX) • (VIN(MAX) − VOUT) + IGNDVIN(MAX) +
IMON(MAX) • (VIN(MAX) − VIMON(MAX))
where,
IOUT(MAX) = 1A
VIN(MAX) = 6.3V
IGND at (IOUT = 1A, VIN = 6.3V) = 11mA
VIMON at (IOUT = 1A, RMON = 698Ω) = 0.698V
So:
P = 1A • (6.3V − 5V) + 11mA • 6.3V +
1mA • (6.3V − 0.698V) = 1.38W
Using a DFN package, the thermal resistance will be in the
range of 25°C/W to 33°C/W depending on the topside cop-
per area. So the junction temperature rise above ambient
approximately equals:
1.38W • 30°C/W = 41.4°C
The maximum junction temperature equals the maximum
ambient temperature plus the maximum junction tempera-
ture rise above ambient or:
TJMAX = 75°C + 41.4°C = 116.4°C
Protection Features
The LT3086 regulator incorporates several protection
features that make it ideal for use in battery-powered
circuits. In addition to the normal protection features
LT3086
25
3086fb
For more information www.linear.com/LT3086
Figure 16. OUT Over IN Shutdown Threshold
Figure 14. Reverse-Output Current
Figure 15. Output Overshoot Pull-Down Current
applicaTions inForMaTion
associated with monolithic regulators, such as current
limiting and thermal limiting, the devices also protect
against reverse-input voltages, reverse-output voltages,
and reverse-output-to-input voltages.
Current limit protection and thermal overload protection
protect the device against current overload conditions at
the output of the device. The typical thermal shutdown
temperature is 165°C and incorporates aboutC of hys-
teresis. For normal operation, do not exceed the maximum
rated junction temperature of 125°C (LT3086E, LT3086I,
LT3086MP) or 150°C (LT3086H).
The LT3086 IN pin withstands reverse voltages of 45V. The
device limits current flow to less than 2mA (typically less
thanA) and no negative voltage appears at OUT. The
device protects both itself and the load against batteries
that are plugged in backwards.
The LT3086 incurs no damage if its output is pulled be-
low ground. If the input is left open-circuit or grounded,
the output can be pulled below ground by 36V. No cur-
rent flows through the pass transistor from the output.
However, current flows in (but is limited by) the feedback
resistors RSET, that sets the output voltage, and RRPWRGD,
that sets the power good threshold. Current flows from
the internal clamps in the SET and RPWRGD pins to the
external circuitry pulling OUT below ground. If the input
is powered by a voltage source, the device protects itself
by turning off the power device when the internal clamps
activate. If Schottky diodes are used to prevent the SET
and RPWRGD pins from activating their internal clamps, the
output sources current equal to its current limit capability
and the LT3086 protects itself by thermal limiting. In this
case, grounding the SHDN pin turns off the device and
stops the output from sourcing current. Reverse current
flow follows the curve shown in Figure 14.
The LT3086 incurs no damage if the SET and RPWRGD
pins are pulled above ground up to 36V. If the input is
left open-circuit or grounded, the SET pin performs like a
large resistor (typically 80k) in series with a diode.
In circuits where a secondary supply raises the output
voltage above the regulated voltage set by RSET, the output
overshoot circuitry pulls current from the output pin to
ground as long as the output voltage is below the input
voltage. Output overshoot current follows the curve shown
OUTPUT VOLTAGE (V)
3086 F14
0 20
32
4 24 28168 12
REVERSE OUTPUT CURRENT (mA)
0.6
0.5
0.3
0.1
0.4
0.2
0
TJ = 25°C
VIN = 0V
VOUT = VSET = VRPWRGD
CURRENT FLOWS THROUGH
PINS TO GROUND
OUT, RPWRGD
SET
OUTPUT VOLTAGE (V)
3086 F15
0 20
36
324 24 28168 12
OUTPUT OVERSHOOT PULL-DOWN (mA)
30
25
15
5
20
10
0
TJ = 25°C
VIN = 0V
VOUT = VSET = VRPWRGD
CURRENT FLOWS THROUGH
OUT PIN TO GND
TEMPERATURE (°C)
–75
OUT OVER IN SHUTDOWN THRESHOLD (mV)
300
275
225
175
150
100
50
250
200
125
75
25
0100–25
3086 F16
175
0–50 125 1507525 50
ON TO OFF
OFF TO ON
in Figure 15. When the output voltage is pulled above
the input by typically 225mV, the LT3086 shuts down as
shown in Figure 16 and the 15mA overshoot pull-down
current source turns off.
LT3086
26
3086fb
For more information www.linear.com/LT3086
Typical applicaTions
2.5V Low Noise Regulator with Power Good
1.2V, 1.5A Low Noise Regulator with 1.8A External Current Limit
5 White LED Driver with PWM Dimming and LED Open Detection
10µF
IN
TEMP
I
LIM
GND
OUT
LT3086 R
SET
42.2k
1%
SET
V
IN
3.1V TO 13V
V
OUT
2.5V AT 2.1A
10µF
SHDN
C
SET
10nF
I
MON
VTEMP
10mV/°C
25°C = 250mV PWRGD VPWRGD HIGH
WHEN
V
OUT
> 90% of 2.5V
R
PWRGD
RPGD
100k
R
PGSET
37.4k
1%
3086 TA09
10µF
IN
TEMP
I
LIM
SHDN
GND
OUT
LT3086 R
SET
15.8k
1%
SET
V
IN
1.65V TO 16V
V
OUT
1.2V AT 1.5A
10µF
C
SET
10nF
I
MON
VTEMP
10mV/°C
25°C = 250mV
200Ω
1%
RMON
442Ω
1%
VMON
0.8V AT 1.8A
FULL-SCALE
3086 TA10
3086 TA11
10µF
IN
I
MON
I
LIM
SHDN
GND
OUT
LT3086
RMON
800Ω
R
SET
**
1%
SET
V
IN*V
OUT
R1
1k
C1
10nF
10µF
NOTE: ADJUST RMON TO SET MAXIMUM LED CURRENT (SET TO 800Ω FOR 1A)
DRIVE PWM LOW TO TURN OFF LED STRING (PULSE TO DIM)
*INPUT VOLTAGE REQUIRED IS DEPENDENT ON THE LED STRING VOLTAGE
**CHOOSE R
SET
AND R
PGSET
BASED ON LED STRING
PWRGD
R
PWRGD
RPGD
100k
1%
R
PGSET
**
1%
VPWRGD HIGH
FOR OPEN LED
CONDITION
PWM
LT1004-1.2
R2
3.32k
1%
R3
9.09k
1%
R4
100k
1%
LT3086
27
3086fb
For more information www.linear.com/LT3086
Typical applicaTions
Ensuring External Current Limit Stability for ILIM ≤ 1A Increasing Current Monitor Output Voltage
Increasing Power Good Hysteresis (Ex: 2%)
IN
SHDN
IMON
VIMON
800mV at 250mA
ADDITIONAL
R-C NETWORK
ILIM
OUT
SET
GND
LT3086
V
IN
12.5V TO 40V
V
OUT
12V AT 200mA
10µF
10µF
RSET
232k
1%
RLIM
3.24k
1%
R1
1k
3086 TA04
CSET
10nF
C1
10nF
IN
SHDN
IMON
VIMON = 1V/A
ILIMIT = 1.5A ILIM
OUT
SET
GND
LT3086
(DHD ONLY)
V
IN
3V TO 19V
V
OUT
2.5V AT 1.2A
10µF
10µF
RSET
41.2k
1%
RLIM
536Ω
1%
R1
464Ω
1%
3086 TA05
CSET
10nF
RLIM =0.8V
ILIMIT
1000
3086 TA06
IN
SHDN
IMON
ILIM
OUT
SET
GND
LT3086
V
OUT
3.3V AT 1.5A
RSET
57.6k
1% RPGSET
51.1k
1%
RMON
442Ω
1%
V
IN
3.85V TO 18V
10µF 10µF
PWRGD
RPWRGD
VPWRGD
RHYS
3.65M
1%
RPGD
100k
RHYS =VX100 PVOUT 0.4V
( )
VOUT HHINT
( )
50µA
( )
WHERE, VX = RPGD TERMINATION VOLTAGE = VOUT
P = POWER GOOD TRIP THRESHOLD (% OF VOUT)
H = DESIRED PERCENTAGE HYSTERESIS
H
INT
= 0.6 (INTERNAL PERCENTAGE HYSTERESIS)
Adjustable Voltage Controlled Current Source
3086 TA12
10µF
IN
SET
I
LIM
SHDN
GND
OUT
LT3086
TRACK
V
IN*
10µF
I
MON
VTRACK
ADJUST FROM 0V TO 750mV
FOR 0A TO 2.1A CONSTANT CURRENT
*RESTRICT INPUT VOLTAGE RANGE TO LIMIT POWER DISSIPATION
AND PREVENT FOLDBACK CURRENT LIMIT FROM INTERFERING
WITH PROPER OPERATION
RMON
357Ω
1%
R1
1k
C1
10nF
400mV
IN
GND
OUT
LT6650 FB
1µF
1µF
LOAD
LT3086
28
3086fb
For more information www.linear.com/LT3086
Typical applicaTions
Load Current Monitoring Using Power Good
IN
SHDN
IMON
ILIM
OUT
SET
PWRGD
RPWRGD
GND
LT3086
V
IN
3.85V TO 18V
V
OUT
3.3V AT 1.5A
10µF 10µF
C1 (OPTIONAL, FOR
POWERGOOD
FLAG DELAY)
RSET
57.6k
1%
R1
169Ω
1%
R2
324Ω
1%
RPGD
100k
3086 TA03
VPWRGD
HIGH WHEN
ILOAD > 1.25A
I
LIMIT
=1.6A
R1=0.8V
ILIMIT
1000R2
R2=0.4V
ILOAD
1000
Input Undervoltage Detector Using Power Good
Programming Thermal Limit Temperature
3086 TA07
IN
SHDN
IMON
ILIM
OUT
SET
GND
LT3086
V
OUT
3.3V AT 1.5A
RSET
57.6k
1%
RPGSET
71.5k
1%
RMON
442Ω
1%
V
IN
4V TO 18V
10µF 10µF
PWRGD
RPWRGD
VPWRGD HIGH
WHEN
VIN > 4V
RPGD
100k
IN
SHDN
IMON
TEMP
VTEMP
10mV/°C
25°C = 250mV
124°C THERMAL LIMIT
ILIM
OUT
SET
GND
LT3086
V
IN
2.4V TO 12V
V
OUT
1.8V AT 2.1A
10µF 10µF
RSET
28k
1%
RMON
332Ω
1%
RTEMP
12.4k
1% 3086 TA08
CSET
10nF
R
TEMP =
V
TEMP
100µA
Paralleling Tw o Regulators for 5V, 4.2A
VIN
5.7V TO 15V
10µF10µF
10µF10µF
CSET
10nF
IN SHDN
IMON
ILIM
OUT
SET
GND
LT3086
MASTER
VOUT
5V AT 4.2A
VOUT
VILIM(MASTER)
0.7V AT 4.2A
RSET
90.9k
1% VTEMP(SLAVE)
10mV/°C
25°C = 250mV
VTEMP(MASTER)
10mV/°C
25°C = 250mV 1.1k
1%
RMON
332Ω
1% 3086 TA02
IN
SHDN
IMON
ILIM
OUT
SET
TRACK
GND
LT3086
SLAVE
RMON
332Ω
1%
TEMP TEMP
RPWRGD
RPGSET
82.5k
1%
RPGD
100k
VPWRGD PWRGD
LT3086
29
3086fb
For more information www.linear.com/LT3086
4.00 ±0.10
(2 SIDES)
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJGD-2) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
2.44 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
4.34 ±0.10
(2 SIDES)
18
169
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DHD16) DFN REV A 1113
0.25 ±0.05
PIN 1
NOTCH
0.50 BSC
4.34 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
2.44 ±0.05
(2 SIDES)
3.10 ±0.05
0.50 BSC
0.70 ±0.05
4.50 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
DHD Package
16-Lead Plastic DFN (5mm × 4mm)
(Reference LTC DWG # 05-08-1707 Rev A)
package DescripTion
Please refer to http://www.linear.com/product/LT3086#packaging for the most recent package drawings.
LT3086
30
3086fb
For more information www.linear.com/LT3086
FE16 (BB) TSSOP REV K 0913
0.09 – 0.20
(.0035 – .0079)
0° 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 4 5678
10 9
4.90 – 5.10*
(.193 – .201)
16 1514 13 12 11
1.10
(.0433)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC
2.94
(.116)
0.195 – 0.30
(.0077 – .0118)
TYP
2
RECOMMENDED SOLDER PAD LAYOUT
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60
±0.10
1.05 ±0.10
2.94
(.116)
3.05
(.120)
3.58
(.141)
3.58
(.141)
4.70
(.185)
MILLIMETERS
(INCHES)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
SEE NOTE 4
NOTE 5
NOTE 5
6.40
(.252)
BSC
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev K)
Exposed Pad Variation BB
5. BOTTOM EXPOSED PADDLE MAY HAVE METAL PROTRUSION
IN THIS AREA. THIS REGION MUST BE FREE OF ANY EXPOSED
TRACES OR VIAS ON PBC LAYOUT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
DETAIL A
DETAIL A IS THE PART OF THE
LEAD FRAME FEATURE FOR
REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.56
(.022)
REF
0.53
(.021)
REF
DETAIL A
package DescripTion
Please refer to http://www.linear.com/product/LT3086#packaging for the most recent package drawings.
LT3086
31
3086fb
For more information www.linear.com/LT3086
R (DD7) 0416 REV G
0.013 – 0.023
(0.330 – 0.584)
0.095 – 0.115
(2.413 – 2.921)
0.004+0.008
–0.004
( )
0.102+0.203
–0.102
0.050 ±0.012
(1.270 ±0.305)
0.06 ±0.01
(1.524 ±0.254)
TYP
0.045 – 0.055
(1.143 – 1.397)
0.165 – 0.180
(4.191 – 4.572)
0.026 – 0.035
(0.660 – 0.889)
TYP
0.143+0.012
–0.020
( )
3.632+0.305
–0.508
0.050
(1.270)
BSC
0.330 – 0.370
(8.382 – 9.398)
0.06 ±0.01
(1.524 ±0.254)
TYP
0.390 – 0.415
(9.906 – 10.541)
15° ±5°
0.55 ±0.05
(13.970 ±1.270)
0.420
0.350
0.585
0.090
0.035
0.050
0.325
0.205
0.080
0.585
RECOMMENDED SOLDER PAD LAYOUT
FOR THICKER SOLDER PASTE APPLICATIONS
RECOMMENDED SOLDER PAD LAYOUT
0.090
0.0350.050
0.420
0.276
0.320
NOTE:
1. DIMENSIONS IN INCH/(MILLIMETER)
2. DRAWING NOT TO SCALE
0.30 ±0.02
(7.620 ±0.508)
0.085 ±0.01
(2.159 ±0.254)
0.18 ±0.01
(4.572 ± 0.254)
0.06 ±0.01
(1.524 ±0.254)
0.30 ±0.02
(7.620 ±0.508)
0.06 ±0.01
(1.524 ±0.254)
0.25 ±0.02
(6.350 ±0.508)
BOTTOM VIEW OF DD PAK
HATCHED AREA IS SOLDER PLATED
COPPER HEAT SINK
R Package
7-Lead Plastic DD Pak
(Reference LTC DWG # 05-08-1462 Rev G)
DETAIL A
DETAIL A
0° – 7° TYP0° – 7° TYP
package DescripTion
Please refer to http://www.linear.com/product/LT3086#packaging for the most recent package drawings.
LT3086
32
3086fb
For more information www.linear.com/LT3086
.050
(1.27)
.026 – .036
(0.660 – 0.914)
T7 (TO-220) 0801
.135 – .165
(3.429 – 4.191)
.700 – .728
(17.780 – 18.491)
.045 – .055
(1.143 – 1.397)
.165 – .180
(4.191 – 4.572)
.095 – .115
(2.413 – 2.921)
.013 – .023
(0.330 – 0.584)
.620
(15.75)
TYP
.155 – .195*
(3.937 – 4.953)
.152 – .202
(3.860 – 5.130)
.260 – .320
(6.604 – 8.128)
.147 – .155
(3.734 – 3.937)
DIA
.390 – .415
(9.906 – 10.541)
.330 – .370
(8.382 – 9.398)
.460 .500
(11.684 12.700)
.570 – .620
(14.478 – 15.748)
.230 – .270
(5.842 – 6.858)
BSC
SEATING PLANE
*MEASURED AT THE SEATING PLANE
T7 Package
7-Lead Plastic TO-220 (Standard)
(Reference LTC DWG # 05-08-1422)
package DescripTion
Please refer to http://www.linear.com/product/LT3086#packaging for the most recent package drawings.
LT3086
33
3086fb
For more information www.linear.com/LT3086
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 6/14 Added MP-grade for TSSOP, DD-Pak, and TO-220 packages 2 to 4
Added EC Table line item for Minimum Load Current and Note 16 3, 5
Added and modified two GND Pin Current curves, two PSRR at 1A curves, two Line Regulation curves and modified
VOUT Noise curve
7 to 12
Updated Thermal Resistance for DHD, FE and R packages 2, 24
Updated DHD Package Description 29
B 8/16 Added H-grade for TSSOP package 2 to 5, 23, 25
LT3086
34
3086fb
For more information www.linear.com/LT3086
LINEAR TECHNOLOGY CORPORATION 2013
LT 0816 REV B • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507 www.linear.com/LT3086
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LT1764/
LT1764A
3A, Fast Transient Response, Low
Noise LDO
340mV Dropout Voltage, Low Noise: 40μVRMS, VIN: 2.7V to 20V, TO-220 and DD Packages, -A
Version Stable Also with Ceramic Capacitors
LT1963/
LT1963A
1.5A, Low Noise, Fast Transient
Response LDO
340mV Dropout Voltage, Low Noise: 40μVRMS, VIN: 2.5V to 20V, -A Version Stable with Ceramic
Capacitors, TO-220, DD-Pak, SOT-223 and SO-8 Packages
LT1965 1.1A, Low Noise, Low Dropout
Linear Regulator
310mV Dropout Voltage, Low Noise: 40μVRMS, VIN: 1.8V to 20V, VOUT: 1.2V to 19.5V, Stable with
Ceramic Capacitors, TO-220, DD-Pak, MSOP and 3mm × 3mm DFN Packages
LT3022 1A, Low Voltage VLDO Linear
Regulator
145mV Dropout Voltage, VIN: 0.9V to 10V, VOUT: 0.2V to 9.5V, Stable with Low ESR, Ceramic
Output Capacitors, 16-Pin DFN (5mm × 3mm) and 16-Lead MSOP Packages
LT3070 5A, Low Noise, Programmable VOUT,
85mV Dropout Linear Regulator with
Digital Margining
85mV Dropout Voltage, Digitally Programmable VOUT: 0.8V to 1.8V, Digital Output Margining:
±1%, ±3% or ±5%, Low Output Noise: 25μVRMS; Directly Parallelable, Stable with Low ESR
Ceramic Output Capacitors (15μF Minimum), 28-Lead 4mm × 5mm QFN Package
LT3071 5A, Low Noise, Programmable VOUT,
85mV Dropout Linear Regulator with
Analog Margining
85mV Dropout Voltage, Digitally Programmable VOUT: 0.8V to 1.8V, Analog Margining: ±10%, Low
Output Noise: 25μVRMS; Directly Parallelable, IMON Output Current Monitor, Stable with Low ESR
Ceramic Output Capacitors (15μF Minimum), 28-Lead 4mm × 5mm QFN Package
LT3080/
LT3080-1
1.1A, Parallelable, Low Noise, Low
Dropout Linear Regulator
300mV Dropout Voltage (2-Supply Operation), Low Noise: 40μVRMS, VIN: 1.2V to 36V, VOUT: 0V
to 35.7V, Current-Based Reference with 1-Resistor VOUT Set; Directly Parallelable (No Op Amp
Required), Stable with Ceramic Capacitors; TO-220, DD-Pak, SOT-223, MSOP and 3mm × 3mm
DFN-8 Packages; -1 Version Has Integrated Internal Ballast Resistor
LT3081 1.5A, Single Resistor Rugged Linear
Regulator with Monitors
Extended Safe Operating Area, VIN: 1.2V to 36V, VOUT: 0V to 34.5V, Current-Based Reference,
Programmable Current Limit, Output Current and Temperature Monitors
LT3083 3A, Parallelable, Low Noise, Low
Dropout Linear Regulator
310mV Dropout Voltage (2-Supply Operation), Low Noise: 40μVRMS, VIN: 1.2V to 23V, VOUT:
0V to 22.6V, Current-Based Reference with 1-Resistor VOUT Set, Directly Parallelable (No Op
Amp Required), Stable with Ceramic Capacitors; TO-220, DD-Pak, TSSOP, 4mm × 4mm DFN-12
Packages
LT3085 500mA, Parallelable, Low Noise,
Low Dropout Linear Regulator
275mV Dropout (2-Supply Operation), Low Noise: 40μVRMS, VIN: 1.2V to 36V, VOUT: 0V to 35.7V,
Current-Based Reference with 1-Resistor VOUT Set, Directly Parallelable (No Op Amp Required),
Stable with Ceramic Capacitors; MS8E and 2mm × 3mm DFN-6 Packages
Paralleling Tw o Regulators for 5V, 4.2A with Cable Drop Compensation (CDC)
VIN
6.4V TO 15V
FOR RWIRE = 0.2Ω
10µF
10µF
RLINE1
CABLE
10µF
10µF
IN SHDN
IMON
ILIM
OUT
SET
GND
LT3086
MASTER
VOUT
VILIM(MASTER)
0.7V AT 4.2A
RSET
90.9k + 1.1k
1% VTEMP(SLAVE)
10mV/°C
25°C = 250mV VLOAD
5V AT
4.2A
VTEMP(MASTER)
10mV/°C
25°C = 250mV RCDC
1%
RMON
332Ω
1% 3086 TA13
IN
SHDN
IMON
ILIM
OUT
SET
TRACK
GND
LT3086
SLAVE
RMON
332Ω
1% RLINE2
TEMP TEMP
CDC
LOAD
RCDC =
R
MON
R
SET
X+1
( )
3000RWIRE
RWIRE =RLINE1 +RLINE2
WHERE X =NUMBER OF SLAVES

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