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LTC6990 Datasheet

Linear Technology/Analog Devices

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Datasheet

LTC6990
1
6990fc
For more information www.linear.com/LTC6990
TYPICAL APPLICATION
DESCRIPTION
TimerBlox: Voltage
Controlled Silicon Oscillator
The LTC
®
6990 is a precision silicon oscillator with a pro-
grammable frequency range of 488Hz to 2MHz. It can be
used as a fixed-frequency or voltage-controlled oscillator
(VCO). The LTC6990 is part of the TimerBlox
®
family of
versatile silicon timing devices.
A single resistor, RSET, programs the LTC6990’s internal
master oscillator frequency. The output frequency is deter-
mined by this master oscillator and an internal frequency
divider, NDIV, programmable to eight settings from 1 to 128.
fOUT =
1MHz
N
DIV
50k
R
SET
, NDIV = 1, 2, 4 …128
Optionally, a second resistor at the SET input provides
linear voltage control of the output frequency and can be
used for frequency modulation. A narrow or wide VCO
tuning range can be configured by the appropriate selec-
tion of the two resistors.
The LTC6990 includes an enable function that is synchro-
nized with the master oscillator to ensure clean, glitch-free
output pulses. The disabled output can be configured to
be high impedance or forced low.
For easy configuration of the LTC6990, download the
TimerBlox Designer tool at www.linear.com/timerblox.
Voltage Controlled Oscillator with 16:1 Frequency Range
L, LT, LTC and LTM , Linear Technology, TimerBlox and the Linear logo are registered
trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents, including 6342817,
6614313.
FEATURES
APPLICATIONS
n Fixed-Frequency or Voltage-Controlled Operation
Fixed: Single Resistor Programs Frequency
with <1.5% Max Error
VCO: Tw o Resistors Set VCO Center
Frequency and Tuning Range
n Frequency Range: 488Hz to 2MHz
n 2.25V to 5.5V Single Supply Operation
n 72µA Supply Current at 100kHz
n 500µs Start-Up Time
n VCO Bandwidth >300kHz at 1MHz
n CMOS Logic Output Sources/Sinks 20mA
n 50% Duty Cycle Square Wave Output
n Output Enable (Selectable Low or Hi-Z When Disabled)
n –55°C to 125°C Operating Temperature Range
n Available in Low Profile (1mm) SOT-23 (ThinSOT™)
and 2mm × 3mm DFN Package
n Low Cost Precision Programmable Oscillator
n Voltage-Controlled Oscillator
n High Vibration, High Acceleration Environments
n Replacement for Fixed Crystal and Ceramic Oscillators
n Portable and Battery-Powered Equipment
VCO Transfer Function
VCTRL (V)
0
fOUT (kHz)
1000
750
250
500
00.5
6990 TA01b
21 1.5
6990 TA01a
LTC6990
OE
GND
SET
OUT
V+
DIV
C1
0.1µF
RSET
100k
V+
V+
VCTRL
RVCO
100k
fOUT =1MHz VCTRL • 0.5 MHz
V
LTC6990
2
6990fc
For more information www.linear.com/LTC6990
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V+) to GND ........................................6V
Maximum Voltage on Any Pin
.............................(GND – 0.3V) ≤ VPIN ≤ (V+ + 0.3V)
Operating Temperature Range (Note 2)
LTC6990C ............................................ 40°C to 8C
LTC6990I .............................................40°C to 8C
LTC6990H .......................................... 40°C to 125°C
LTC6990MP ....................................... 5C to 125°C
(Note 1)
TOP VIEW
OUT
GND
OE
V+
DIV
SET
DCB PACKAGE
6-LEAD (2mm × 3mm) PLASTIC DFN
4
5
7
6
3
2
1
TJMAX = 150°C, θJA = 64°C/W, θJC = 10.6°C/W
EXPOSED PAD (PIN 7) CONNECTED TO GND,
PCB CONNECTION OPTIONAL
OE 1
GND 2
SET 3
6 OUT
5 V+
4 DIV
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
TJMAX = 150°C, θJA = 192°C/W, θJC = 51°C/W
PIN CONFIGURATION
ORDER INFORMATION
Specified Temperature Range (Note 3)
LTC6990C ................................................ C to 70°C
LTC6990I .............................................40°C to 8C
LTC6990H .......................................... 40°C to 125°C
LTC6990MP ....................................... 5C to 125°C
Junction Temperature ........................................... 150°C
Storage Temperature Range ..................6C to 150°C
Lead Temperature (Soldering, 10sec)....................30C
Lead Free Finish
TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6990CDCB#TRMPBF LTC6990CDCB#TRPBF LDWX 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C
LTC6990IDCB#TRMPBF LTC6990IDCB#TRPBF LDWX 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C
LTC6990HDCB#TRMPBF LTC6990HDCB#TRPBF LDWX 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C
LTC6990CS6#TRMPBF LTC6990CS6#TRPBF LTDWW 6-Lead Plastic TSOT-23 0°C to 70°C
LTC6990IS6#TRMPBF LTC6990IS6#TRPBF LTDWW 6-Lead Plastic TSOT-23 –40°C to 85°C
LTC6990HS6#TRMPBF LTC6990HS6#TRPBF LTDWW 6-Lead Plastic TSOT-23 –40°C to 125°C
LTC6990MPS6#TRMPBF LTC6990MPS6#TRPBF LTDWW 6-Lead Plastic TSOT-23 –55°C to 125°C
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LTC6990
3
6990fc
For more information www.linear.com/LTC6990
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fOUT Output Frequency Recommended Range: RSET = 50k to 800k
Extended Range: RSET = 25k to 800k 0.488
0.488 1000
2000 kHz
kHz
fOUT Frequency Accuracy (Note 4) Recommended Range
RSET = 50k to 800k
l
±0.8 ±1.5
±2.2 %
%
Extended Range
RSET = 25k to 800k
l
±2.4
±3.2 %
%
fOUT/TFrequency Drift Over Temperature l±0.005 %/°C
fOUT/V+Frequency Drift Over Supply V+ = 4.5V to 5.5V
V+ = 2.25V to 4.5V
l
l
0.23
0.06 0.55
0.16 %/V
%/V
Long-Term Frequency Stability (Note 11) 90 ppm/√kHr
Period Jitter (Note 10) NDIV = 1 0.38 %P-P
NDIV = 2 0.22
0.027 %P-P
%RMS
NDIV = 128 0.022
0.004 %P-P
%RMS
Duty Cycle NDIV = 1, RSET = 25k to 800k
NDIV > 1, RSET = 25k to 800k
l
l
47
48 50
50 53
52 %
%
BW Frequency Modulation Bandwidth 0.4•fOUT kHz
tSFrequency Change Settling Time
(Note 9) tMASTER = tOUT/NDIV 6•tMASTER µs
Analog Inputs
VSET Voltage at SET Pin l0.97 1.00 1.03 V
VSET/TVSET Drift Over Temperature l±75 µV/°C
VSET/V+VSET Drift Over Supply –150 µV/V
VSET/ISET VSET Droop with ISET –7 Ω
RSET Frequency-Setting Resistor Recommended Range
Extended Range
l
l
50
25 800
800
VDIV DIV Pin Voltage l0 V+V
VDIV/V+DIV Pin Valid Code Range (Note 5) Deviation from Ideal VDIV/V+ = (DIVCODE + 0.5)/16 l±1.5 %
DIV Pin Input Current l±10 nA
Power Supply
V+Operating Supply Voltage Range l2.25 5.5 V
Power-On Reset Voltage RSET = 25k to 800k l1.95 V
ISSupply Current RL = ∞, NDIV = 1, RSET = 50k V+ = 5.5V
V+ = 2.25V
l
l
235
145 283
183 µA
µA
RL = ∞, NDIV = 1 RSET = 800k V+ = 5.5V
V+ = 2.25V
l
l
71
59 105
92 µA
µA
RL = ∞, NDIV = 128, RSET = 50k V+ = 5.5V
V+ = 2.25V
l
l
137
106 180
145 µA
µA
RL = ∞, NDIV = 128, RSET = 800k V+ = 5.5V
V+ = 2.25V
l
l
66
56 100
90 µA
µA
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, OE = V+, DIVCODE = 0 to 15
(NDIV = 1 to 128), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
LTC6990
4
6990fc
For more information www.linear.com/LTC6990
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, OE = V+, DIVCODE = 0 to 15
(NDIV = 1 to 128), RSET = 25k to 800k, RLOAD = ∞, CLOAD = 5pF unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6990C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 3: The LTC6990C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6990C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but it is not tested or
QA sampled at these temperatures. The LTC6990I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6990H is guaranteed
to meet specified performance from –40°C to 125°C. The LTC6990MP is
guaranteed to meet specified performance from –55°C to 125°C.
Note 4: Frequency accuracy is defined as the deviation from the fOUT
equation, assuming RSET is used to program the frequency.
Note 5: See Operation section, Table 1 and Figure 2 for a full explanation
of how the DIV pin voltage selects the value of DIVCODE.
Note 6: The OE pin has hysteresis to accommodate slow rising or falling
signals. The threshold voltages are proportional to V+. Typical values can
be estimated at any supply voltage using VOE(RISING) ≈ 0.55 • V+ + 185mV
and VOE(FALLING) ≈ 0.48 • V+ – 155mV.
Note 7: To conform to the Logic IC Standard, current out of a pin is
arbitrarily given a negative value.
Note 8: Output rise and fall times are measured between the 10% and the
90% power supply levels with 5pF output load. These specifications are
based on characterization.
Note 9: Settling time is the amount of time required for the output to settle
within ±1% of the final frequency after a 0.5x or 2x change in ISET.
Note 10: Jitter is the ratio of the deviation of the period to the mean of the
period. This specification is based on characterization and is not 100% tested.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital I/O
OE Pin Input Capacitance 2.5 pF
OE Pin Input Current OE = 0V to V+l±10 nA
VIH High Level OE Pin Input Voltage (Note 6) l0.7•V+V
VIL Low Level OE Pin Input Voltage (Note 6) l0.3•V+V
OUT Pin Hi-Z Leakage OE = 0V, DIVCODE ≥ 8, OUT = 0V to V+±10 µA
IOUT(MAX) Maximum Output Current ±20 mA
VOH High Level Output Voltage
(Note 7) V+ = 5.5V IOH = –1mA
IOH = –16mA
l
l
5.45
4.84 5.48
5.15 V
V
V+ = 3.3V IOH = –1mA
IOH = –10mA
l
l
3.24
2.75 3.27
2.99 V
V
V+ = 2.25V IOH = –1mA
IOH = –8mA
l
l
2.17
1.58 2.21
1.88 V
V
VOL Low Level Output Voltage
(Note 7) V+ = 5.5V IOL = 1mA
IOL = 16mA
l
l
0.02
0.26 0.04
0.54 V
V
V+ = 3.3V IOL = 1mA
IOL = 10mA
l
l
0.03
0.22 0.05
0.46 V
V
V+ = 2.25V IOL = 1mA
IOL = 8mA
l
l
0.03
0.26 0.07
0.54 V
V
tPD Output Disable Propagation Delay V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
17
26
44
ns
ns
ns
tENABLE Output Enable Time NDIV ≤ 2, tOUT = 1/fOUT
NDIV ≥ 4, tMASTER = tOUT/NDIV
tPD to tOUT
tPD to 2tMASTER
µs
µs
trOutput Rise Time (Note 8) V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
1.1
1.7
2.7
ns
ns
ns
tfOutput Fall Time (Note 8) V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
1.0
1.6
2.4
ns
ns
ns
LTC6990
5
6990fc
For more information www.linear.com/LTC6990
TYPICAL PERFORMANCE CHARACTERISTICS
VSET vs ISET VSET vs Supply Voltage VSET vs Temperature
Frequency Error vs RSET
Frequency Error
vs Supply Voltage Frequency Error vs Temperature
V+ = 3.3V, unless otherwise noted.
RSET (kΩ)
FREQUENCY ERROR (%)
6990 G01
4
3
2
1
–1
–2
–3
0
–410 100 1000
TA = 25°C
GUARANTEED MAX
OVER TEMPERATURE
GUARANTEED MIN
OVER TEMPERATURE
TYPICAL MAX
90% OF UNITS
TYPICAL MIN
SUPPLY VOLTAGE (V)
FREQUENCY ERROR (%)
6990 G02
0.5
0.4
0.3
0.1
0.2
–0.1
–0.2
–0.3
0
–0.5
–0.4
2 43 5 6
TA = 25°C
RSET = 800k
RSET = 200k
RSET = 50k
ISET (µA)
V
SET
(V)
6990 G04
1.003
1.002
1.001
1.000 0 2010 30 40
V+ = 3.3V
TA = 25°C
SUPPLY VOLTAGE (V)
V
SET
(V)
6990 G05
1.003
1.002
1.001
1.000 2 43 5 6
RSET = 200k
TA = 25°C
TEMPERATURE (°C)
SET
6990 G06
1.005
1.000
1.010
1.015
0.995
0.990
0.985
0.980
–50 75500 25–25 100 125
RSET = 200k
3 TYPICAL PARTS
TEMPERATURE (°C)
ERROR (%)
6990 G03
1.5
0.5
1.0
0.0
–0.5
–1.0
–1.5
–50 –25 25 500 10075 125
V+ = 3.3V
DIVCODE = 4
RSET = 50k
RSET = 267k
RSET = 800k
ELECTRICAL CHARACTERISTICS
Note 11: Long-term drift of silicon oscillators is primarily due to the
movement of ions and impurities within the silicon and is tested at 30°C
under otherwise nominal operating conditions. Long-term drift is specified
as ppm/√kHr due to the typically nonlinear nature of the drift. To calculate
drift for a set time period, translate that time into thousands of hours, take
the square root and multiply by the typical drift number. For instance, a
year is 8.77kHr and would yield a drift of 266ppm at 90ppm/√kHr. Drift
without power applied to the device may be approximated as 1/10th of the
drift with power, or 9ppm/√kHr for a 90ppm/√kHr device.
LTC6990
6
6990fc
For more information www.linear.com/LTC6990
TYPICAL PERFORMANCE CHARACTERISTICS
Peak-to-Peak Jitter vs Frequency
OE Threshold Voltage
vs Supply Voltage
Supply Current vs Frequency, 5V Supply Current vs Frequency, 2.5V Supply Current vs OE Pin Voltage
V+ = 3V, unless otherwise noted.
Output Resistance
vs Supply Voltage
FREQUENCY (kHz)
POWER SUPPLY CURRNET (µA)
6990 G10
400
300
350
200
250
150
100
50
00.1 1 1000 1000010010
V+ = 5V
TA = 25°C
÷128 ÷1
÷2
RECOMMENDED RANGE
EXTENDED RANGE
FREQUENCY (kHz)
POWER SUPPLY CURRNET (µA)
6990 G11
400
300
350
200
250
150
100
50
00.1 1 1000 1000010010
V+ = 2.5V
TA = 25°C
RECOMMENDED RANGE
EXTENDED RANGE
÷128
÷1
÷2
VOE/V+ (%)
POWER SUPPLY CURRENT (µA)
6990 G12
200
100
125
75
150
175
50 0 604020 80 100
5V, OE RISING
TA = 25°C
RSET = 800k
DIVCODE = 7
5V, OE FALLING
3.3V,
OE RISING
3.3V, OE FALLING
SUPPLY VOLTAGE (V)
OE PIN VOLTAGE (V)
6990 G14
3.5
1.0
2.0
3.0
0.5
1.5
2.5
02 43 5 6
TA = 25°C
POSITIVE-GOING
NEGATIVE-GOING
FREQUENCY (kHz)
JITTER (%
P-P
)
6990 G13
0.50
0.25
0.30
0.40
0.20
0.10
0.05
0.15
0.35
0.45
00.1 10 1001 1000
TA = 25°C
V+ = 5V
PEAK-TO-PEAK PERIOD
DEVIATION MEASURED
OVER 30sec INTERVALS
÷1
÷2
÷4
÷128
Typical VSET Distribution Supply Current vs Supply Voltage Supply Current vs Temperature
VSET (V)
NUMBER OF UNITS
6990 G07
300
150
100
200
250
50
00.986 1.0020.994 1.010 1.018
TA = 25°C
2 LOTS
DFN AND SOT-23
1416 UNITS
SUPPLY VOLTAGE (V)
POWER SUPPLY CURRENT (µA)
6990 G05
250
150
100
50
200
02 43 5 6
TA = 25°C
RSET = 800k, ÷1
RSET = 800k, ÷128
RSET = 50k, ÷1
RSET = 50k, ÷2
RSET = 50k, ÷128
TEMPERATURE (°C)
POWER SUPPLY CURRENT (µA)
6990 G09
250
100
50
150
200
0
–50 75500 25–25 100 125
5.5V, RSET = 800k, ÷1
2.25V, RSET = 800k, ÷128
5.5V, RSET = 50k, ÷1
2.25V, RSET = 50k, ÷1
5.5V, RSET = 50k, ÷128
SUPPLY VOLTAGE (V)
OUTPUT RESISTANCE (Ω)
6990 G15
50
25
20
35
45
5
10
15
30
40
02 43 5 6
TA = 25°C
OUTPUT SOURCING CURRENT
OUTPUT SINKING CURRENT
LTC6990
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6990fc
For more information www.linear.com/LTC6990
Rise and Fall Time
vs Supply Voltage
Output Disable Propagation Delay
(tPD) vs Supply Voltage
TYPICAL PERFORMANCE CHARACTERISTICS
Frequency Modulation Frequency Modulation
Typical ISET Current Limit vs V+Typical Output Waveform
SUPPLY VOLTAGE (V)
RISE/FALL TIME (ns)
6990 G16
3.0
1.5
2.5
1.0
0.5
2.0
02 43 5 6
TA = 25°C
CLOAD = 5pF
tRISE
tFALL
SUPPLY VOLTAGE (V)
PROPAGATION DELAY (ns)
6990 G17
50
20
40
10
30
25
45
15
5
35
02 43 5 6
TA = 25°C
CLOAD = 5pF
SUPPLY VOLTAGE (V)
I
SET
(µA)
6990 G18
1000
400
800
200
600
02 43 5 6
TA = 25°C
SET PIN SHORTED TO GND
20µs/DIV 6990 G19
OUT
2V/DIV
OE
2V/DIV
V+ = 3.3V
DIVCODE = 2
RSET = 200k
20µs/DIV 6990 G20
OUT
2V/DIV
VCTRL
2V/DIV
fOUT
50kHz/DIV
V+ = 3.3V, DIVCODE = 0
RSET = 200k, RVCO = 464k
fOUT = 175kHz to 350kHz
20µs/DIV 6990 G21
OUT
2V/DIV
VCTRL
2V/DIV
fOUT
50kHz/DIV
V+ = 3.3V, DIVCODE = 0
RSET = 200k, RVCO = 464k
fOUT = 175kHz to 350kHz
V+ = 3V, unless otherwise noted.
Typical Frequency Error vs
Time (Long-Term Drift)
TIME (h)
DELTA FREQUENCY (ppm)
6990 G15a
50
0
150
–150
–100
–50
100
200
–200 0 1200400 800 1600 2000 2400 2800
65 UNITS
SOT-23 AND DFN PARTS
TA = 30°C
LTC6990
8
6990fc
For more information www.linear.com/LTC6990
PIN FUNCTIONS
V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This
supply must be kept free from noise and ripple. It should
be bypassed directly to the GND pin with a 0.1µF capacitor.
DIV (Pin 2/Pin 4): Programmable Divider and Hi-Z Mode
Input. A V+ referenced A/D converter monitors the DIV
pin voltage (VDIV) to determine a 4-bit result (DIVCODE).
VDIV may be generated by a resistor divider between V+
and GND. Use 1% resistors to ensure an accurate result.
The DIV pin and resistors should be shielded from the
OUT pin or any other traces that have fast edges. Limit
the capacitance on the DIV pin to less than 100pF so that
VDIV settles quickly. The MSB of DIVCODE (Hi-Z) deter-
mines the behavior of the output when OE is driven low.
If Hi-Z = 0 the output is pulled low when disabled. If Hi-Z
= 1 the output is placed in a high impedance condition
when disabled.
SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage
on the SET pin (VSET) is regulated to 1V above GND. The
amount of current sourced from the SET pin (ISET) pro-
grams the master oscillator frequency. The ISET current
range is 1.25µA to 40µA. The output oscillation will stop
if ISET drops below approximately 500nA. A resistor con-
nected between SET and GND is the most accurate way to
set the frequency. For best performance, use a precision
metal or thin film resistor of 0.5% or better tolerance and
50ppm/°C or better temperature coefficient. For lower ac-
curacy applications an inexpensive 1% thick film resistor
may be used.
Limit the capacitance on the SET pin to less than 10pF
to minimize jitter and ensure stability. Capacitance less
than 100pF maintains the stability of the feedback circuit
regulating the VSET voltage.
(DCB/S6)
OE (Pin 4/Pin 1): Output Enable. Drive high to enable the
output driver (Pin 6). Driving OE low disables the output
asynchronously, so that the output is immediately forced
low (Hi-Z = 0) or floated (Hi-Z = 1). When enabled, the
output may temporarily remain low to synchronize with
the internal oscillator in order to eliminate pulse slivers.
GND (Pin 5/Pin 2): Ground. Tie to a low inductance ground
plane for best performance.
OUT (Pin 6/Pin 6): Oscillator Output. The OUT pin swings
from GND to V+ with an output resistance of approximately
30Ω. When driving an LED or other low-impedance load
a series output resistor should be used to limit source/
sink current to 20mA.
6990 PF
LTC6990
OE
GND
SET
OUT
V+
DIV
C1
0.1µF
RSET R2
R1
V+
V+
LTC6990
9
6990fc
For more information www.linear.com/LTC6990
BLOCK DIAGRAM
6990 BD
PROGRAMMABLE DIVIDER
÷1, 2, 4, 8, 16, 32, 64, 128
MASTER OSCILLATOR
Hi-Z WHEN
DISABLED
Hi-Z OUTPUT
UNTIL SETTLED
POR
DIGITAL
FILTER
4-BIT A/D
CONVERTER
Hi-Z BIT
R1
R2
DIV
V+OE
OUT
5
4
1
6
HALT OSCILLATOR
IF ISET < 500nA
MCLK
+
ISET
VSET = 1V
+
1V
322
GND SET
RSET
tOUT
tMASTER =1µs
50kVSET
ISET
(S6 Package Pin Numbers Shown)
LTC6990
10
6990fc
For more information www.linear.com/LTC6990
OPERATION
The LTC6990 is built around a master oscillator with a
1MHz maximum frequency. The oscillator is controlled
by the SET pin current (ISET) and voltage (VSET), with a
1MHz • 50k conversion factor that is accurate to ±0.8%
under typical conditions.
fMASTER =
1
tMASTER
=1MHz • 50k
I
SET
VSET
A feedback loop maintains VSET at 1V ±30mV, leaving ISET
as the primary means of controlling the output frequency.
The simplest way to generate ISET is to connect a resistor
(RSET) between SET and GND, such that ISET = VSET/RSET.
The master oscillator equation reduces to:
fMASTER =
1
tMASTER
=
1MHz 50k
RSET
From this equation it is clear that VSET drift will not affect
the output frequency when using a single program resis-
tor (RSET). Error sources are limited to RSET tolerance and
the inherent frequency accuracy ∆fOUT of the LTC6990.
RSET values between 50k and 800k (equivalent to ISET
between 1.25µA and 20µA) produce the best results,
although RSET may be reduced to 25k (ISET = 40µA) with
reduced accuracy.
The LTC6990 includes a programmable frequency divider
which can further divide the frequency by 1, 2, 4, 8, 16,
32, 64 or 128 before driving the OUT pin. The divider ratio
NDIV is set by a resistor divider attached to the DIV pin.
fOUT =1
t
OUT
=1MHz • 50k
N
DIV
I
SET
V
SET
With RSET in place of VSET/ISET the equation reduces to:
fOUT =
1
t
OUT
=
1MHz • 50k
N
DIV
R
SET
DIVCODE
The DIV pin connects to an internal, V+ referenced 4-bit
A/D converter that monitors the DIV pin voltage (VDIV) to
determine the DIVCODE value. DIVCODE programs two
settings on the LTC6990:
1. DIVCODE determines the output frequency divider
setting, NDIV.
2. DIVCODE determines the state of the output when
disabled, via the Hi-Z bit.
VDIV may be generated by a resistor divider between V+
and GND as shown in Figure 1.
Figure 1. Simple Technique for Setting DIVCODE
6990 F01
LTC6990
V+
DIV
GND
R1
R2
2.25V TO 5.5V
LTC6990
11
6990fc
For more information www.linear.com/LTC6990
Table 1. DIVCODE Programming
DIVCODE Hi-Z NDIV Recommended fOUT R1 (k) R2 (k) VDIV/V+
0 0 1 62.5kHz to 1MHz Open Short ≤ 0.03125 ±0.015
1 0 2 31.25kHz to 500kHz 976 102 0.09375 ±0.015
2 0 4 15.63kHz to 250kHz 976 182 0.15625 ±0.015
3 0 8 7.813kHz to 125kHz 1000 280 0.21875 ±0.015
4 0 16 3.906kHz to 62.5kHz 1000 392 0.28125 ±0.015
5 0 32 1.953kHz to 31.25kHz 1000 523 0.34375 ±0.015
6 0 64 976.6Hz to 15.63kHz 1000 681 0.40625 ±0.015
7 0 128 488.3Hz to 7.813kHz 1000 887 0.46875 ±0.015
8 1 128 488.3Hz to 7.813kHz 887 1000 0.53125 ±0.015
9 1 64 976.6Hz to 15.63kHz 681 1000 0.59375 ±0.015
10 1 32 1.953kHz to 31.25kHz 523 1000 0.65625 ±0.015
11 1 16 3.906kHz to 62.5kHz 392 1000 0.71875 ±0.015
12 1 8 7.813kHz to 125kHz 280 1000 0.78125 ±0.015
13 1 4 15.63kHz to 250kHz 182 976 0.84375 ±0.015
14 1 2 31.25kHz to 500kHz 102 976 0.90625 ±0.015
15 1 1 62.5kHz to 1MHz Short Open ≥ 0.96875 ±0.015
OPERATION
Table 1 offers recommended 1% resistor values that ac-
curately produce the correct voltage division as well as the
corresponding NDIV and Hi-Z values for the recommended
resistor pairs. Other values may be used as long as:
1. The VDIV/V+ ratio is accurate to ±1.5% (including resis-
tor tolerances and temperature effects)
2. The driving impedance (R1||R2) does not exceed 500kΩ.
If the voltage is generated by other means (i.e. the output
of a DAC) it must track the V+ supply voltage. The last
column in Table 1 shows the ideal ratio of VDIV to the
supply voltage, which can also be calculated as:
V
DIV
V
+=DIVCODE
+
0.5
16 ±1.5%
For example, if the supply is 3.3V and the desired DIVCODE
is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV.
Figure 2 illustrates the information in Table 1, showing
that NDIV is symmetric around the DIVCODE midpoint.
On start-up, the DIV pin A/D converter must determine
the correct DIVCODE before the output is enabled. If VDIV
0.5V+
fOUT (kHz)
6990 F02
1000
100
10
1
0.1
INCREASING VDIV
V+
0V
RECOMMENDED RANGE
EXTENDED RANGE
Hi-Z BIT = 0 Hi-Z BIT = 1
0 15
1
3
2
5
4
7
69
8
11
10
13
12
14
Figure 2. Frequency Range and Hi-Z Bit vs DIVCODE
LTC6990
12
6990fc
For more information www.linear.com/LTC6990
OPERATION
is not stable, it will increase the start-up time as the con-
verter waits for a stable result. Therefore, capacitance on
the DIV pin should be minimized so it will settle quickly.
Less than 100pF will not affect performance.
Output Enable
The OE pin controls the state of the LTC6990’s output as
seen on the OUT pin. Pulling the OE pin high enables the
oscillator output. Pulling it low disables the output. When
the output is disabled, it is either held low or placed in
a high impedance state as dictated by the Hi-Z bit value
(determined by the DIVCODE as described earlier). Table 2
summarizes the output control states.
Table 2. Output States
OE Pin Hi-Z OUT
1 X Enabled, Output is Active
0 1 Disabled, Output is Hi-Z
0 0 Disabled, Output is Held Low
Figure 3 illustrates the timing for the OE function when
Hi-Z = 0. When OE is low, the output is disabled and OUT
is held low. Bringing OE high enables the output after a
delay, tENABLE, which synchronizes the enable to eliminate
sliver pulses and guarantee the correct width for the first
pulse. If NDIV = 1 or 2 this delay will be no longer than
the output period, tOUT. If NDIV > 2 the delay is limited to
twice the internal master oscillator period (or 2 • tMASTER).
Forcing OE low will bring OUT low after a propagation
delay, tPD. If the output is high when OE falls, the output
pulse will be truncated.
As shown in Figure 4, setting Hi-Z = 1 places the output in
a high-impedance state when OE = 0. This feature allows
forwired-OR” connections of multiple devices. Driving OE
high enables the output. The output will usually be forced
low during this time, although it is possible for OUT to
transition directly from high-impedance to a high output,
depending on the timing of the OE transition relative to
the internal oscillator. Once high, the first output pulse
will have the correct width (unless truncated by bringing
OE low again).
Figure 3. OE Timing Diagram (Hi-Z = 0)
6990 F03
OE
OUT
tPD
tPD
tENABLE
tENABLE tOUT
Figure 4. OE Timing Diagram (Hi-Z = 1)
6990 F04
OE
OUT
tPD
tPD tPD
tPD
tENABLE
tENABLE tOUT
Hi-Z
LTC6990
13
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OPERATION
Changing DIVCODE After Start-Up
Following start-up, the A/D converter will continue
monitoring VDIV for changes. Changes to DIVCODE will
be recognized slowly, as the LTC6990 places a priority on
eliminating anywandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
t
DIVCODE
=16 •(DIVCODE +6) • t
MASTER
A change in DIVCODE will not be recognized until it is
stable, and will not pass through intermediate codes. A
digital filter is used to guarantee the DIVCODE has settled
to a new value before making changes to the output. Then
the output will make a clean (glitchless) transition to the
new divider setting.
Start-Up Time
When power is first applied to the LTC6990 the power-on
reset (POR) circuit will initiate the start-up time, tSTART.
The OUT pin is floated (high-impedance) during this time.
The typical value for tSTART ranges from 0.5ms to 8ms
depending on the master oscillator frequency (indepen-
dent of NDIV):
t
START(TYP)
=500 t
MASTER
The start-up time may be longer if the supply or DIV
pin voltages are not stable. For this reason, it is recom-
mended to minimize the capacitance on the DIV pin so it
will properly track V+.
Figure 5. DIVCODE Change from 5 to 2 Figure 6. Typical Start-Up
100µs/DIV 6990 F05
DIV
1V/DIV
OUT
1V/DIV
V+ = 3.3V
RSET = 200k
576µs
100µs/DIV 6990 F06
V+
1V/DIV
OUT
1V/DIV
V+ = 2.5V
DIVCODE = 4
RSET = 50k
OUTPUT CONNECTED
TO 1.25V THROUGH 25k
TO SHOW Hi-Z
470µs
LTC6990
14
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APPLICATIONS INFORMATION
Figure 7. Start-Up Timing Diagram (OE = 1, NDIV = 1 or 2, Hi-Z = 0 or 1)
Figure 8. Start-Up Timing Diagram (OE = 1, NDIV ≥ 4, Hi-Z = 0 or 1)
Figure 9. Start-Up Timing Diagram (OE = 0, NDIV = Any, Hi-Z = 0)
Figure 10. Start-Up Timing Diagram (OE = 0, NDIV = Any, Hi-Z = 1)
6990 F07
OE
OUT
1/2 tOUT tOUT
tSTART
Hi-Z
6990 F08
OE
OUT
tOUT
tMASTER
tSTART
Hi-Z
6990 F09
OE
OUT
tOUT
tENABLE
tSTART
Hi-Z
6990 F10
OE
OUT
tOUT
tENABLE
tSTART
Hi-Z
tPD
REMAINS Hi-Z
UNTIL OE = 1
LTC6990
15
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APPLICATIONS INFORMATION
Start-Up Behavior
When first powered up, the output is high impedance. If
the output is enabled (OE = 1) at the end of the start-up
time, the output will go low for one tMASTER cycle (or half
a tOUT cycle if NDIV < 4) before the first rising edge. If the
output is disabled (OE = 0) at the end of the start-up time,
the output will drop to a low output if the Hi-Z bit = 0, or
simply remain floating if Hi-Z = 1.
Basic Fixed Frequency Operation
The simplest and most accurate method to program the
LTC6990 for fixed frequency operation is to use a single
resistor, RSET, between the SET and GND pins. The design
procedure is a simple two step process. First select the NDIV
value and then calculate the value for the RSET resistor.
Alternatively, Linear Technology offers the easy to use
TimerBlox Designer tool to quickly design any LTC6990
based circuit. Download the free TimerBlox Designer
software at www.linear.com/timerblox.
Step 1: Selecting the NDIV Frequency Divider Value
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the Hi-Z bit and the
NDIV value. For a given output frequency, NDIV should be
selected to be within the following range.
62.5kHz
f
OUT
NDIV
1MHz
f
OUT
(1a)
To minimize supply current, choose the lowest NDIV value
(generally recommended). For faster start-up or decreased
jitter, choose a higher NDIV setting. Alternatively, use Table 1
as a guide to select the best NDIV value for the given ap-
plication. After choosing the value for NDIV, use Table 1 to
select the proper resistor divider or VDIV/V+ ratio to apply
to the DIV pin.
Step 2: Calculate and Select RSET
The final step is to calculate the correct value for RSET
using the following equation.
RSET =
1MHz • 50k
NDIV • fOUT
(1b)
Select the standard resistor value closest to the calculated
value.
Example: Design a 20kHz Oscillator with Minimum
Power Consumption
Step 1: Selecting the NDIV Frequency Divider Value
First, choose an NDIV value that meets the requirements
of Equation (1a).
3.125 ≤ NDIV ≤ 50
Potential settings for NDIV include 4, 8, 16, and 32. NDIV = 4
is the best choice, as it minimizes supply current by using
a large RSET resistor. Using Table 1, choose the R1 and R2
values to program DIVCODE to either 2 or 13, depending
on the desired behavior when the output is disabled.
Step 2: Select RSET
Calculate the correct value for RSET using Equation (1b).
RSET =
1MHz • 50k
4 20kHz
=625k
Since 625k is not available as a standard 1% resistor,
substitute 619k if a 0.97% frequency shift is acceptable.
Otherwise, select a parallel or series pair of resistors such
as 309k and 316k to attain a more precise resistance.
LTC6990
16
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APPLICATIONS INFORMATION
Frequency Modulated Operation (Voltage-Controlled
Oscillator)
Operating the LTC6990 as a voltage-controlled oscillator in
its simplest form is achieved with one additional resistor.
As shown in Figure 11, voltage VCTRL sources/sinks a cur-
rent through RVCO to vary the ISET current, which in turn
modulates the output frequency as described in Equation (2).
fOUT =1MHz • 50k
NDIV RVCO
• 1+RVCO
RSET
VCTRL
VSET
(2)
fOUT, choose a value for NDIV that meets the following
conditions
62.5kHz
fOUT(MIN)
NDIV
1MHz
fOUT(MAX)
(3a)
The 16:1 frequency range of the master oscillator and
the 2:1 divider step-size provides several overlapping fre-
quency spans to guarantee that any 8:1 modulation range
can be covered by a single NDIV setting. RVCO allows the
gain to be tailored to the application, mapping the VCTRL
voltage range to the modulation range.
Step 2: Calculate KVCO and f(0V)
KVCO and f(0V) define the VCO’s transfer function and sim-
plify the calculation of the the RVCO and RSET resistors.
Calculate these parameters using the following equations.
KVCO =
f
OUT(MAX)
f
OUT(MIN)
VCTRL(MAX) VCTRL(MIN)
(3b)
f(0V) = fOUT(MAX) + KVCO • VCTRL(MIN) (3c)
KVCO and f(0V) are not device settings or resistor values
themselves. However, beyond their utility for the resistor
calculations, these parameters provide a useful and intuitive
way to look at the VCO application. The f(0V) parameter is
the output frequency when VCTRL is at 0V. Viewed another
way, it is the fixed output frequency when the RVCO and
RSET resistors are in parallel. KVCO is actually the frequency
gain of the circuit.
With KVCO and f(0V) determined, the RVCO and RSET values
can now be calculated.
Step 3: Calculate and Select RVCO
The next step is to calculate the correct value for RVCO
using the following equation.
RVCO =
1MHz 50k
NDIV • VSET KVCO
(3d)
Select the standard resistor value closest to the calculated
value.
Figure 11. Voltage Controlled Oscillator
6990 F08
LTC6990
OE
GND
SET
OUT
V+
DIV
C1
0.1µF R1
R2
RSET
V+
V
+
RVCO
VCTRL
Equation (2) can be re-written as shown below, where
f(0V) is the output frequency when VCTRL = 0V, and KVCO
is the frequency gain. Note that the gain is negative (the
output frequency decreases as VCTRL increases).
f
OUT
= f
(0V)
– K
VCO
V
CTRL
f(0V) = 1MHz • 50k
NDIV RSET RVCO
(
)
KVCO = 1MHz • 50k
NDIV • VSET RVCO
The design procedure for a VCO is a simple four step
process. First select the NDIV value. Then calculate the
intermediate values KVCO and f(0V). Next, calculate and
select the RVCO resistor. Finally calculate and select the
RSET resistor.
Step 1: Select the NDIV Frequency Divider Value
For best accuracy, the master oscillator frequency should
fall between 62.5kHz and 1MHz. Since fMASTER = NDIV
LTC6990
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For more information www.linear.com/LTC6990
Figure 12. VCO Transfer Function
VCTRL (V)
1
fOUT (kHz)
100
80
40
20
60
02
6990 F12
43
APPLICATIONS INFORMATION
Step 4: Calculate and Select RSET
The final step is to calculate the correct value for RSET
using the following equation:
RSET =
1MHz 50k
NDIV • f(0V) VSET KVCO
(
)
(3e)
Select the standard resistor value closest to the calculated
value.
Some applications require combinations of fOUT(MIN),
fOUT(MAX), VCTRL(MIN) and VCTRL(MAX) that are not achiev-
able. These applications result in unrealistic or unrealiz-
able (e.g. negative value) resistors. These applications
will require preconditioning of the VCTRL signal via range
scaling and/or level shifting to place the VCTRL into a range
that yields realistic resistor values.
Frequency Error in VCO Applications Due to VSET Error
As stated earlier, f(0V) represents the frequency for VCTRL
= 0V, which is the same value as would be generated by
a single resistor between SET and GND with a value of
RSET || RVCO. Therefore, f(0V) is not affected by error or
drift in VSET (i.e. ∆VSET adds no frequency error when
VCTRL = 0V).
The accuracy of KVCO does depend on VSET because the
output frequency is controlled by the ratio of VCTRL to
VSET. The frequency error (in Hertz) due toVSET is ap-
proximated by:
fOUT KVCO • VCTRL
V
SET
V
SET
As the equation indicates, the potential for error in output
frequency due to VSET error increases with KVCO and is
at its largest when VCTRL is at its maximum. Recall that
when VCTRL is at its maximum, the output frequency is
at its minimum. With the maximum absolute frequency
error (in Hertz) occurring at the lowest output frequency,
the relative frequency error (in percent) can be significant.
VSET is nominally 1.0V with a maximum error of ±30mV
for at most a ±3% error term. However, this ±3% po-
tential error term is multiplied by both VCTRL and KVCO.
Wide frequency range applications (high KVCO) can have
frequency errors greater than ±50% at the highest VCTRL
voltage (lowest fOUT). For this reason the simple, two
resistor VCO circuit must be used with caution for ap-
plications where the frequency range is greater than 4:1.
Restricting the range to 4:1 typically keeps the frequency
error due to VSET variation below 10%.
For wide frequency range applications, the non-inverting
VCO circuit shown in Figure 13 is preferred because the
maximum frequency error occurs when the frequency
is highest, keeping the relative error (in percent) much
smaller.
Example: Design a VCO with the Following Parameters
fOUT(MAX) = 100kHz at VCTRL(MIN) = 1V
fOUT(MIN) = 10kHz at VCTRL(MAX) = 4V
Step 1: Select the NDIV Value
First, choose an NDIV that meets the requirements of
Equation (3a).
6.25 ≤ NDIV ≤ 10
The application’s desired frequency range is 10:1, which
isn’t always possible. However, in this case NDIV = 8 meets
both requirements of Equation (3).
LTC6990
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APPLICATIONS INFORMATION
Step 2: Calculate KVCO and f(0V)
Next, calculate the intermediate values KVCO and f(0V) using
Equations (3b) and (3c).
KVCO =
100kHz 10kHz
4V 1V =30kHz/V
f(0V) =100kHz +30kHz/V • 1V =130kHz
Step 3: Calculate and Select RVCO
The next step is to use Equation (3d) to calculate the cor-
rect value for RVCO.
RVCO =
1MHz 50k
8 1V 30kHz/V
=208.333k
Select RVCO = 210k.
Step 4: Calculate and Select RSET
The final step is to calculate the correct value for RSET
using Equation (3e).
RSET =
1MHz 50k
8 • 130kHz 1V • 30kHz/V
(
)
=62.5k
Select RSET = 61.9k
In this design example, with its wide 10:1 frequency
range, the potential output frequency error due to VSET
error alone ranges from less than ±1% when VCTRL is at
its minimum up to ±36% when VCTRL is at its maximum.
This error must be accounted for in the system design.
Depending on the application’s requirements, the non-
inverting VCO circuit in Figure 13 may be preferred for
this wide of a frequency variation as its maximum inac-
curacy due to VSET error is only ±9% and can be reduced
to only ±3% with a small change to the voltage tuning
range specification.
Reducing VSET Error Effects in VCO Applications
Figure 13 shows a VCO that reduces the effect ofVSET
by adding an op-amp to make VCTRL dependent on VSET.
This circuit also has a positive transfer function (the out-
put frequency increases as VIN increases). Furthermore,
for positive VIN voltages, this circuit places the greatest
absolute frequency error at the highest output frequency.
Compared to the simple VCO circuit of Figure 11, the
absolute frequency error is unchanged. However, with
the maximum absolute frequency error (in Hertz) now
occurring at the highest output frequency, the relative
frequency error (in percent) is greatly improved.
Figure 13. VCO with Reduced VSET Sensitivity
6990 F13
LTC6990
OE
GND
SET
OUT
V+
DIV
C1
0.1µF R1
1M
R2
280k
DIVCODE = 3
(NDIV = 8, Hi-Z = 0)
RSET
249k
3V
RVCO
75k
+
3V
3V 10kHz TO 100kHz
fOUT
VCTRL
VSET
1/2
LTC6078
R4
30.1k
C4
33pF
R3
100k
0.4V TO 4V
VIN
fOUT =1MHz • 50k
NDIV RVCO
RVCO
RSET
+V
IN
VSET
1
R4
R3
IF R4
R3 =RVCO
RSET
, THE EQUATION REDUCES TO:
fOUT = 1MHz • 50k
NDIV RSET
V
IN
VSET
=V
IN • 25kHz/V
LTC6990
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Figure 14. Digitally Controlled Oscillator with VSET Variation Eliminated
6990 F14
LTC6990
OE
GND
SET
OUT
V+
DIV
C1
0.1µF R1
R2
RSET
V+
RVCO
+
V+
1/2
LTC6078
LTC1659
V+
VCC REF
GND
VOUT
µP
DIN
CLK
CS/LD
fOUT =1MHz • 50k
NDIV RVCO
• 1+RVCO
RSET
DIN
4096
DIN = 0 to 4095
Additionally, by choosing the VCOs specifications
shrewdly, the frequency error (in percent) due to VSET
variation is reduced toVSET/VSET = ±3%. To realize this
improvement, the design must abide by three conditions.
First, the VIN voltage must be positive throughout the
range. Second, choose VMAX/VMINfMAX /fMIN. Last,
choose RVCO/RSET ≥ R4/R3.
Figure 13 shows a design similar to the previous design
example where the VMIN voltage is now specified to be
0.4V. This satisfies the VMAX/VMINfMAX /fMIN condition
and the design assures that the output frequency error
due to VSET variation is only ±3%.
Eliminating VSET Error Effects with DAC Frequency
Control
Many DACs allow for the use of an external reference.
If such a DAC is used to provide the VCTRL voltage, the
VSET error is eliminated by buffering VSET and using it as
the DAC’s reference voltage, as shown in Figure 14. The
DAC’s output voltage now tracks any VSET variation and
eliminates it as an error source. The SET pin cannot be
tied directly to the reference input of the DAC because
the current drawn by the DAC’s REF input would affect
the frequency.
APPLICATIONS INFORMATION
ISET Extremes (Master Oscillator Frequency Extremes)
Pushing ISET outside of the recommended 1.25µA to 20µA
range forces the master oscillator to operate outside of the
62.5kHz to 1MHz range in which it is most accurate. The
oscillator will still function with reduced accuracy in its
extended range (see the Electrical Characteristics section).
The LTC6990 is designed to function normally for ISET
as low as 1.25µA. At approximately 500nA, the oscillator
output will be frozen in its current state. For NDIV = 1 or 2,
OUT will halt in a low state. But for larger divider ratios,
it could halt in a high or low state. This avoids introduc-
ing short pulses while modulating a very low frequency
output. Note that the output will not be
disabled
as when
OE is low (e.g. the output will not enter a high impedance
state if Hi-Z = 1).
At the other extreme, the master oscillator frequency can
reach 2MHz for ISET = 40μA (RSET = 25k). It is not recom-
mended to operate the master oscillator beyond 2MHz
because the accuracy of the DIV pin ADC will suffer.
LTC6990
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APPLICATIONS INFORMATION
Modulation Bandwidth and Settling Time
The LTC6990 will respond to changes in ISET up to a –3dB
bandwidth of 0.4 • fOUT (see Figure 15). This makes it easy
to stabilize a feedback loop around the LTC6990, since it
does not introduce a low-frequency pole.
Settling time depends on the master oscillator frequency.
Following a 2x or 0.5x step change in ISET, the output
frequency takes approximately six master clock cycles
(6 • tMASTER) to settle to within 1% of the final value. An
example is shown in Figure 16.
Power Supply Current
The power supply current varies with frequency, supply
voltage and output loading. It can be estimated under any
condition using the following equation:
IS(TYP) V
+
• fMASTER • 7pF +V
+
• fOUT(13pF +CLOAD )
+V+
480k+V+
2 •RLOAD
+1.75 •ISET +50µA
The equation is also valid for OE = 0 (output disabled),
with fOUT = 0Hz.
Figure 15. Modulation Frequency Response
Figure 16. Settling Time
fMOD/fOUT (Hz/Hz)
0.1
f
OUT
(f
MOD
)/f
OUT
(DC) (dB)
0
–20
–30
–10
–40 1
6990 F15
10
VCTRL = 0.536V + 0.278V
• SIN(2πfMODt)
fOUT =18.75kHz ±10%
–3dB AT 0.4fOUT
RSET = 200k
RVCO = 464k
DIVCODE = 4(÷16)
10µs/DIV 6990 F16
V
CTRL
2V/DIV
fOUT
50kHz/DIV
OUT
2V/DIV
V+ = 3.3V, DIVCODE = 0
RSET = 200k, RVCO = 464k
fOUT = 175kHz AND 350kHz
LTC6990
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6990 F17
LTC6990
OE
GND
SET
OUT
V+
DIV
C1
0.1µF R1
R2
RSET
V+
V+
DIV
SET
OUT
GND
OE
C1R1
R2
V+
RSET
DCB PACKAGE
OE
GND
SET
OUT
V+
DIV
R2
V+
RSET
TSOT-23 PACKAGE
R1
C1
Figure 17. Supply Bypassing and PCB Layout
APPLICATIONS INFORMATION
SUPPLY BYPASSING AND PCB LAYOUT GUIDELINES
The LTC6990 is a 2.2% accurate silicon oscillator when
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance
is easily achieved. The most important use issues involve
adequate supply bypassing and proper PCB layout.
Figure 17 shows example PCB layouts for both the SOT-23
and DCB packages using 0603 sized passive components.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6990. These layouts are
a guide and need not be followed exactly.
1. Connect the bypass capacitor, C1, directly to the V+ and
GND pins using a low inductance path. The connection
from C1 to the V+ pin is easily done directly on the top
layer. For the DCB package, C1’s connection to GND is
also simply done on the top layer. For the SOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that, C1’s GND connection can be accomplished through
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1µF ceramic capacitor.
2. Place all passive components on the top side of the
board. This minimizes trace inductance.
3. Place RSET as close as possible to the SET pin and
make a direct, short connection. The SET pin is a
current summing node and currents injected into this
pin directly modulate the operating frequency. Having
a short connection minimizes the exposure to signal
pickup.
4. Connect RSET directly to the GND pin. Using a long path
or vias to the ground plane will not have a significant
affect on accuracy, but the direct, short connection is
recommended and easy to apply.
5. Use a ground trace to shield the SET pin. This provides
another layer of protection from radiated signals.
6. Place R1 and R2 close to the DIV pin. A direct, short
connection to the DIV pin minimizes the external signal
coupling.
LTC6990
22
6990fc
For more information www.linear.com/LTC6990
TYPICAL APPLICATIONS
Full Range VCO with Any NDIV Setting (fMAX to fMIN for VIN = 0V to VSET)
6990 TA03
LTC6990
5V
OE
GND
SET
OUT
V+
DIV
C1
0.1µF R1
R2
RSET
826k
5V
5V
D1
IN4148
+
LT1490
RVCO1
26.1k
VIN
0V TO 1V
RVCO2
26.1k
Full Range VCO with Any NDIV Setting (Positive Frequency Control, fMIN to fMAX for VIN = 0V to VSET
6990 TA04
LTC6990
5V
OE
GND
SET
OUT
V+
DIV
C1
0.1µF R1
R2
RSET2
412k
RSET1
412k
5V
5V
+
LT1490
R3
10k
VIN
0V TO 1V
R4
10k
RVCO
53.6k
Programming NDIV Using an 8-Bit DAC
6990 TA02
LTC6990
OE
GND
SET
OUT
V+
DIV
C1
0.1µF
RSET
619k
2.25V TO 5.5V
C2
0.1µF
µPLTC2630-LZ8
SDI
SCK
CS/LD
VCC
GND
VOUT
DIVCODE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DAC CODE
0
24
40
56
72
88
104
120
136
152
168
184
200
216
232
255
LTC6990
23
6990fc
For more information www.linear.com/LTC6990
TYPICAL APPLICATIONS
Speaker Alarm. Modulate Tone with RVCO within 500Hz to 8kHz Span
6990 TA05
LTC6990
OE
GND
SET
OUT
V+
DIV
1M
887k97.6k
STEP
RAMP
5V
5V
RVCO
20k
5V
50k
8Ω
2N2222
IN4004
Overvoltage Detector/Alarm. Direct Drive of Piezo Alarm
6990 TA06
LTC6990
5V
24V
OE
GND
SET
OUT
V+
DIV
1M
PIEZO ALARM
4kHz
MURATA
PKM29-3A0
100k
523k392k
RB
10.7k
RA
787k
5V
400mV
+
LT6703-3
VALARM =400mV 1+RA
RB
=30V
LTC6990
24
6990fc
For more information www.linear.com/LTC6990
TYPICAL APPLICATIONS
Isolated V F Converter. VIN Provided by Isolated Measurement Circuit.
5µs Rise/Fall Time of Isolator Limits fMAX to 60kHz
6990 TA08
LTC6990
5V
365Ω
3.3V
OE
GND
SET
OUT
V+
DIV
1M
523k
412Ω fOUT
157k
VIN
0V TO 5V
75k
5V
MOC207M
6990 TA07
LTC6990
5V
OE
GND
SET
OUT
V+
DIV
1M
PIEZO ALARM
MURATA
PKM29-340
f = 4kHz
10k
ON
OFF
523k392k
5V
Direct Piezo Alarm Driver. Adjust Frequency for Maximum Alarm Sound Pressure
(Maximum Annoyance for Best Effect)
LTC6990
25
6990fc
For more information www.linear.com/LTC6990
6990 TA09
LTC6990
OE
GND
SET
OUT
V+
DIV
R1
1M
2k
1M
SINE COSINE
R2
280k
*1/2 OF AN LTC1060 FILTER CAN
BE USED IN PLACE OF THE LTC1059
0.1µF
4.12k
1M
RSET
49.9k
RVCO
267k FREQ
ADJ
5V
5V
+
LTC1440
OUT
1.18VREF HYST
LT1004-2.5V
2.5V
2.5V FOR 5Hz TO 10kHz
5V FOR 10Hz TO 20kHz
50/100
BPS1
N
+
LP
CLOCK
LTC1059*
SA
VCC
V
5V
AGND
+
10k
124k
5.11k
INV1
51.1k
1.18VREF
5V
14
8
142
3
5 11 9
Quadrature Sine Wave Oscillator. Voltage Controlled Frequency Range
from ~5Hz to ~20kHz with 1VP-P Constant Output Amplitude
TYPICAL APPLICATIONS
6990 TA10
LTC6990
OE
GND
SET
OUT
V+
DIV
1M
523k21.5k
+
22k AT 25°C
B = 3964
THERMISTOR: VISHAY NTHS120601N2202J
5V
fOUT
5V
60.4k
Temperature to Frequency Converter.
3% Linearity from –20°C (fOUT ≈ 20kHz) to 75°C (fOUT ≈ 25kHz)
LTC6990
26
6990fc
For more information www.linear.com/LTC6990
TYPICAL APPLICATIONS
6990 TA11
LTC6990
OE
GND
SET
OUT
V+
DIV
1M
681k10k
+
22k AT 25°C
B = 3964
26k
5V
fOUT
5V
100k
5V
10k
26k
+
LT1490
THERMISTOR: VISHAY NTHS120601N2202J
Full Range Temperature to Frequency Converter. 16kHz to 1kHz from –20°C to 80°C
6990 TA12
LTC6990
OE
GND
SET
OUT
V+
DIV
187k
1M619k
SFH213
IPD 5V
fOUT
5V
222k
5V
24.9k
1000pF
+
LT1677
Light to Frequency Converter. fOUT ≈ –1.4kHz per Microampere of Photo Diode Current, IPD
LTC6990
27
6990fc
For more information www.linear.com/LTC6990
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
3.00 ±0.10
(2 SIDES)
2.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
1.35 ±0.10
(2 SIDES)
1
3
64
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DCB6) DFN 0405
0.25 ±0.05
0.50 BSC
PIN 1 NOTCH
R0.20 OR 0.25
× 45° CHAMFER
0.25 ±0.05
1.35 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)
2.15 ±0.05
0.70 ±0.05
3.55 ±0.05
PACKAGE
OUTLINE
0.50 BSC
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
LTC6990
28
6990fc
For more information www.linear.com/LTC6990
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) S6 TSOT-23 0302
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
LTC6990
29
6990fc
For more information www.linear.com/LTC6990
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 7/11 Updated Features, Description, Pin Configuration, and Order Information sections
Added additional information to ∆fOUT/∆V+ and included Note 11 in Electrical Characteristics section
Added Typical Frequency Error vs Time curve to Typical Performance Characteristics section
Modified drawing in SET pin description in Pin Functions
Added text to Basic Fixed Frequency Operation paragraph in Applications Information section
Updated Related Parts list
1, 2
3, 4
7
8
15
30
B 01/12 Added MP-grade 1, 2, 4
C 02/14 Web links added
Schematic edits to Quadrature Sine Wave Oscillator circuit
Edits to description of LTC6906 and LTC6907 (Related Parts)
1-30
25
30
LTC6990
30
6990fc
For more information www.linear.com/LTC6990
LINEAR TECHNOLOGY CORPORATION 2010
LT 0214 REV C • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507 www.linear.com/2364-16
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1799 1MHz to 33MHz ThinSOT Silicon Oscillator Wide Frequency Range
LTC6900 1MHz to 20MHz ThinSOT Silicon Oscillator Low Power, Wide Frequency Range
LTC6906 10kHz to 1MHz ThinSOT Silicon Oscillator Micropower, ISUPPLY = 12µA at 100kHz
LTC6907 40kHz to 4MHz ThinSOT Silicon Oscillator Micropower, ISUPPLY = 35µA at 400kHz
LTC6930 Fixed Frequency Oscillator, 32.768kHz to 8.192MHz 0.09% Accuracy, 110µs Start-Up Time, 105µA at 32kHz
LTC6991 TimerBlox, Very Low Frequency Clock with Reset Cycle Time from 2ms to 9.5 Hours, No Caps, 2.2% Accurate
LTC6992 TimerBlox, Voltage-Controlled Pulse Width Modulator
(PWM)Simple PWM with Wide Frequency Range
LTC6993 TimerBlox, Monostable Pulse Generator Resistor Set Pulse Width from 1µs to 34sec, No Caps, 3% Accurate
LTC6994 TimerBlox, Delay Block/Debouncer Resistor Set Delay from 1µs to 34sec, No Caps Required, 3% Accurate
TYPICAL APPLICATION
Ultrasonic Frequency Sweep Generator
6990 TA13
LTC6990
OE
GND
SET
OUT
V+
DIV
C1
0.1µF R1
976k
R2
102k
RSET1
49.9k
RSET2
750k
CSET
0.022µF
2.25V TO 5.5V
fOUT = 500kHz TO 31.25kHz
OE
74HC125
SWEEPS FROM 500kHz to 31.25kHz IN A
FEW MILLISECONDS (CONTROLLED BY CSET).

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