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ADP150 Datasheet

Analog Devices Inc.

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Datasheet

Ultralow Noise,
150 mA CMOS Linear Regulator
Data Sheet ADP150
Rev. C Document Feedback
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Tel: 781.329.4700 ©2009-2015 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Ultra low noise: 9 μV rms, independent of VOUT
No additional noise bypass capacitor required
Stable with 1 μF ceramic input and output capacitors
Maximum output current: 150 mA
Input voltage range: 2.2 V to 5.5 V
Low quiescent current
IGND = 10 μA with zero load
Low shutdown current: <1 μA
Low dropout voltage: 105 mV @ 150 mA load
Initial output voltage accuracy: ±1%
Up to 14 fixed output voltage options: 1.8 V to 3.3 V
PSRR performance of 70 dB at 10 kHz
Current limit and thermal overload protection
Logic-controlled enable
5-lead TSOT package
4-ball, 0.8 mm × 0.8 mm, 0.4 mm pitch WLCSP
APPLICATIONS
Mobile phones
Digital camera and audio devices
Portable and battery-powered equipment
Post dc-to-dc regulation
Portable medical devices
RF, PLL, VCO, and clock power supplies
TYPICAL APPLICATION CIRCUITS
08343-001
NC = NO CONNECT
1
2
3
5
4
C
OUT
1µF
C
IN
1µF
V
OUT
= 1.8
V
V
IN
= 2.3V VOUT
NC
VIN
GND
EN
OFF
ON
Figure 1. 5-Lead TSOT with Fixed Output Voltage, 1.8 V
VIN VOUT
12
EN GND
C
OUT
1µF
C
IN
1µF
V
OUT
= 1.8V
V
IN
= 2.3V
TOP VIEW
(Not to Scale)
A
B
08343-002
OFF
ON
Figure 2. 4-Ball WLCSP with Fixed Output Voltage, 1.8 V
GENERAL DESCRIPTION
The ADP150 is an ultralow noise (9 μV), low dropout, linear
regulator that operates from 2.2 V to 5.5 V and provides up to
150 mA of output current. The low 105 mV dropout voltage at
150 mA load improves efficiency and allows operation over a
wide input voltage range.
Using an innovative circuit topology, the ADP150 achieves ultralow
noise performance without the necessity of an additional noise
bypass capacitor, making it ideal for noise sensitive analog and
RF applications. The ADP150 also achieves ultralow noise
performance without compromising PSRR or line and load
transient performance. The ADP150 offers the best combination
of ultralow noise and quiescent current consumption to maximize
battery life in portable applications.
The ADP150 is specifically designed for stable operation with
tiny 1 μF ± 30% ceramic input and output capacitors to meet
the requirements of high performance, space-constrained
applications.
The ADP150 is available in 14 fixed output voltage options,
ranging from 1.8 V to 3.3 V.
Short-circuit and thermal overload protection circuits prevent
damage in adverse conditions. The ADP150 is available in tiny
5-lead TSOT and 4-ball, 0.4 mm pitch WLCSP packages for the
smallest footprint solution to meet a variety of portable power
applications.
ADP150 Data Sheet
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Application Circuits ............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Recommended Specifications: Input and Output Capacitor .. 4
Absolute Maximum Ratings ............................................................ 5
Thermal Data ................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 11
Applications Information .............................................................. 12
Capacitor Selection .................................................................... 12
Undervoltage Lockout ............................................................... 13
Enable Feature ............................................................................ 13
Current Limit and Thermal Overload Protection ................. 13
Thermal Considerations ............................................................ 14
PCB Layout Considerations ...................................................... 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 19
REVISION HISTORY
8/15Rev. B to Rev. C
Changes to Ordering Guide .......................................................... 19
8/13Rev. A to Rev. B
Changes to Ordering Guide .......................................................... 19
4/10Rev. 0 to Rev. A
Changes to Figure 21 ........................................................................ 9
10/09Revision 0: Initial Version
Data Sheet ADP150
Rev. C | Page 3 of 20
SPECIFICATIONS
VIN = (VOUT + 0.4 V) or 2.2 V, whichever is greater; EN = VIN, IOUT = 10 mA, CIN = COUT = 1 µF, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE V
IN
T
J
= −40°C to +125°C 2.2 5.5 V
OPERATING SUPPLY CURRENT I
GND
I
OUT
= 0 µA 10 µA
I
OUT
= 0 µA, T
J
= −40°C to +125°C 22 µA
IOUT = 100 µA
20
I
OUT
= 100 µA, T
J
= −40°C to +125°C 40 µA
I
OUT
= 10 mA 60 µA
I
OUT
= 10 mA, T
J
= −40°C to +125°C 100 µA
I
OUT
= 150 mA 220 µA
I
OUT
= 150 mA, T
J
= −40°C to +125°C 320 µA
SHUTDOWN CURRENT I
GND-SD
EN = GND 0.2 µA
EN = GND, T
J
= −40°C to +125°C 1.0 µA
OUTPUT VOLTAGE ACCURACY
5-Lead TSOT V
OUT
I
OUT
= 10 mA −1 +1 %
100 µA < IOUT < 150 mA, VIN = (VOUT + 0.4 V) to 5.5 V,
T
J
= −40°C to +125°C
−2.5 +1.5 %
4-Ball WLCSP V
OUT
I
OUT
= 10 mA −1 +1 %
100 µA < IOUT < 150 mA, VIN = (VOUT + 0.4 V) to 5.5 V,
T
J
= −40°C to +125°C
−2.0 +1.5 %
REGULATION
Line Regulation ∆V
OUT
/∆V
IN
V
IN
= (V
OUT
+ 0.4 V) to 5.5 V, T
J
= −40°C to +125°C 0.05 +0.05 %/V
Load Regulation1
5-Lead TSOT ∆V
OUT
/∆I
OUT
I
OUT
= 100 µA to 150 mA 0.003 %/mA
I
OUT
= 100 µA to 150 mA, T
J
= −40°C to +125°C 0.0075 %/mA
4-Ball WLCSP ∆V
OUT
/∆I
OUT
I
OUT
= 100 µA to 150 mA 0.002 %/mA
I
OUT
= 100 µA to 150 mA, T
J
= −40°C to +125°C 0.006 %/mA
DROPOUT VOLTAGE2 V
DROPOUT
I
OUT
= 10 mA 10 mV
IOUT = 10 mA, TJ = −40°C to +125°C
35
I
OUT
= 150 mA 105 mV
I
OUT
= 150 mA, T
J
= −40°C to +125°C 160 mV
START-UP TIME
3
T
START-UP
V
OUT
= 3.3 V 150 µs
CURRENT LIMIT THRESHOLD4 I
LIMIT
190 260 400 mA
UNDERVOLTAGE LOCKOUT UVLO
Input Voltage Rising UVLO
RISE
T
J
= −40°C to +125°C 1.96 V
Input Voltage Falling UVLO
FAL L
T
J
= −40°C to +125°C 1.28 V
Hysteresis
UVLOHYS
TJ = −40°C to +125°C
115
THERMAL SHUTDOWN
Thermal Shutdown Threshold TSSD TJ rising 150 °C
Thermal Shutdown Hysteresis TSSD-HYS 15 °C
EN INPUT
EN Input Logic High V
IH
2.2 V ≤ V
IN
5.5 V 1.2 V
EN Input Logic Low V
IL
2.2 V ≤ V
IN
5.5 V 0.4 V
EN Input Leakage Current V
I-LEAKAGE
EN = IN or GND 0.001 µA
EN = IN or GND, T
J
= −40°C to +125°C 1 µA
OUTPUT NOISE OUT
NOISE
10 Hz to 100 kHz, V
IN
= 5 V, V
OUT
= 3.3 V 9 µV rms
10 Hz to 100 kHz, V
IN
= 5 V, V
OUT
= 2.5 V 9 µV rms
10 Hz to 100 kHz, V
IN
= 5 V, V
OUT
= 1.8 V 9 µV rms
ADP150 Data Sheet
Rev. C | Page 4 of 20
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY REJECTION RATIO
(V
IN
= V
OUT
+ 0.5 V)
PSRR 10 kHz, VIN = 3.8 V, VOUT = 3.3 V, IOUT = 10 mA 70 dB
10 kHz, V
IN
= 2.3 V, V
OUT
= 1.8 V, I
OUT
= 10 mA 70 dB
100 kHz, V
IN
= 3.8 V, V
OUT
= 3.3 V, I
OUT
= 10 mA 55 dB
100 kHz, V
IN
= 2.3 V, V
OUT
= 1.8 V, I
OUT
= 10 mA 55 dB
POWER SUPPLY REJECTION RATIO
(VIN = VOUT + 1 V)
10 kHz, VIN = 4.3 V, VOUT = 3.3 V, IOUT = 10 mA 70 dB
100 kHz, V
IN
= 4.3 V, V
OUT
= 3.3 V, I
OUT
= 10 mA 55 dB
1 Based on an end-point calculation using 1 mA and 150 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA.
2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.2 V.
3 Start-up time is defined as the time between the rising edges of EN to VOUT being at 90% of its nominal value.
4 Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V or 2.7 V.
RECOMMENDED SPECIFICATIONS: INPUT AND OUTPUT CAPACITOR
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT AND OUTPUT CAPACITOR
Minimum Input and Output Capacitance1 C
MIN
T
A
= −40°C to +125°C 0.7 µF
Capacitor ESR R
ESR
T
A
= −40°C to +125°C 0.001 0.2
1 The minimum input and output capacitance should be greater than 0.7 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R-type and X5R-type capacitors are
recommended, and Y5V and Z5U capacitors are not recommended for use with any LDO.
Data Sheet ADP150
Rev. C | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN to GND 0.3 V to +6.5 V
VOUT to GND 0.3 V to VIN
EN to GND 0.3 V to +6.5 V
Storage Temperature Range 65°C to +150°C
Operating Junction Temperature Range 40°C to +125°C
Operating Ambient Temperature Range −40°C to +85°C
Soldering Conditions JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP150 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that TJ is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated.
In applications with moderate power dissipation and low printed
circuit board (PCB) thermal resistance, the maximum ambient
temperature can exceed the maximum limit as long as the junction
temperature is within specification limits. The junction
temperature (TJ) of the device is dependent on the ambient
temperature (TA), the power dissipation of the device (PD), and
the junction-to-ambient thermal resistance of the package (θJA).
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) by
TJ = TA + (PD × θJA)
The junction-to-ambient thermal resistance (θJA) of the package
is based on modeling and a calculation using a 4-layer board.
The junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA can vary, depending on
PCB material, layout, and environmental conditions. The specified
values of θJA are based on a 4-layer, 4 inch × 3 inch circuit board.
Refer to JESD 51-7 and JESD 51-9 for detailed information
on the board construction. For additional information, see
the AN-617 Application Note, MicroCSPWafer Level Chip
Scale Package.
ΨJB is the junction-to-board thermal characterization parameter
with units of ° C / W. ΨJB of the package is based on modeling and
a calculation using a 4-layer board. The JESD51-12, Guidelines
for Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as thermal
resistances. ΨJB measures the component power flowing through
multiple thermal paths rather than a single path as in thermal
resistance, θJB. Therefore, ΨJB thermal paths include convection
from the top of the package as well as radiation from the package,
factors that make ΨJB more useful in real-world applications.
Maximum junction temperature (TJ) is calculated from the
board temperature (TB) and power dissipation (PD) by
TJ = TB + (PD × ΨJB)
Refer to JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θ
JA
Ψ
JB
Unit
5-Lead TSOT 170 43 °C/W
4-Ball, 0.4 mm Pitch WLCSP 260 58 °C/W
ESD CAUTION
ADP150 Data Sheet
Rev. C | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NC = NO CONNECT
TOP VIEW
(Not to Scale)
ADP150
1
2
3
5
4
VIN
GND
EN
VOUT
NC
0
8343-003
Figure 3. 5-Lead TSOT Pin Configuration
12
A
B
TOP VIEW
(Not to Scale)
VIN VOUT
EN GND
08343-004
Figure 4. 4-Ball WLCSP Pin Configuration
Table 5. 5-Lead TSOT Pin Function Descriptions
Pin No. Mnemonic Description
1 VIN Regulator Input Supply. Bypass VIN to
GND with a 1 μF or greater capacitor.
2 GND Ground.
3 EN Enable Input. Drive EN high to turn on
the regulator; drive EN low to turn off
the regulator. For automatic startup,
connect EN to VIN.
4 NC No Connect. Not connected internally.
5 VOUT
Regulated Output Voltage. Bypass VOUT
to GND with a 1 μF or greater capacitor.
Table 6. 4-Ball WLCSP Pin Function Descriptions
Pin No. Mnemonic Description
A1 VIN Regulator Input Supply. Bypass VIN to
GND with a 1 μF or greater capacitor.
A2 VOUT Regulated Output Voltage. Bypass VOUT
to GND with a 1 μF or greater capacitor.
B1 EN Enable Input. Drive EN high to turn on
the regulator; drive EN low to turn off
the regulator. For automatic startup,
connect EN to VIN.
B2 GND Ground.
Data Sheet ADP150
Rev. C | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 3.7 V, VOUT = 3.3 V, IOUT = 1 mA, CIN = COUT = 1 μF, TA = 25°C, unless otherwise noted.
3.315
3.265
3.270
3.275
3.280
3.285
3.290
3.295
3.300
3.305
3.310
4052585125
V
OUT
(V)
JUNCTION TEMPERATURE (°C)
08343-005
I
OUT
= 0.1mA
I
OUT
= 1mA
I
OUT
= 10mA
I
OUT
= 50mA
I
OUT
= 100mA
I
OUT
= 150mA
Figure 5. Output Voltage (VOUT) vs. Junction Temperature
3.298
3.290
3.291
3.292
3.293
3.294
3.295
3.296
3.297
0.01 10001001010.1
V
OUT
(V)
I
OUT
(mA)
08343-006
Figure 6. Output Voltage (VOUT) vs. Load Current (IOUT)
3.300
3.288
3.290
3.292
3.294
3.296
3.298
3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
V
OUT
(V)
V
IN
(V)
08343-007
I
OUT
= 0.1mA
I
OUT
= 1mA
I
OUT
= 10mA
I
OUT
= 150mA
I
OUT
= 50mA
I
OUT
= 100mA
Figure 7. Output Voltage (VOUT) vs. Input Voltage (VIN)
300
250
200
150
100
50
0–40 –5 25 85 125
GROUND CURRENT (µA)
JUNCTION TEMPERATURE (°C)
08343-008
I
OUT
= 0.1mA
I
OUT
= 1mA
I
OUT
= 10mA
I
OUT
= 50mA
I
OUT
= 100mA
I
OUT
= 150mA
Figure 8. Ground Current vs. Junction Temperature
08343-009
250
0
50
100
150
200
0.01 10001001010.1
GROUND CURRENT (µA)
I
OUT
(mA)
Figure 9. Ground Current vs. Load Current (IOUT)
250
200
150
100
50
0
3.5 5.55.35.14.94.74.54.34.13.93.7
GROUND CURRENT (µA)
V
IN
(V)
08343-010
I
OUT
= 0.1mA
I
OUT
= 1mA
I
OUT
= 10mA
I
OUT
= 50mA
I
OUT
= 100mA
I
OUT
= 150mA
Figure 10. Ground Current vs. Input Voltage (VIN)
ADP150 Data Sheet
Rev. C | Page 8 of 20
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–50 –25 1251007550250
SHUTDOWN CURRENT (µA)
TEMPERATURE (°C)
08343-011
V
IN
= 3.6V
V
IN
= 3.8V
V
IN
= 4.2V
V
IN
= 4.4V
V
IN
= 5.0V
V
IN
= 5.2V
V
IN
= 5.4V
V
IN
= 5.5V
Figure 11. Shutdown Current vs. Temperature at Various Input Voltages
80
70
60
50
40
30
20
10
01 10 100 1000
DROPOUT (mA)
I
OUT
(mA)
08343-012
Figure 12. Dropout Voltage vs. Load Current (ILOAD)
3.35
3.30
3.25
3.20
3.15
3.10
3.00
3.05
3.05 3.10 3.453.403.353.303.253.203.15
V
OUT
(V)
V
IN
(V)
08343-013
I
OUT
= 10mA
I
OUT
= 50mA
I
OUT
= 100mA
I
OUT
= 150mA
Figure 13. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout
700
600
500
400
300
200
100
0
3.05 3.10 3.453.403.353.303.253.203.15
GROUND CURRENT (µA)
V
IN
(A)
08343-014
I
OUT
= 10mA
I
OUT
= 50mA
I
OUT
= 100mA
I
OUT
= 150mA
Figure 14. Ground Current vs. Input Voltage (VIN) in Dropout
10
–20
–30
–40
–50
–60
–70
–80
–90
–10010 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
I
OUT
= 100µA
I
OUT
= 1mA
I
OUT
= 10mA
I
OUT
= 100mA
I
OUT
= 150mA
08343-015
V
IN
= V
OUT
+ 0.5V
V
RIPPLE
= 50mV
C
IN
= C
OUT
= 1µF
Figure 15. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = 1.8 V, VIN = 2.3 V
10
–20
–30
–40
–50
–60
–70
–80
–90
–10010 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
I
OUT
= 100µA
I
OUT
= 1mA
I
OUT
= 10mA
I
OUT
= 100mA
I
OUT
= 150mA
08343-016
V
IN
= V
OUT
+ 0.5V
V
RIPPLE
= 50mV
C
IN
= C
OUT
= 1µF
Figure 16. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = 2.8 V, VIN=3.3 V
Data Sheet ADP150
Rev. C | Page 9 of 20
10
–20
–30
–40
–50
–60
–70
–80
–90
–10010 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
I
OUT
= 100µA
I
OUT
= 1mA
I
OUT
= 10mA
I
OUT
= 100mA
I
OUT
= 150mA
08343-017
V
IN
= V
OUT
+ 0.5V
V
RIPPLE
= 50mV
C
IN
= C
OUT
= 1µF
Figure 17. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = 3.3 V, VIN = 3.8 V
10
–20
–30
–40
–50
–60
–70
–80
–90
–10010 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
V
OUT
= 1.8V, I
OUT
= 100µA
V
OUT
= 2.8V, I
OUT
= 100µA
V
OUT
= 3.3V, I
OUT
= 100µA
V
OUT
= 1.8V, I
OUT
= 150mA
V
OUT
= 2.8V, I
OUT
= 150mA
V
OUT
= 3.3V, I
OUT
= 150mA
08343-018
V
IN
= V
OUT
+ 0.5V
V
RIPPLE
= 50mV
C
IN
= C
OUT
= 1µF
Figure 18. Power Supply Rejection Ratio (PSRR) vs. Frequency
Various Output Voltages and Load Currents
10
–20
–30
–40
–50
–60
–70
–80
–90
–10010 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
V
IN
= 3.8V, I
OUT
= 1mA
V
IN
= 4.3V, I
OUT
= 1mA
V
IN
= 5.3V, I
OUT
= 1mA
V
IN
= 3.8V, I
OUT
= 150mA
V
IN
= 4.3V, I
OUT
= 150mA
V
IN
= 5.3V, I
OUT
= 150mA
08343-019
V
RIPPLE
= 50mV
C
IN
= C
OUT
= 1µF
Figure 19. Power Supply Rejection Ratio (PSRR) vs. Frequency with
Various Headroom Voltages (VIN − VOUT), VOUT = 3.3 V
15
13
11
9
7
5
3
1
0.001 0.01 0.1 1 10 100 1k
RMS NOISE (µV)
I
OUT
(mA)
V
OUT
= 3.3V
V
OUT
= 2.8V
V
OUT
= 1.8V
08343-021
Figure 20. Output RMS Noise vs. Load Current (IOUT) and
Output Voltage (VOUT), VIN = 5 V, COUT = 1 µF
1
0.01
0.1
10 100 1k 10k 100k
NOISE (µV/ Hz)
FREQUENCY (Hz)
V
OUT
= 1.8V
V
OUT
= 2.8V
V
OUT
= 3.3V
08343-020
Figure 21. Output Noise Spectrum, VIN = 5 V, ILOAD = 10 mA, COUT = 1 F
CH1 100mA CH2 50mV M40µs A CH1 112mA
T 117.560µs
1
2
T
08343-022
I
OUT
1mA TO 150mA LOAD STEP
V
OUT
V
IN
= 3.7V
V
OUT
= 3.3V
Figure 22. Load Transient Response, COUT = 1 µF
ADP150 Data Sheet
Rev. C | Page 10 of 20
CH1 100mA CH2 50mV M40µs A CH1 108mA
T 118.000µs
1
2
T
08343-023
I
OUT
1mA TO 150mA LOAD STEP
V
OUT
V
IN
= 3.7V
V
OUT
= 3.3V
Figure 23. Load Transient Response, COUT = 4.7 μF
CH1 1.00V CH2 10mV M10µs A CH1 4.60V
T 29.60µs
1
2
T
08343-024
V
IN
3.7V TO 4.7V VOLTAGE STEP
OFFSET = 2.7V
V
OUT
Figure 24. Line Transient Response, CIN, COUT = 1 μF, ILOAD = 1mA
CH1 1.00V CH2 10mV M10µs A CH1 4.60V
T 29.60µs
1
2
T
08343-125
V
IN
3.7V TO 4.7V VOLTAGE STEP
OFFSET = 2.7V
V
OUT
Figure 25. Line Transient Response, CIN, COUT =1 μF, ILOAD = 150 mA
Data Sheet ADP150
Rev. C | Page 11 of 20
THEORY OF OPERATION
The ADP150 is an ultralow noise, low quiescent current, low
dropout linear regulator that operates from 2.2 V to 5.5 V and
can provide up to 150 mA of output current. Drawing a low 220 μA
of quiescent current (typical) at full load makes the ADP150 ideal
for battery-operated portable equipment. Shutdown current
consumption is typically 200 nA.
Using new innovative design techniques, the ADP150 provides
superior noise performance for noise sensitive analog and
RF applications without the need for a noise bypass capacitor.
The ADP150 is also optimized for use with small 1 μF ceramic
capacitors.
VOLTAGE
REFERENCE
SHORT CIRCUIT,
UVLO, AND
THERMAL
PROTECT
SHUTDOWN
R1
R2
V
OUTVIN
GND
EN
08343-025
Figure 26. Internal Block Diagram
Internally, the ADP150 consists of a reference, an error amplifier,
a feedback voltage divider, and a PMOS pass transistor. Output
current is delivered via the PMOS pass device that is controlled
by the error amplifier. The error amplifier compares the reference
voltage with the feedback voltage from the output and amplifies
the difference. If the feedback voltage is lower than the reference
voltage, the gate of the PMOS device is pulled lower, allowing
more current to pass and increasing the output voltage. If the
feedback voltage is higher than the reference voltage, the gate of
the PMOS device is pulled higher, allowing less current to pass
and decreasing the output voltage.
The ADP150 is available in 14 output voltage options, ranging
from 1.8 V to 3.3 V. The ADP150 uses the EN pin to enable and
disable the VOUT pin under normal operating conditions. When
EN is high, VOUT turns on, and when EN is low, VOUT turns
off. For automatic startup, EN can be tied to VIN.
ADP150 Data Sheet
Rev. C | Page 12 of 20
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP150 is designed for operation with small, space-saving
ceramic capacitors but functions with most commonly used
capacitors as long as care is taken with regard to the effective
series resistance (ESR) value. The ESR of the output capacitor
affects the stability of the LDO control loop. A minimum of 1 µF
capacitance with an ESR of 1or less is recommended to
ensure the stability of the ADP150. The transient response to
changes in load current is also affected by output capacitance.
Using a larger value of output capacitance improves the transient
response of the ADP150 to large changes in the load current.
Figure 27 and Figure 28 show the transient responses for output
capacitance values of 1 µF and 4.7 µF, respectively.
CH1 100mA CH2 50mV M1.0µs A CH1 100mA
T 716.000µs
1
2
T
08343-126
I
OUT
1mA TO 150mA LOAD STEP
V
OUT
V
IN
= 3.7V
V
OUT
= 3.3V
Figure 27. Output Transient Response, COUT = 1 µF
CH1 100mA CH2 50mV M1.0µs A CH1 108mA
T 240.000ns
1
2
T
08343-127
I
OUT
1mA TO 150mA LOAD STEP
V
OUT
V
IN
= 3.7V
V
OUT
= 3.3V
Figure 28. Output Transient Response, COUT = 4.7 µF
Input Bypass Capacitor
Connecting a 1 µF capacitor from VIN to GND reduces the
circuit sensitivity to the PCB layout, especially when long input
traces or high source impedance is encountered. If greater than
1 µF of output capacitance is required, increase the input capacitor
to match the output capacitor.
Input and Output Capacitor Properties
Any good quality ceramic capacitors can be used with the ADP150,
as long as they meet the minimum capacitance and maximum
ESR requirements. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior over temperature
and applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R or X7R dielectrics with a
voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U
dielectrics are not recommended, due to their poor temperature
and dc bias characteristics.
Figure 29 depicts the capacitance vs. the voltage bias characteristic
of a 0402, 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the X5R
dielectric is about ±15% over the 40°C to +85°C temperature
range and is not a function of package or voltage rating.
1.2
1.0
0.8
0.6
0.4
0.2
00246810
CAPACITANCE (µF)
BIAS VOLTAGE (V)
08343-100
Figure 29. Capacitance vs. Voltage Bias Characteristic
Use Equation 1 to determine the worst-case capacitance,
accounting for capacitor variation over temperature, component
tolerance, and voltage.
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL) (1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
the CBIAS is 0.94 µF at 1.8 V, as shown in Figure 29.
Substituting these values in Equation 1 yields
CEFF = 0.94 µF × (1 − 0.15) × (1 − 0.1) = 0.719 µF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature
and tolerance at the chosen output voltage.
Data Sheet ADP150
Rev. C | Page 13 of 20
To guarantee the performance of the ADP150, it is imperative
that the effects of the dc bias, temperature, and tolerances on
the behavior of the capacitors be evaluated for each.
UNDERVOLTAGE LOCKOUT
The ADP150 has an internal undervoltage lockout circuit that
disables all inputs and the output when the input voltage is less
than approximately 2.0 V. This ensures that the ADP150 inputs
and output behave in a predictable manner during power-up.
ENABLE FEATURE
The ADP150 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. As shown in Figure 30,
when a rising voltage on EN crosses the active threshold, VOUT
turns on. When a falling voltage on EN crosses the inactive
threshold, VOUT turns off.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
V
EN
V
OUT
08343-101
Figure 30. Typical EN Pin Operation
As shown in Figure 30, the EN pin has hysteresis built in. This
prevents on/off oscillations that can occur due to noise on the
EN pin as it passes through the threshold points.
The EN pin active/inactive thresholds are derived from the VIN
voltage; therefore, these thresholds vary with changing input
voltage. Figure 31 shows the typical EN active/inactive thresholds
when the input voltage varies from 2.2 V to 5.5 V.
1.1
0.4
0.5
0.6
0.7
0.8
0.9
1.0
TYPICAL THRESHOLD (V)
V
IN
(V)
5.55.34.84.33.83.32.82.3
RISING
FALLING
08343-102
Figure 31. Typical EN Pin Thresholds vs. Input Voltage (VIN)
The ADP150 uses an internal soft start to limit the inrush current
when the output is enabled. The start-up time for the 3.3 V
option is approximately 150 µs from the time the EN active
threshold is crossed to when the output reaches 90% of its final
value. As shown in Figure 32, the start-up time is dependent on
the output voltage setting.
1
1
1
CH1 1V CH2 1V
CH3 1V CH4 1V M40.0µs A CH1 3.24V
T 240.000ns
1
T
EN
V
OUT
= 3.3V
V
OUT
= 2.8V
V
OUT
= 1.8V
08343-128
Figure 32. Typical Start-Up Time
CURRENT LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP150 is protected against damage due to excessive
power dissipation by current and thermal overload protection
circuits. The ADP150 is designed to limit current when the
output load reaches 260 mA (typical). When the output load
exceeds 260 mA, the output voltage is reduced to maintain a
constant current limit.
Thermal overload protection is included, which limits the junction
temperature to a maximum of 150°C (typical). Under extreme
conditions (that is, high ambient temperature and power dissipation)
when the junction temperature starts to rise above 150°C, the
output is turned off, reducing the output current to zero. When
the junction temperature drops below 135°C, the output is turned
on again and the output current is restored to its nominal value.
Consider the case where a hard short from VOUT to GND occurs.
At first, the ADP150 limits current so that only 260 mA is
conducted into the short. If self-heating of the junction is great
enough to cause its temperature to rise above 150°C, thermal
shutdown activates, turning off the output and reducing the
output current to zero. As the junction temperature cools and
drops below 135°C, the output turns on and conducts 260 mA
into the short, again causing the junction temperature to rise
above 150°C. This thermal oscillation between 135°C and 150°C
causes a current oscillation between 260 mA and 0 mA that
continues as long as the short remains at the output.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For reliable
operation, device power dissipation must be externally limited
so that the junction temperatures do not exceed 125°C.
ADP150 Data Sheet
Rev. C | Page 14 of 20
THERMAL CONSIDERATIONS
In most applications, the ADP150 does not dissipate much heat
due to its high efficiency. However, in applications with high
ambient temperature and high supply voltage to output voltage
differential, the heat dissipated in the package is large enough
that it can cause the junction temperature of the die to exceed
the maximum junction temperature of 125°C.
When the junction temperature exceeds 150°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature decreases below 135°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application is
very important to guarantee reliable performance over all conditions.
The junction temperature of the die is the sum of the ambient
temperature of the environment and the temperature rise of the
package due to the power dissipation, as shown in Equation 2.
To guarantee reliable operation, the junction temperature of
the ADP150 must not exceed 125°C. To ensure that the junction
temperature stays below 125°C, be aware of the parameters that
contribute to the junction temperature changes. These parameters
include ambient temperature, power dissipation in the power
device, and thermal resistances between the junction and
ambient airJA). The θJA number is dependent on the package
assembly compounds that are used and the amount of copper
used to solder the package GND pins to the PCB. Table 7 shows
typical θJA values of the 5-lead TSOT and 4-ball WLCSP packages
for various PCB copper sizes. Table 8 shows the typical ΨJB
value of the 5-lead TSOT and 4-ball WLCSP.
Table 7. Typical θJA Values
θ
JA (°C/W)
Copper Size (mm2) TSOT WLCSP
01 170 260
50 152 159
100 146 157
300 134 153
500 131 151
1 Device soldered to minimum size pin traces.
Table 8. Typical ΨJB Values
ΨJB (°C/W)
TSOT WLCSP
42.8 58.4
Use Equation 2 to calculate the junction temperature.
TJ = TA + (PD × θJA) (2)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = ((VINVOUT) × ILOAD) + (VIN × IGND)
where:
ILOAD is the load current.
IGND is the ground current.
VIN and VOUT are input and output voltages, respectively.
Power dissipation due to ground current is quite small and can be
ignored. Therefore, the junction temperature equation simplifies to
TJ = TA + (((VINVOUT) × ILOAD) × θJA) (3)
As shown in the previous equation, for a given ambient temperature,
input-to-output voltage differential, and continuous load current,
there exists a minimum copper size requirement for the PCB to
ensure that the junction temperature does not rise above 125°C.
Figure 33 to Figure 46 show the junction temperature calculations
for the different ambient temperatures, load currents, VIN-to-VOUT
differentials, and areas of PCB copper.
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE, T
J
(°C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION TEMPERATURE
08343-228
Figure 33. TSOT, 500 mm2 of PCB Copper, TA = 25°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE,
T
J
(°C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION TEMPERATURE
08343-229
Figure 34. TSOT, 100 mm2 of PCB Copper, TA = 25°C
Data Sheet ADP150
Rev. C | Page 15 of 20
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE, T
J
C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION TEMPERATURE
08343-230
Figure 35. TSOT, 0 mm2 of PCB Copper, TA = 25°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE, T
J
C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION TEMPERATURE
08343-231
Figure 36. TSOT, 500 mm2 of PCB Copper, TA = 50°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE, T
J
C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION TEMPERATURE
08343-232
Figure 37. TSOT, 100 mm2 of PCB Copper, TA = 50°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE, T
J
C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION TEMPERATURE
08343-233
Figure 38. TSOT, 0 mm2 of PCB Copper, TA = 50°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE, T
J
C)
MAX JUNCTION TEMPERATURE
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
08343-248
Figure 39. TSOT, 100 mm2 of PCB Copper, Board Temperature = 85°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE, T
J
C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION TEMPERATURE
08343-042
Figure 40. WLCSP, 500 mm2 of PCB Copper, TA = 25°C
ADP150 Data Sheet
Rev. C | Page 16 of 20
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE, T
J
C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION TEMPERATURE
08343-043
Figure 41. WLCSP, 100 mm2 of PCB Copper, TA = 25°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE, T
J
C)
MAX JUNCTION
TEMPERATURE
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 50mA
I
LOAD
= 75mA
08343-044
Figure 42. WLCSP, 0 mm2 of PCB Copper, TA = 25°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE, T
J
C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION TEMPERATURE
08343-045
Figure 43. WLCSP, 500 mm2 of PCB Copper, TA = 50°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE, T
J
C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION TEMPERATURE
08343-046
Figure 44. WLCSP, 100 mm2 of PCB Copper, TA = 50°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE, T
J
C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION
TEMPERATURE
08343-047
Figure 45. WLCSP, 0 mm2 of PCB Copper, TA = 50°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE, T
J
C)
MAX JUNCTION TEMPERATURE
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
08343-049
Figure 46. WLCSP, 100 mm2 of PCB Copper, Board Temperature = 85°C
Data Sheet ADP150
Rev. C | Page 17 of 20
PCB LAYOUT CONSIDERATIONS
Heat dissipation from the package can be improved by
increasing the amount of copper attached to the pins of the
ADP150. However, as listed in Table 7, a point of diminishing
returns is reached eventually, beyond which an increase in the
copper size does not yield significant heat dissipation benefits.
Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitor as close as possible to the
VOUT and GND pins. Use of 0402 size or 0603 size capacitors
and resistors achieves the smallest possible footprint solution on
boards where area is limited.
08343-147
Figure 47. Example TSOT PCB Layout
08343-148
Figure 48. Example WLCSP PCB Layout
ADP150 Data Sheet
Rev. C | Page 18 of 20
OUTLINE DIMENSIONS
100708-A
*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
1.60 BSC 2.80 BSC
1.90
BSC
0.95 BSC
0.20
0.08
0.60
0.45
0.30
0.50
0.30
0.10 MAX
*1.00 MAX
*0.90 MAX
0.70 MIN
2.90 BSC
5 4
1 2 3
SEATING
PLANE
Figure 49. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions show in millimeters
0.800
0.760 SQ
0.720
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
A
1
2
B
BALLA1
IDENTIFIER
0.40
REF
0.660
0.600
0.540 END VIEW
0.280
0.260
0.240
0.430
0.400
0.370
SEATING
PLANE 0.230
0.200
0.170
COPLANARITY
0.05
04-18-2012-A
Figure 50. 4-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-4-3)
Dimensions show in millimeters
Data Sheet ADP150
Rev. C | Page 19 of 20
ORDERING GUIDE
Model1 Temperature Range (TJ)
Output
Voltage (V)2 Package Description
Package
Option Branding
ADP150ACBZ-1.8-R7 –40°C to +125°C 1.8 4-Ball Wafer Level Chip Scale Package [WLCSP] CB-4-3 36
ADP150ACBZ-2.5-R7 –40°C to +125°C 2.5 4-Ball Wafer Level Chip Scale Package [WLCSP] CB-4-3 3V
ADP150ACBZ-2.6-R7 –40°C to +125°C 2.6 4-Ball Wafer Level Chip Scale Package [WLCSP] CB-4-3 63
ADP150ACBZ-2.75R7 –40°C to +125°C 2.75 4-Ball Wafer Level Chip Scale Package [WLCSP] CB-4-3 3X
ADP150ACBZ-2.8-R7 –40°C to +125°C 2.8 4-Ball Wafer Level Chip Scale Package [WLCSP] CB-4-3 46
ADP150ACBZ-2.85R7 –40°C to +125°C 2.85 4-Ball Wafer Level Chip Scale Package [WLCSP] CB-4-3 3Y
ADP150ACBZ-3.0-R7 –40°C to +125°C 3.0 4-Ball Wafer Level Chip Scale Package [WLCSP] CB-4-3 47
ADP150ACBZ-3.3-R7 –40°C to +125°C 3.3 4-Ball Wafer Level Chip Scale Package [WLCSP] CB-4-3 48
ADP150AUJZ-1.8-R7 –40°C to +125°C 1.8 5-Lead Thin Small Outline Transistor Package
[TSOT]
UJ-5 LDS
ADP150AUJZ-2.0-R7 –40°C to +125°C 2.0 5-Lead Thin Small Outline Transistor Package
[TSOT]
UJ-5 LT4
ADP150AUJZ-2.5-R7 –40°C to +125°C 2.5 5-Lead Thin Small Outline Transistor Package
[TSOT]
UJ-5 LDZ
ADP150AUJZ-2.65-R7 –40°C to +125°C 2.65 5-Lead Thin Small Outline Transistor Package
[TSOT]
UJ-5 LPE
ADP150AUJZ-2.8-R7 –40°C to +125°C 2.8 5-Lead Thin Small Outline Transistor Package
[TSOT]
UJ-5 LE3
ADP150AUJZ-3.0-R7 –40°C to +125°C 3.0 5-Lead Thin Small Outline Transistor Package
[TSOT]
UJ-5 LE2
ADP150AUJZ-3.3-R7 –40°C to +125°C 3.3 5-Lead Thin Small Outline Transistor Package
[TSOT]
UJ-5 LEJ
ADP150CB-3.3-EVALZ 3.3 Evaluation Board with WLCSP package
ADP150UJZ-REDYKIT Evaluation Board
1 Z = RoHS Compliant Part.
2 Up to 14 fixed output voltage options from 1.8 V to 3.3 V are available. For additional voltage options, contact your local Analog Devices, Inc, sales or distribution
representative.
ADP150 Data Sheet
Rev. C | Page 20 of 20
NOTES
©
2009-2015
Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08343-0-8/15(C)

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