It
This is information on a product in full production.
May 2018 DS10741 Rev 2 1/229
STM32L471xx
Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS,
up to 1MB Flash, 128 KB SRAM, analog, audio
Datasheet - production data
Features
•Ultra-low-power with FlexPowerControl
– 1.71 V to 3.6 V power supply
– -40 °C to 85/105/125 °C temperature range
– 300 nA in VBAT mode: supply for RTC and
32x32-bit backup registers
– 30 nA Shutdown mode (5 wakeup pins)
– 120 nA Standby mode (5 wakeup pins)
– 420 nA Standby mode with RTC
– 1.1 µA Stop 2 mode, 1.4 µA with RTC
– 100 µA/MHz run mode
– Batch acquisition mode (BAM)
– 4 µs wakeup from Stop mode
– Brown out reset (BOR)
– Interconnect matrix
•Core: Arm® 32-bit Cortex®-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait-state execution
from Flash memory, frequency up to 80 MHz,
MPU, 100DMIPS and DSP instructions
•Performance benchmark
– 1.25 DMIPS/MHz (Drystone 2.1)
– 273.55 CoreMark® (3.42 CoreMark/MHz @
80 MHz)
•Energy benchmark
– 294 ULPMark™ CP score
– 106 ULPMark™ PP score
•Clock Sources
– 4 to 48 MHz crystal oscillator
– 32 kHz crystal oscillator for RTC (LSE)
– Internal 16 MHz factory-trimmed RC (±1%)
– Internal low-power 32 kHz RC (±5%)
– Internal multispeed 100 kHz to 48 MHz
oscillator, auto-trimmed by LSE (better than
±0.25 % accuracy)
– 3 PLLs for system clock, audio, ADC
•Up to 114 fast I/Os, most 5 V-tolerant, up to 14
I/Os with independent supply down to 1.08 V
•RTC with HW calendar, alarms and calibration
•Up to 24 capacitive sensing channels: support
touchkey, linear and rotary touch sensors
•16x timers: 2x 16-bit advanced motor-control,
2x 32-bit and 5x 16-bit general purpose, 2x 16-
bit basic, 2x low-power 16-bit timers (available
in Stop mode), 2x watchdogs, SysTick timer
•Memories
– Up to 1 MB Flash, 2 banks read-while-
write, proprietary code readout protection
– Up to 128 KB of SRAM including 32 KB
with hardware parity check
– External memory interface for static
memories supporting SRAM, PSRAM,
NOR and NAND memories
– Quad SPI memory interface
•4x digital filters for sigma delta modulator
•Rich analog peripherals (independent supply)
– 3x 12-bit ADC 5 Msps, up to 16-bit with
hardware oversampling, 200 µA/Msps
– 2x 12-bit DAC output channels, low-power
sample and hold
– 2x operational amplifiers with built-in PGA
– 2x ultra-low-power comparators
•19x communication interfaces
– 2x SAIs (serial audio interface)
–3x I2C FM+(1 Mbit/s), SMBus/PMBus
– 5x USARTs (ISO 7816, LIN, IrDA, modem)
– 1x LPUART (Stop 2 wake-up)
– 3x SPIs (and 1x Quad SPI)
– CAN (2.0B Active) and SDMMC interface
– SWPMI single wire protocol master I/F
UFBGA144 (10 × 10)
LQFP144 (20 × 20)
LQFP100 (14 × 14)
LQFP64 (10 × 10)
UFBGA132 (7 × 7)
www.st.com
STM32L471xx
2/229 DS10741 Rev 2
– IRTIM (Infrared interface)
•14-channel DMA controller
•True random number generator
•CRC calculation unit, 96-bit unique ID
•Development support: serial wire debug
(SWD), JTAG, Embedded Trace Macrocell™
•All packages are ECOPACK2® compliant
Table 1. Device summary
Reference Part numbers
STM32L471xx STM32L471RG, STM32L471VG, STM32L471QG, STM32L471ZG, STM32L471RE,
STM32L471VE, STM32L471QE, STM32L471ZE
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STM32L471xx Contents
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Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 17
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6 Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 20
3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.9.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.9.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.10 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.12 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.13 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.14 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.14.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 38
3.14.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 38
3.15 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.15.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.15.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.15.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.16 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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3.17 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.18 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.19 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.20 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.21 Digital filter for Sigma-Delta Modulators (DFSDM) . . . . . . . . . . . . . . . . . . 43
3.22 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.23 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.23.1 Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.23.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.23.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.23.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 47
3.23.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.23.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.23.7 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.23.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.24 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 49
3.25 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.26 Universal synchronous/asynchronous receiver transmitter (USART) . . . 51
3.27 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 52
3.28 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.29 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.30 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 54
3.31 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.32 Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 55
3.33 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 55
3.34 Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.35 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.35.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.35.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 100
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . 100
6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3.6 Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 148
6.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.3.18 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 149
6.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 162
6.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 167
6.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.3.25 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
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6.3.26 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.3.27 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 178
6.3.28 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
6.3.29 SWPMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
7.1 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
7.2 UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
7.3 UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
7.4 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
7.5 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
7.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
7.6.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
7.6.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 223
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
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STM32L471xx List of tables
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List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. STM32L471xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 18
Table 4. STM32L471xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 6. STM32L471xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 7. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 8. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 9. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 10. DFSDM1 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 11. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 12. I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 13. STM32L471xx USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 14. SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 15. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 16. STM32L471xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 17. Alternate function AF0 to AF7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 18. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 19. STM32L471xx memory map and peripheral register boundary addresses . . . . . . . . . . . . 91
Table 20. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 21. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 22. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 23. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 24. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 25. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 26. Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 27. Current consumption in Run and Low-power run modes, code with data processing
running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 106
Table 28. Current consumption in Run and Low-power run modes, code with data processing
running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 29. Current consumption in Run and Low-power run modes, code with data processing
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 30. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 109
Table 31. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 32. Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 33. Current consumption in Sleep and Low-power sleep modes, Flash ON . . . . . . . . . . . . . 111
Table 34. Current consumption in Low-power sleep modes, Flash in power-down . . . . . . . . . . . . . 112
Table 35. Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 36. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 37. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 38. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 39. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 40. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 41. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 42. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
List of tables STM32L471xx
8/229 DS10741 Rev 2
Table 43. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 44. Wakeup time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 45. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 46. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 47. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 48. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 49. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 50. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Table 51. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 52. PLL, PLLSAI1, PLLSAI2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 53. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 54. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 55. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 56. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 57. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 58. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 59. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 60. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 61. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 62. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 63. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 64. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 65. Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 66. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 67. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 68. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 69. ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 70. ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 71. ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 72. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 73. DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 74. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 75. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 76. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 77. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 78. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 79. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 80. DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 81. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 82. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 83. WWDG min/max timeout value at 80 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 84. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 85. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 86. Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 87. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 88. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 89. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 90. eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 191
Table 92. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 191
Table 93. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 192
Table 94. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 193
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STM32L471xx List of tables
9
Table 95. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 96. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 194
Table 97. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 98. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 196
Table 99. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 100. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 101. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 102. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 103. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 104. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 105. SWPMI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 106. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 107. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 108. UFBGA144 recommended PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . 212
Table 109. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 110. UFBGA132 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 215
Table 111. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 112. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 113. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 114. STM32L471xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 115. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
List of figures STM32L471xx
10/229 DS10741 Rev 2
List of figures
Figure 1. STM32L471xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 3. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 4. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 5. Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 6. STM32L471Zx LQFP144 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 7. STM32L471Zx UFBGA144 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 8. STM32L471Qx UFBGA132 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 9. STM32L471Vx LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 10. STM32L471Rx LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 11. STM32L471xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 12. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 13. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 14. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 15. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 16. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 17. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 18. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 19. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 20. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 21. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 22. Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 23. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 24. I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 25. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 26. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 27. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 28. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 29. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 30. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 31. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 32. Quad SPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 33. Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 34. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 35. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 36. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 37. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 38. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 190
Figure 39. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 192
Figure 40. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 41. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 42. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 43. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 44. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 45. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 46. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 47. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 48. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 204
DS10741 Rev 2 11/229
STM32L471xx List of figures
11
Figure 49. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 205
Figure 50. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 207
Figure 51. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 52. LQFP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 53. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 54. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 55. UFBGA144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 56. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 57. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 58. UFBGA132 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 59. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 217
Figure 60. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 61. LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Figure 62. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 220
Figure 63. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 64. LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 65. LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
arm
Introduction STM32L471xx
12/229 DS10741 Rev 2
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32L471xx microcontrollers.
This document should be read in conjunction with the STM32L4x1 reference manual
(RM0392). The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the Arm®(a) Cortex®-M4 core, please refer to the Cortex®-M4 Technical
Reference Manual, available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS10741 Rev 2 13/229
STM32L471xx Description
58
2 Description
The STM32L471xx devices are the ultra-low-power microcontrollers based on the high-
performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz.
The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all
Arm® single-precision data-processing instructions and data types. It also implements a full
set of DSP instructions and a memory protection unit (MPU) which enhances application
security.
The STM32L471xx devices embed high-speed memories (Flash memory up to 1 Mbyte, up
to 128 Kbyte of SRAM), a flexible external memory controller (FSMC) for static memories
(for devices with packages of 100 pins and more), a Quad SPI flash memories interface
(available on all packages) and an extensive range of enhanced I/Os and peripherals
connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
The STM32L471xx devices embed several protection mechanisms for embedded Flash
memory and SRAM: readout protection, write protection, proprietary code readout
protection and Firewall.
The devices offer up to three fast 12-bit ADCs (5 Msps), two comparators, two operational
amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, two
general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control, seven
general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support four
digital filters for external sigma delta modulators (DFSDM).
In addition, up to 24 capacitive sensing channels are available.
They also feature standard and advanced communication interfaces.
•Three I2Cs
•Three SPIs
•Three USARTs, two UARTs and one Low-Power UART.
•Two SAIs (Serial Audio Interfaces)
•One SDMMC
•One CAN
•One SWPMI (Single Wire Protocol Master Interface)
The STM32L471xx operates in the -40 to +85 °C (+105 °C junction), -40 to +105 °C
(+125 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to
3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-
power applications.
Some independent power supplies are supported: analog independent supply input for
ADC, DAC, OPAMPs and comparators, and up to 14 I/Os can be supplied independently
down to 1.08V. A VBAT input allows to backup the RTC and backup registers.
The STM32L471xx family offers four packages from 64-pin to 144-pin packages.
Description STM32L471xx
14/229 DS10741 Rev 2
Table 2. STM32L471xx family device features and peripheral counts
Peripheral STM32L471Zx STM32L471Qx STM32L471Vx STM32L471Rx
Flash memory 512KB 1MB 512KB 1MB 512KB 1MB 512KB 1MB
SRAM 128KB
External memory controller
for static memories Yes Yes Yes (1) No
Quad SPI Yes
Timers
Advanced
control 2 (16-bit)
General
purpose
5 (16-bit)
2 (32-bit)
Basic 2 (16-bit)
Low -power 2 (16-bit)
SysTick timer 1
Watchdog
timers
(independent,
window)
2
Comm.
interfaces
SPI 3
I2C3
USART
UART
LPUART
3
2
1
SAI 2
CAN 1
SDMMC Yes
SWPMI Yes
Digital filters for sigma-
delta modulators Yes (4 filters)
Number of channels 8
RTC Yes
Tamper pins 3
2
Random generator Yes
GPIOs
Wakeup pins
Nb of I/Os down to 1.08 V
114
5
14
109
5
14
82
5
0
51
4
0
Capacitive sensing
Number of channels 24 24 21 12
12-bit ADCs
Number of channels
3
24
3
19
3
16
3
16
DS10741 Rev 2 15/229
STM32L471xx Description
58
12-bit DAC channels 2
Internal voltage reference
buffer Yes No
Analog comparator 2
Operational amplifiers 2
Max. CPU frequency 80 MHz
Operating voltage 1.71 to 3.6 V
Operating temperature
Ambient operating temperature: -40 to 85 °C / -40 to 105 °C / -40 to
125 °C
Junction temperature: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C
Packages LQFP144
UFBGA144 UFBGA132 LQFP100 LQFP64
1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed
NOR/PSRAM memory using the NE1 Chip Select.
Table 2. STM32L471xx family device features and peripheral counts (continued)
Peripheral STM32L471Zx STM32L471Qx STM32L471Vx STM32L471Rx
Description STM32L471xx
16/229 DS10741 Rev 2
Figure 1. STM32L471xx block diagram
Note: AF: alternate function on I/O pins.
MSv36837V4
Flash
up to
1 MB
Flexible static memory controller (FSMC):
SRAM, PSRAM, NOR Flash,
NAND Flash
GPIO PORT A
AHB/APB2
EXT IT. WKUP
114 AF
PA[15:0]
TIM1 / PWM
3 compl. channels (TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]),
ETR, BKIN, BKIN2 as AF
USART1
RX, TX, CK,CTS,
RTS as AF
SPI1
MOSI, MISO,
SCK, NSS as AF
APB260 M Hz
APB1 30MHz
OUT1
ITF
WWDG
RTC_TS
OSC32_IN
OSC32_OUT
smcard
IrDA
16b
SDIO / MMC
D[7:0]
CMD, CK as AF
VBAT = 1.55 to 3.6 V
JTAG & SW
ARM Cortex-M4
80 MHz
FPU
NVIC
ETM
MPU
DMA2
ART
ACCEL/
CACHE
CLK, NE[4:1], NL, NBL[1:0],
A[25:0], D[15:0], NOE, NWE,
NWAIT, NCE3, INT3 as AF
RNG
FIFO
@ VDDA
BOR
Supply
supervision
PVD, PVM
Int
reset
XTAL 32 kHz
MAN AGT
RTC
FCLK
Standby
interface
IWDG
@VBAT
@ VDD
@VDD
AWU
Reset & clock
control
PCLKx
Voltage
regulator
3.3 to 1.2 V
VDD Power management
@ VDD
RTC_TAMPx
Backup register
AHB bus-matrix
TIM15
2 channels,
1 compl. channel, BKIN as AF
DAC1
DAC2
TIM6
TIM7
D-BUS
APB1 80 MHz (max)
SRAM 96 KB
SRAM 32 KB
I-BUS
S-BUS
DMA1
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
PF[15:0]
PG[15:0]
PH[1:0]
GPIO PORT B
GPIO PORT C
GPIO PORT D
GPIO PORT E
GPIO PORT F
GPIO PORT G
GPIO PORT H
TIM8 / PWM 16b
16b
TIM16 16b
TIM17 16b
3 compl. channels (TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]),
ETR, BKIN, BKIN2 as AF
1 channel,
1 compl. channel, BKIN as AF
1 channel,
1 compl. channel, BKIN as AF
OUT2
16b
16b
AHB/APB1
OSC_IN
OSC_OUT
HCLKx
XTAL OSC
4- 16MHz
8 analog inputs common
to the 3 ADCs
VREF+
USAR T 2MBps
Temperature sensor
ADC1
ADC2
ADC3
IF
ITF
@ VDDA
8 analog inputs common
to the ADC1 & 2
8 analog inputs for ADC3
SAI1
MCLK_A, SD_A, FS_A, SCK_A, EXTCLK
MCLK_B, SD_B, FS_B, SCK_B as AF
SAI2
MCLK_A, SD_A, FS_A, SCK_A, EXTCLK
MCLK_B, SD_B, FS_B, SCK_B as AF
DFSDM
SDCKIN[7:0], SDDATIN[7:0],
SDCKOUT,SDTRIG as AF
Touch sensing controller
8 Groups of
3 channels max as AF RC HSI
RC LSI
PLL 1&2&3
MSI
Quad SPI memory interface
BK1_IO[3:0]
CLK
NCS
COMP1
INP, INM, OUT
COMP2
INP, INM, OUT
@ VDDA
RTC_OUT
AHB1 80 MHz
CRC
APB2 80MHz
AHB2 80 MHz
Firewall
VREF Buffer
@ VDDA
@ VDD
VDD = 1.71 to 3.6 V
VSS
VDDA, VSSA
VDD, VSS, NRST
VDDIO2
TRACECLK
TRACED[3:0]
NJTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
TIM2 32b 4 channels, ETR as AF
TIM3 16b 4 channels, ETR as AF
TIM4 16b 4 channels, ETR as AF
TIM5 32b 4 channels, ETR as AF
USART2 RX, TX, CK, CTS, RTS as AF
smcard
IrDA
USART3 RX, TX, CK, CTS, RTS as AF
smcard
IrDA
RX, TX, CTS, RTS as AF
UART4
RX, TX, CTS, RTS as AF
UART5
MOSI, MISO, SCK, NSS as AF
SP2
MOSI, MISO, SCK, NSS as AF
SP3
I2C1/SMBUS SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
I2C2/SMBUS
SCL, SDA, SMBA as AF
I2C3/SMBUS
FIFO
TX, RX as AF
bxCAN1
VOUT, VINM, VINP
OpAmp1
OpAmp2
@VDDA
VOUT, VINM, VINP
LPUART1 RX, TX, CTS, RTS as AF
SWPMI1 IO
RX, TX, SUSPEND as AF
LPTIM1 IN1, IN2, OUT, ETR as AF
LPTIM2 IN1, OUT, ETR as AF
DS10741 Rev 2 17/229
STM32L471xx Functional overview
58
3 Functional overview
3.1 Arm® Cortex®-M4 core with FPU
The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional code-
efficiency, delivering the high-performance expected from an Arm® core in the memory size
usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
With its embedded Arm® core, the STM32L471xx family is compatible with all Arm® tools
and software.
Figure 1 shows the general block diagram of the STM32L471xx family devices.
3.2 Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-
standard Arm® Cortex®-M4 processors. It balances the inherent performance advantage of
the Arm® Cortex®-M4 over Flash memory technologies, which normally requires the
processor to wait for the Flash memory at higher frequencies.
To release the processor near 100 DMIPS performance at 80MHz, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 80 MHz.
3.3 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
Functional overview STM32L471xx
18/229 DS10741 Rev 2
3.4 Embedded Flash memory
STM32L471xx devices feature up to 1 Mbyte of embedded Flash memory available for
storing programs and data. The Flash memory is divided into two banks allowing read-
while-write operations. This feature allows to perform a read operation from one bank while
an erase or program operation is performed to the other bank. The dual bank boot is also
supported. Each bank contains 256 pages of 2 Kbyte.
Flexible protections can be configured thanks to option bytes:
•Readout protection (RDP) to protect the whole memory. Three levels are available:
– Level 0: no readout protection
– Level 1: memory readout protection: the Flash memory cannot be read from or
written to if either debug features are connected, boot in RAM or bootloader is
selected
– Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial
wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This
selection is irreversible.
•Write protection (WRP): the protected area is protected against erasing and
programming. Two areas per bank can be selected, with 2-Kbyte granularity.
•Proprietary code readout protection (PCROP): a part of the flash memory can be
protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU, as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.
One area per bank can be selected, with 64-bit granularity. An additional option bit
(PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP
protection is changed from Level 1 to Level 0.
Table 3. Access status versus readout protection level and execution modes
Area Protection
level
User execution Debug, boot from RAM or boot
from system memory (loader)
Read Write Erase Read Write Erase
Main
memory
1 Yes Yes Yes No No No
2 Yes Yes Yes N/A N/A N/A
System
memory
1 Yes No No Yes No No
2 Yes No No N/A N/A N/A
Option
bytes
1 Yes Yes Yes Yes Yes Yes
2 Yes No No N/A N/A N/A
Backup
registers
1YesYesN/A
(1)
1. Erased when RDP change from Level 1 to Level 0.
No No N/A(1)
2 Yes Yes N/A N/A N/A N/A
SRAM2
1 Yes Yes Yes(1) No No No(1)
2 Yes Yes Yes N/A N/A N/A
DS10741 Rev 2 19/229
STM32L471xx Functional overview
58
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
•single error detection and correction
•double error detection.
•The address of the ECC fail can be read in the ECC register
3.5 Embedded SRAM
STM32L471xx devices feature up to 128 Kbyte of embedded SRAM. This SRAM is split into
two blocks:
•96 Kbyte mapped at address 0x2000 0000 (SRAM1)
•32 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).
This block is accessed through the ICode/DCode buses for maximum performance.
These 32 Kbyte SRAM can also be retained in Standby mode.
The SRAM2 can be write-protected with 1 Kbyte granularity.
The memory can be accessed in read/write at CPU clock speed with 0 wait states.
3.6 Firewall
The device embeds a Firewall which protects code sensitive and secure data from any
access performed by a code executed outside of the protected areas.
Each illegal access generates a reset which kills immediately the detected intrusion.
The Firewall main features are the following:
•Three segments can be protected and defined thanks to the Firewall registers:
– Code segment (located in Flash or SRAM1 if defined as executable protected
area)
– Non-volatile data segment (located in Flash)
– Volatile data segment (located in SRAM1)
•The start address and the length of each segments are configurable:
– Code segment: up to 1024 Kbyte with granularity of 256 bytes
– Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes
– Volatile data segment: up to 96 Kbyte with a granularity of 64 bytes
•Specific mechanism implemented to open the Firewall to get access to the protected
areas (call gate entry sequence)
•Volatile data segment can be shared or not with the non-protected code
•Volatile data segment can be executed or not depending on the Firewall configuration
The Flash readout protection must be set to level 2 in order to reach the expected level of
protection.
Functional overview STM32L471xx
20/229 DS10741 Rev 2
3.7 Boot modes
At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:
•Boot from user Flash
•Boot from system memory
•Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART, I2C, SPI or CAN.
3.8 Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.9 Power supply management
3.9.1 Power supply schemes
•VDD = 1.71 to 3.6 V: external power supply for I/Os (VDDIO1), the internal regulator and
the system analog such as reset, power management and internal clocks. It is provided
externally through VDD pins.
•VDDA = 1.62 V (ADCs/COMPs) / 1.8 (DAC/OPAMPs) to 3.6 V: external analog power
supply for ADCs, DAC, OPAMPs, Comparators and Voltage reference buffer. The VDDA
voltage level is independent from the VDD voltage.
•VDDIO2 = 1.08 to 3.6 V: external power supply for 14 I/Os (PG[15:2]). The VDDIO2
voltage level is independent from the VDD voltage.
•VBAT = 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Note: When the functions supplied by VDDA or VDDIO2 are not used, these supplies should
preferably be shorted to VDD.
Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V
tolerant (refer to Table 20: Voltage characteristics).
Note: VDDIOx is the I/Os general purpose digital functions supply. VDDIOx represents VDDIO1 or
VDDIO2, with VDDIO1 = VDD. VDDIO2 supply voltage level is independent from VDDIO1.
DS10741 Rev 2 21/229
STM32L471xx Functional overview
58
Figure 2. Power supply overview
During power-up and power-down phases, the following power sequence requirements
must be respected:
•When VDD is below 1 V, other power supplies (VDDA, VDDIO2) must remain below VDD +
300 mV.
•When VDD is above 1 V, all power supplies are independent.
During the power-down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the MCU remains below 1 mJ; this allows external decoupling
capacitors to be discharged with different time constants during the power-down transient
phase.
MSv36858V1
VDDA domain
Backup domain
2 x D/A converters
3 x A/D converters
Standby circuitry
(Wakeup logic,
IWDG)
Voltage regulator
Core
SRAM1
SRAM2
Digital
peripherals
Low voltage detector
LSE crystal 32 K osc
BKP registers
RCC BDCR register
RTC
2 x comparators
2 x operational amplifiers
Voltage reference buffer
I/O ring
VCORE domain
Temp. sensor
Reset block
3 x PLL, HSI, MSI
Flash memory
VDDIO2
VDDIO1
I/O ring
PG[15:2]
VDDIO2
VDDA
VSSA
VSS
VDDIO2 domain
VDD domain
VCORE
VSS
VDD
VBAT
,,,,,,,4, , ,,,,,,,,,,,,,,,,,,,,,,,,,
Functional overview STM32L471xx
22/229 DS10741 Rev 2
Figure 3. Power-up/down sequence
1. VDDX refers to any power supply among VDDA, VDDIO2.
3.9.2 Power supply supervisor
The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes
except Shutdown and ensuring proper operation after power-on and during power down.
The device remains in reset mode when the monitored supply voltage VDD is below a
specified threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected
through option bytes.The device features an embedded programmable voltage detector
(PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An
interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the device embeds a Peripheral Voltage Monitor which compares the
independent supply voltages VDDA, VDDIO2 with a fixed threshold in order to ensure that the
peripheral is in its functional supply range.
MSv47490V1
0.3
1
VBOR0
3.6
Operating modePower-on Power-down time
V
VDDX(1)
VDD
Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
DS10741 Rev 2 23/229
STM32L471xx Functional overview
58
3.9.3 Voltage regulator
Two embedded linear voltage regulators supply most of the digital circuitries: the main
regulator (MR) and the low-power regulator (LPR).
•The MR is used in the Run and Sleep modes and in the Stop 0 mode.
•The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is
also used to supply the 32 Kbyte SRAM2 in Standby with SRAM2 retention.
•Both regulators are in power-down in Standby and Shutdown modes: the regulator
output is in high impedance, and the kernel circuitry is powered down thus inducing
zero consumption.
The ultralow-power STM32L471xx supports dynamic voltage scaling to optimize its power
consumption in run mode. The voltage from the Main Regulator that supplies the logic
(VCORE) can be adjusted according to the system’s maximum operating frequency.
There are two power consumption ranges:
•Range 1 with the CPU running at up to 80 MHz.
•Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also
limited to 26 MHz.
The VCORE can be supplied by the low-power regulator, the main regulator being switched
off. The system is then in Low-power run mode.
•Low-power run mode with the CPU running at up to 2 MHz. Peripherals with
independent clock can be clocked by HSI16.
3.9.4 Low-power modes
The ultra-low-power STM32L471xx supports seven low-power modes to achieve the best
compromise between low-power consumption, short startup time, available peripherals and
available wakeup sources.
Functional overview STM32L471xx
24/229 DS10741 Rev 2
Table 4. STM32L471xx modes overview
Mode Regulator
(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time
Run
Range 1
Yes ON(4) ON Any
All
N/A
112 µA/MHz
N/A
Range2 All except RNG 100 µA/MHz
LPRun LPR Yes ON(4) ON
Any
except
PLL
All except RNG N/A 136 µA/MHz to Range 1: 4 µs
to Range 2: 64 µs
Sleep
Range 1
No ON(4) ON(5) Any
All Any interrupt or
event
37 µA/MHz 6 cycles
Range 2 All except RNG 35 µA/MHz 6 cycles
LPSleep LPR No ON(4) ON(5)
Any
except
PLL
All except RNG Any interrupt or
event 40 µA/MHz 6 cycles
Stop 0
Range 1
No Off ON LSE
LSI
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1,2)
DAC1
OPAMPx (x=1,2)
USARTx (x=1...5)(6)
LPUART1(6)
I2Cx (x=1...3)(7)
LPTIMx (x=1,2)
***
All other peripherals are
frozen.
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
USARTx (x=1...5)(6)
LPUART1(6)
I2Cx (x=1...3)(7)
LPTIMx (x=1,2)
SWPMI1(8)
108 µA 0.7 µs in SRAM
4.5 µs in Flash
Range 2
STM32L471xx Functional overview
DS10741 Rev 2 25/229
Stop 1 LPR No Off ON LSE
LSI
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1,2)
DAC1
OPAMPx (x=1,2)
USARTx (x=1...5)(6)
LPUART1(6)
I2Cx (x=1...3)(7)
LPTIMx (x=1,2)
***
All other peripherals are
frozen.
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
USARTx (x=1...5)(6)
LPUART1(6)
I2Cx (x=1...3)(7)
LPTIMx (x=1,2)
SWPMI1(8)
6.6 µA w/o RTC
6.9 µA w RTC
4 µs in SRAM
6 µs in Flash
Stop 2 LPR No Off ON LSE
LSI
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
I2C3(7)
LPUART1(6)
LPTIM1
***
All other peripherals are
frozen.
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
I2C3(7)
LPUART1(6)
LPTIM1
1.1 µA w/o RTC
1.4 µA w/RTC
5 µs in SRAM
7 µs in Flash
Table 4. STM32L471xx modes overview (continued)
Mode Regulator
(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time
Functional overview STM32L471xx
26/229 DS10741 Rev 2
Standby
LPR
Powered
Off Off
SRAM2
ON
LSE
LSI
BOR, RTC, IWDG
***
All other peripherals are
powered off.
***
I/O configuration can be
floating, pull-up or pull-down
Reset pin
5 I/Os (WKUPx)(9)
BOR, RTC, IWDG
0.35 µA w/o RTC
0.65 µA w/ RTC
14 µs
OFF Powered
Off
0.12 µA w/o RTC
0.42 µA w/ RTC
Shutdown OFF Powered
Off Off Powered
Off LSE
RTC
***
All other peripherals are
powered off.
***
I/O configuration can be
floating, pull-up or pull-
down(10)
Reset pin
5 I/Os (WKUPx)(9)
RTC
0.03 µA w/o RTC
0.33 µA w/ RTC 256 µs
1. LPR means Main regulator is OFF and Low-power regulator is ON.
2. All peripherals can be active or clock gated to save power consumption.
3. Typical current at VDD = 1.8 V, 25°C. Consumptions values provided running from SRAM, Flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in
LPRun/LPSleep.
4. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.
5. The SRAM1 and SRAM2 clocks can be gated on or off independently.
6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. SWPMI1 wakeup by resume from suspend.
9. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.
Table 4. STM32L471xx modes overview (continued)
Mode Regulator
(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time
DS10741 Rev 2 27/229
STM32L471xx Functional overview
58
By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the
user to select one of the low-power modes described below:
•Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•Low-power run mode
This mode is achieved with VCORE supplied by the low-power regulator to minimize the
regulator's operating current. The code can be executed from SRAM or from Flash,
and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can
be clocked by HSI16.
•Low-power sleep mode
This mode is entered from the low-power run mode. Only the CPU clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the low-
power run mode.
•Stop 0, Stop 1 and Stop 2 modes
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI
RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still
running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode
to detect their wakeup condition.
Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,
most of the VCORE domain is put in a lower leakage mode.
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator
remains ON, allowing a very fast wakeup time but with much higher consumption.
The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI
up to 48 MHz or HSI16, depending on software configuration.
•Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off. The PLL, the
MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The brown-out reset (BOR) always remains active in Standby mode.
The state of each I/O during standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAM1 and register contents are lost except for registers
in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in
Standby mode, supplied by the low-power Regulator (Standby with SRAM2 retention
mode).
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,
periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).
The system clock after wakeup is MSI up to 8 MHz.
Functional overview STM32L471xx
28/229 DS10741 Rev 2
•Shutdown mode
The Shutdown mode allows to achieve the lowest power consumption. The internal
regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16,
the MSI, the LSI and the HSE oscillators are also switched off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported.
SRAM1, SRAM2 and register contents are lost except for registers in the Backup
domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wakeup, timestamp, tamper).
The system clock after wakeup is MSI at 4 MHz.
DS10741 Rev 2 29/229
STM32L471xx Functional overview
58
Table 5. Functionalities depending on the working mode(1)
Peripheral Run Sleep
Low-
power
run
Low-
power
sleep
Stop 0/1 Stop 2 Standby Shutdown
VBAT
-
Wakeup capability
-
Wakeup capability
-
Wakeup capability
-
Wakeup capability
CPU Y - Y - - --------
Flash memory (up to
1 MB) O(2) O(2) O(2) O(2) ---------
SRAM1 (up to
96 KB) YY
(3) YY
(3) Y-Y------
SRAM2 (32 KB) Y Y(3) YY
(3) Y-Y-O
(4) ----
FSMC OOOO-
--------
Quad SPI O O O O - --------
Backup Registers Y Y Y Y Y -Y-Y-Y-Y
Brown-out reset
(BOR) YYYYY
YYYYY- --
Programmable
Voltage Detector
(PVD)
OOOOOOOO- ----
Peripheral Voltage
Monitor (PVMx;
x=1,2,3,4)
OOOOO
OOO- ----
DMA OOOO-
--------
High Speed Internal
(HSI16) OOOO
(5) -(5) ------
High Speed External
(HSE) OOOO-
--------
Low Speed Internal
(LSI) OOOOO
-O-O----
Low Speed External
(LSE) OOOOO
-O-O-O-O
Multi-Speed Internal
(MSI) OOOO-
--------
Clock Security
System (CSS) OOOO-
--------
Clock Security
System on LSE OOOOO
OOOOO- --
RTC / Auto wakeup O O O O O OOOOOOOO
Number of RTC
Tamper pins 33333
O3O3O3O3
Functional overview STM32L471xx
30/229 DS10741 Rev 2
USARTx
(x=1,2,3,4,5) OOOOO
(6) O(6) -------
Low-power UART
(LPUART) OOOOO
(6) O(6) O(6) O(6) -----
I2Cx (x=1,2) O O O O O(7) O(7) -------
I2C3 OOOOO
(7) O(7) O(7) O(7) -----
SPIx (x=1,2,3) O O O O - --------
CAN OOOO-
--------
SDMMC1 O O O O - --------
SWPMI1 OOOO-
O- ------
SAIx (x=1,2) O O O O - --------
DFSDM1 OOOO-
--------
ADCx (x=1,2,3) O O O O - --------
DAC1 O O O O O --------
VREFBUF O O O O O --------
OPAMPx (x=1,2) O O O O O --------
COMPx (x=1,2) O O O O O OOO- ----
Temperature sensor O O O O - --------
Timers (TIMx) O O O O - --------
Low-power timer 1
(LPTIM1) OOOOO
OOO- ----
Low-power timer 2
(LPTIM2) OOOOO
O- ------
Independent
watchdog (IWDG) OOOOO
OOOOO- --
Window watchdog
(WWDG) OOOO-
--------
SysTick timer O O O O - --------
Touch sensing
controller (TSC) OOOO-
--------
Random number
generator (RNG) O(8) O(8) -----------
Table 5. Functionalities depending on the working mode(1) (continued)
Peripheral Run Sleep
Low-
power
run
Low-
power
sleep
Stop 0/1 Stop 2 Standby Shutdown
VBAT
-
Wakeup capability
-
Wakeup capability
-
Wakeup capability
-
Wakeup capability
DS10741 Rev 2 31/229
STM32L471xx Functional overview
58
3.9.5 Reset mode
In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
3.9.6 VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when no external battery and an external supercapacitor are
present. The VBAT pin supplies the RTC with LSE and the backup registers. Three anti-
tamper detection pins are available in VBAT mode.
VBAT operation is automatically activated when VDD is not present.
An internal VBAT battery charging circuit is embedded and can be activated when VDD is
present.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
CRC calculation unit O O O O - --------
GPIOs OOOOO
OOO(9)
5
pins
(10)
(11)
5
pins
(10)
-
1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available.
2. The Flash can be configured in power-down mode. By default, it is not in power-down mode.
3. The SRAM clock can be gated on or off.
4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.
5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or
received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. Voltage scaling Range 1 only.
9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
Table 5. Functionalities depending on the working mode(1) (continued)
Peripheral Run Sleep
Low-
power
run
Low-
power
sleep
Stop 0/1 Stop 2 Standby Shutdown
VBAT
-
Wakeup capability
-
Wakeup capability
-
Wakeup capability
-
Wakeup capability
Functional overview STM32L471xx
32/229 DS10741 Rev 2
3.10 Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run
and sleep, Stop 0, Stop 1 and Stop 2 modes.
Table 6. STM32L471xx peripherals interconnect matrix
Interconnect source Interconnect
destination Interconnect action
Run
Sleep
Low-power run
Low-power sleep
Stop 0 / Stop 1
Stop 2
TIMx
TIMx Timers synchronization or chaining Y Y Y Y - -
ADCx
DAC1
DFSDM1
Conversion triggers Y Y Y Y - -
DMA Memory to memory transfer trigger Y Y Y Y - -
COMPx Comparator output blanking Y Y Y Y - -
TIM16/TIM17 IRTIM Infrared interface output generation Y Y Y Y - -
COMPx
TIM1, 8
TIM2, 3
Timer input channel, trigger, break from
analog signals comparison YYYY - -
LPTIMERx Low-power timer triggered by analog
signals comparison YYYYYY
(1)
ADCx TIM1, 8 Timer triggered by analog watchdog Y Y Y Y - -
RTC
TIM16 Timer input channel from RTC events Y Y Y Y - -
LPTIMERx Low-power timer triggered by RTC alarms
or tampers YYYYYY
(1)
All clocks sources (internal
and external)
TIM2
TIM15, 16, 17
Clock source used as input channel for
RC measurement and trimming YYYY - -
CSS
CPU (hard fault)
RAM (parity error)
Flash memory (ECC error)
COMPx
PVD
DFSDM1 (analog
watchdog, short circuit
detection)
TIM1,8
TIM15,16,17 Timer break Y Y Y Y - -
DS10741 Rev 2 33/229
STM32L471xx Functional overview
58
GPIO
TIMx External trigger Y Y Y Y - -
LPTIMERx External trigger Y Y Y Y Y Y
(1)
ADCx
DAC1
DFSDM1
Conversion external trigger Y Y Y Y - -
1. LPTIM1 only.
Table 6. STM32L471xx peripherals interconnect matrix (continued)
Interconnect source Interconnect
destination Interconnect action
Run
Sleep
Low-power run
Low-power sleep
Stop 0 / Stop 1
Stop 2
Functional overview STM32L471xx
34/229 DS10741 Rev 2
3.11 Clocks and startup
The clock controller (see Figure 4) distributes the clocks coming from different oscillators to
the core and the peripherals. It also manages clock gating for low-power modes and
ensures clock robustness. It features:
•Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
•Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
•Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
•System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
– 4-48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply
a PLL. The HSE can also be configured in bypass mode for an external clock.
– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can
supply a PLL
– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate
12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL.
– System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency
at 80 MHz.
•Auxiliary clock source: two ultralow-power clock sources that can be used to drive
the real-time clock:
– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
– 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock accuracy is ±5% accuracy.
•Peripheral clock sources: Several peripherals (SDMMC, RNG, SAI, USARTs, I2Cs,
LPTimers, ADC, SWPMI) have their own independent clock whatever the system clock.
Three PLLs, each having three independent outputs allowing the highest flexibility, can
generate independent clocks for the ADC, the SDMMC/RNG and the two SAIs.
•Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
•Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI16 and a software
interrupt is generated if enabled. LSE failure can also be detected and generated an
interrupt.
•Clock-out capability:
–MCO: microcontroller clock output: it outputs one of the internal clocks for
external use by the application. Low frequency clocks (LSI, LSE) are available
down to Stop 1 low power state.
–LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes
down to Standby mode. LSE can also be output on LSCO in Shutdown mode.
LSCO is not available in VBAT mode.
mg
m
Msu
use
svscLK
m m
mom
svscLK
Functional overview STM32L471xx
36/229 DS10741 Rev 2
Figure 4. Clock tree
MSv36859V3
PLLCLK
SYSCLK
MCO
LSCO
SAI2_EXTCLK
48 MHz clock to RNG, SDMMC
to ADC
to IWDG
to RTC
to PWR
HCLK
to AHB bus, core, memory and DMA
FCLK Cortex free running clock
to Cortex system timer
to APB1 peripherals
to APB2 peripherals
PCLK1
PCLK2
to SAI1
to SAI2
LSE
HSI16
SYSCLK to USARTx
x=2..5
to LPUART1
to I2Cx
x=1,2,3
to LPTIMx
x=1,2
SAI1_EXTCLK
to SWPMI
to TIMx
x=2..7
OSC32_OUT
OSC32_IN
MSI HSI16
HSE
HSI16
LSI
LSE
HSE
SYSCLK
HSE
MSI
HSI16
MSI
SYSCLK
LSE OSC
32.768 kHz /32
AHB PRESC
/ 1,2,..512
/ 8
APB1 PRESC
/ 1,2,4,8,16
x1 or x2
HSI16
SYSCLK
LSI
LSE
HSI16
HSI16
APB2 PRESC
/ 1,2,4,8,16
to TIMx
x=1,8,15,16,17
x1 or x2
to
USART1
LSE
HSI16
SYSCLK
/ M
MSI RC
100 kHz – 48 MHz
HSI RC
16 MHz
HSE OSC
4-48 MHz
Clock
detector
OSC_OUT
OSC_IN
/ 1→16
LSI RC 32 kHz
Clock
source
control
PLLSAI3CLK
PLL48M1CLK
PLLCLK
PLLSAI1CLK
PLL48M2CLK
PLLADC1CLK
PLLSAI2CLK
PLLADC2CLK
MSI
PLLSAI1
VCO F
VCO
/ P
/ R
/ Q
PLLSAI2
VCO F
VCO
/ P
/ R
/ Q
PLL
VCO F
VCO
/ P
/ R
/ Q
DS10741 Rev 2 37/229
STM32L471xx Functional overview
58
3.12 General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
3.13 Direct memory access controller (DMA)
The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features
implementation.
Direct memory access (DMA) is used in order to provide high-speed data transfer between
peripherals and memory as well as memory to memory. Data can be quickly moved by DMA
without any CPU actions. This keeps CPU resources free for other operations.
The two DMA controllers have 14 channels in total, each dedicated to managing memory
access requests from one or more peripherals. Each has an arbiter for handling the priority
between DMA requests.
The DMA supports:
•14 independently configurable channels (requests)
•Each channel is connected to dedicated hardware DMA requests, software trigger is
also supported on each channel. This configuration is done by software.
•Priorities between requests from channels of one DMA are software programmable (4
levels consisting of very high, high, medium, low) or hardware in case of equality
(request 1 has priority over request 2, etc.)
•Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data
size.
•Support for circular buffer management
•3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)
logically ORed together in a single interrupt request for each channel
•Memory-to-memory transfer
•Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral
transfers
•Access to Flash, SRAM, APB and AHB peripherals as source and destination
•Programmable number of data to be transferred: up to 65536.
Table 7. DMA implementation
DMA features DMA1 DMA2
Number of regular channels 7 7
Functional overview STM32L471xx
38/229 DS10741 Rev 2
3.14 Interrupts and events
3.14.1 Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-
M4.
The NVIC benefits are the following:
•Closely coupled NVIC gives low latency interrupt processing
•Interrupt entry vector table address passed directly to the core
•Allows early processing of interrupts
•Processing of late arriving higher priority interrupts
•Support for tail chaining
•Processor state automatically saved on interrupt entry, and restored on interrupt exit,
with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.14.2 Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 36 edge detector lines used to generate
interrupt/event requests and wake-up the system from Stop mode. Each external line can be
independently configured to select the trigger event (rising edge, falling edge, both) and can
be masked independently. A pending register maintains the status of the interrupt requests.
The internal lines are connected to peripherals with wakeup from Stop mode capability. The
EXTI can detect an external line with a pulse width shorter than the internal clock period. Up
to 114 GPIOs can be connected to the 16 external interrupt lines.
DS10741 Rev 2 39/229
STM32L471xx Functional overview
58
3.15 Analog to digital converter (ADC)
The device embeds 3 successive approximation analog-to-digital converters with the
following features:
•12-bit native resolution, with built-in calibration
•5.33 Msps maximum conversion rate with full resolution
– Down to 18.75 ns sampling time
– Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit
resolution)
•Up to 24 external channels, some of them shared between ADC1 and ADC2, or ADC1,
ADC2 and ADC3.
•5 internal channels: internal reference voltage, temperature sensor, VBAT/3,
DAC1_OUT1 and DAC1_OUT2.
•One external reference pin is available on some package, allowing the input voltage
range to be independent from the power supply
•Single-ended and differential mode inputs
•Low-power design
– Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
– Dual clock domain architecture: ADC speed independent from CPU frequency
•Highly versatile digital interface
– Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
– Handles two ADC converters for dual mode operation (simultaneous or
interleaved sampling modes)
– Each ADC support multiple trigger inputs for synchronization with on-chip timers
and external signals
– Results stored into 3 data register or in RAM with DMA controller support
– Data pre-processing: left/right alignment and per channel offset compensation
– Built-in oversampling unit for enhanced SNR
– Channel-wise programmable sampling time
– Three analog watchdog for automatic voltage monitoring, generating interrupts
and trigger for selected timers
– Hardware assistant to prepare the context of the injected channels to allow fast
context switching
3.15.1 Temperature sensor
The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to the ADC1_IN17 and ADC3_IN17 input
channels which is used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
Functional overview STM32L471xx
40/229 DS10741 Rev 2
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
3.15.2 Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and Comparators. VREFINT is internally connected to the ADC1_IN0 input
channel. The precise voltage of VREFINT is individually measured for each part by ST
during production test and stored in the system memory area. It is accessible in read-only
mode.
3.15.3 VBAT battery voltage monitoring
This embedded hardware feature allows the application to measure the VBAT battery voltage
using the internal ADC channel ADC1_IN18 or ADC3_IN18. As the VBAT voltage may be
higher than VDDA, and thus outside the ADC input range, the VBAT pin is internally
connected to a bridge divider by 3. As a consequence, the converted digital value is one
third the VBAT voltage.
3.16 Digital to analog converter (DAC)
Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage
signal outputs. The chosen design structure is composed of integrated resistor strings and
an amplifier in inverting configuration.
Table 8. Temperature sensor calibration values
Calibration value name Description Memory address
TS_CAL1
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
0x1FFF 75A8 - 0x1FFF 75A9
TS_CAL2
TS ADC raw data acquired at a
temperature of 110 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
0x1FFF 75CA - 0x1FFF 75CB
Table 9. Internal voltage reference calibration values
Calibration value name Description Memory address
VREFINT
Raw data acquired at a
temperature of 30 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
0x1FFF 75AA - 0x1FFF 75AB
DS10741 Rev 2 41/229
STM32L471xx Functional overview
58
This digital interface supports the following features:
•Up to two DAC output channels
•8-bit or 12-bit output mode
•Buffer offset calibration (factory and user trimming)
•Left or right data alignment in 12-bit mode
•Synchronized update capability
•Noise-wave generation
•Triangular-wave generation
•Dual DAC channel independent or simultaneous conversions
•DMA capability for each channel
•External triggers for conversion
•Sample and hold low-power mode, with internal or external capacitor
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA channels.
3.17 Voltage reference buffer (VREFBUF)
The STM32L471xx devices embed an voltage reference buffer which can be used as
voltage reference for ADCs, DAC and also as voltage reference for external components
through the VREF+ pin.
The internal voltage reference buffer supports two voltages:
•2.048 V
•2.5 V
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with VDDA on some packages. In these packages the
internal voltage reference buffer is not available.
Figure 5. Voltage reference buffer
MSv40197V1
VREFBUF
Low frequency
cut-off capacitor
DAC, ADC
Bandgap +
VDDA
-
100 nF
VREF+
Functional overview STM32L471xx
42/229 DS10741 Rev 2
3.18 Comparators (COMP)
The STM32L471xx devices embed two rail-to-rail comparators with programmable
reference voltage (internal or external), hysteresis and speed (low speed for low-power) and
with selectable output polarity.
The reference voltage can be one of the following:
•External I/O
•DAC output channels
•Internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers
and can be also combined into a window comparator.
3.19 Operational amplifier (OPAMP)
The STM32L471xx embeds two operational amplifiers with external or internal follower
routing and PGA capability.
The operational amplifier features:
•Low input bias current
•Low offset voltage
•Low-power mode
•Rail-to-rail input
3.20 Touch sensing controller (TSC)
The touch sensing controller provides a simple solution for adding capacitive sensing
functionality to any application. Capacitive sensing technology is able to detect finger
presence near an electrode which is protected from direct touch by a dielectric (glass,
plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is
measured using a proven implementation based on a surface charge transfer acquisition
principle.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
DS10741 Rev 2 43/229
STM32L471xx Functional overview
58
The main features of the touch sensing controller are the following:
•Proven and robust surface charge transfer acquisition principle
•Supports up to 24 capacitive sensing channels
•Up to 3 capacitive sensing channels can be acquired in parallel offering a very good
response time
•Spread spectrum feature to improve system robustness in noisy environments
•Full hardware management of the charge transfer acquisition sequence
•Programmable charge transfer frequency
•Programmable sampling capacitor I/O pin
•Programmable channel I/O pin
•Programmable max count value to avoid long acquisition when a channel is faulty
•Dedicated end of acquisition and max count error flags with interrupt capability
•One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
components
•Compatible with proximity, touchkey, linear and rotary touch sensor implementation
•Designed to operate with STMTouch touch sensing firmware library
Note: The number of capacitive sensing channels is dependent on the size of the packages and
subject to I/O availability.
3.21 Digital filter for Sigma-Delta Modulators (DFSDM)
The device embeds one DFSDM with 4 digital filters modules and 8 external input serial
channels (transceivers) or alternately 8 internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
Functional overview STM32L471xx
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hardware. DFSDM features optional parallel data stream inputs from microcontrollers
memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
The DFSDM peripheral supports:
•8 multiplexed input digital serial channels:
– configurable SPI interface to connect various SD modulator(s)
– configurable Manchester coded 1 wire interface support
– PDM (Pulse Density Modulation) microphone input support
– maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
– clock output for SD modulator(s): 0..20 MHz
•alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):
– internal sources: device memory data streams (DMA)
•4 digital filter modules with adjustable digital signal processing:
–Sinc
x filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
– integrator: oversampling ratio (1..256)
•up to 24-bit output data resolution, signed output data format
•automatic data offset correction (offset stored in register by user)
•continuous or single conversion
•start-of-conversion triggered by:
– software trigger
– internal timers
– external events
– start-of-conversion synchronously with first digital filter module (DFSDM1_FLT0)
•analog watchdog feature:
– low value and high value data threshold registers
– dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
– input from final output data or from selected input digital serial channels
– continuous monitoring independently from standard conversion
•short circuit detector to detect saturated analog input values (bottom and top range):
– up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
– monitoring continuously each input serial channel
•break signal generation on analog watchdog event or on short circuit detector event
•extremes detector:
– storage of minimum and maximum values of final conversion data
– refreshed by software
•DMA capability to read the final conversion data
•interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
•“regular” or “injected” conversions:
– “regular” conversions can be requested at any time or even in continuous mode
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STM32L471xx Functional overview
58
without having any impact on the timing of “injected” conversions
– “injected” conversions for precise timing and with high conversion priority
3.22 Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
3.23 Timers and watchdogs
The STM32L471xx includes two advanced control timers, up to nine general-purpose
timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer.
The table below compares the features of the advanced control, general purpose and basic
timers.
Table 10. DFSDM1 implementation
DFSDM features DFSDM1
Number of channels 8
Number of filters 4
Input from internal ADC -
Supported trigger sources 10
Pulses skipper -
ID registers support -
Table 11. Timer feature comparison
Timer type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complementary
outputs
Advanced
control TIM1, TIM8 16-bit Up, down,
Up/down
Any integer
between 1
and 65536
Yes 4 3
General-
purpose TIM2, TIM5 32-bit Up, down,
Up/down
Any integer
between 1
and 65536
Yes 4 No
General-
purpose TIM3, TIM4 16-bit Up, down,
Up/down
Any integer
between 1
and 65536
Yes 4 No
General-
purpose TIM15 16-bit Up
Any integer
between 1
and 65536
Yes 2 1
Functional overview STM32L471xx
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3.23.1 Advanced-control timer (TIM1, TIM8)
The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6
channels. They have complementary PWM outputs with programmable inserted dead-
times. They can also be seen as complete general-purpose timers. The 4 independent
channels can be used for:
•Input capture
•Output compare
•PWM generation (edge or center-aligned modes) with full modulation capability (0-
100%)
•One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIMx timers (described in
Section 3.23.2) using the same architecture, so the advanced-control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
General-
purpose TIM16, TIM17 16-bit Up
Any integer
between 1
and 65536
Yes 1 1
Basic TIM6, TIM7 16-bit Up
Any integer
between 1
and 65536
Yes 0 No
Table 11. Timer feature comparison (continued)
Timer type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complementary
outputs
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STM32L471xx Functional overview
58
3.23.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17)
There are up to seven synchronizable general-purpose timers embedded in the
STM32L471xx (see Table 11 for differences). Each general-purpose timer can be used to
generate PWM outputs, or act as a simple time base.
•TIM2, TIM3, TIM4 and TIM5
They are full-featured general-purpose timers:
– TIM2 and TIM5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler
– TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler.
These timers feature 4 independent channels for input capture/output compare, PWM
or one-pulse mode output. They can work together, or with the other general-purpose
timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
•TIM15, 16 and 17
They are general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
– TIM15 has 2 channels and 1 complementary channel
– TIM16 and TIM17 have 1 channel and 1 complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.23.3 Basic timers (TIM6 and TIM7)
The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebases.
3.23.4 Low-power timer (LPTIM1 and LPTIM2)
The devices embed two low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to
wakeup the system from Stop mode.
LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.
LPTIM2 is active in Stop 0 and Stop 1 mode.
Functional overview STM32L471xx
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This low-power timer supports the following features:
•16-bit up counter with 16-bit autoreload register
•16-bit compare register
•Configurable output: pulse, PWM
•Continuous/ one shot mode
•Selectable software/hardware input trigger
•Selectable clock source
– Internal clock sources: LSE, LSI, HSI16 or APB clock
– External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application).
•Programmable digital glitch filter
•Encoder mode (LPTIM1 only)
3.23.5 Infrared interface (IRTIM)
The STM32L471xx includes one infrared interface (IRTIM). It can be used with an infrared
LED to perform remote control functions. It uses TIM16 and TIM17 output channels to
generate output signal waveforms on IR_OUT pin.
3.23.6 Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.
3.23.7 System window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.23.8 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
•A 24-bit down counter
•Autoreload capability
•Maskable system interrupt generation when the counter reaches 0.
•Programmable clock source
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STM32L471xx Functional overview
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3.24 Real-time clock (RTC) and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
•Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
•Two programmable alarms.
•On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
•Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
•Three anti-tamper detection pins with programmable filter.
•Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
•17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby or Shutdown mode.
The RTC clock sources can be:
•A 32.768 kHz external crystal (LSE)
•An external resonator or oscillator (LSE)
•The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
•The high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes except Shutdown mode.
All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt
and wakeup the device from the low-power modes.
Functional overview STM32L471xx
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3.25 Inter-integrated circuit interface (I2C)
The device embeds three I2C. Refer to Table 12: I2C implementation for the features
implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•I2C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
•System Management Bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (Packet Error Checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
•Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility
•Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming. Refer to
Figure 4: Clock tree.
•Wakeup from Stop mode on address match
•Programmable analog and digital noise filters
•1-byte buffer with DMA capability
Table 12. I2C implementation
I2C features(1)
1. X: supported
I2C1 I2C2 I2C3
Standard-mode (up to 100 kbit/s) X X X
Fast-mode (up to 400 kbit/s) X X X
Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X
Programmable analog and digital noise filters X X X
SMBus/PMBus hardware support X X X
Independent clock X X X
Wakeup from Stop 0 / Stop 1 mode on address match X X X
Wakeup from Stop 2 mode on address match - - X
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STM32L471xx Functional overview
58
3.26 Universal synchronous/asynchronous receiver transmitter
(USART)
The STM32L471xx devices have three embedded universal synchronous receiver
transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver
transmitters (UART4, UART5).
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable. They are able to communicate at speeds of up to
10Mbit/s.
USART1, USART2 and USART3 also provide Smart Card mode (ISO 7816 compliant) and
SPI-like communication capability.
All USART have a clock domain independent from the CPU clock, allowing the USARTx
(x=1,2,3,4,5) to wake up the MCU from Stop mode using baudrates up to 204 Kbaud. The
wake up events from Stop mode are programmable and can be:
•Start bit detection
•Any received data frame
•A specific programmed data frame
All USART interfaces can be served by the DMA controller.
Table 13. STM32L471xx USART/UART/LPUART features
USART modes/features(1) USART1 USART2 USART3 UART4 UART5 LPUART1
Hardware flow control for modem XXXXX X
Continuous communication using DMA XXXXX X
Multiprocessor communication XXXXX X
Synchronous mode X X X - - -
Smartcard mode X X X - - -
Single-wire half-duplex communication XXXXX X
IrDA SIR ENDEC block XXXXX -
LIN mode XXXXX -
Dual clock domain XXXXX X
Wakeup from Stop 0 / Stop 1 modes XXXXX X
Wakeup from Stop 2 mode ----- X
Receiver timeout interrupt XXXXX -
Modbus communication XXXXX -
Auto baud rate detection X (4 modes) -
Driver Enable XXXXX X
LPUART/USART data length 7, 8 and 9 bits
1. X = supported.
Functional overview STM32L471xx
52/229 DS10741 Rev 2
3.27 Low-power universal asynchronous receiver transmitter
(LPUART)
The device embeds one Low-Power UART. The LPUART supports asynchronous serial
communication with minimum power consumption. It supports half duplex single wire
communication and modem operations (CTS/RTS). It allows multiprocessor
communication.
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop
mode are programmable and can be:
•Start bit detection
•Any received data frame
•A specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
LPUART interface can be served by the DMA controller.
DS10741 Rev 2 53/229
STM32L471xx Functional overview
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3.28 Serial peripheral interface (SPI)
Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s
slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8
master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI
interfaces support NSS pulse mode, TI mode and Hardware CRC calculation.
All SPI interfaces can be served by the DMA controller.
3.29 Serial audio interfaces (SAI)
The device embeds 2 SAI. Refer to Table 14: SAI implementation for the features
implementation. The SAI bus interface handles communications between the
microcontroller and the serial audio protocol.
The SAI peripheral supports:
•Two independent audio sub-blocks which can be transmitters or receivers with their
respective FIFO.
•8-word integrated FIFOs for each audio sub-block.
•Synchronous or asynchronous mode between the audio sub-blocks.
•Master or slave configuration independent for both audio sub-blocks.
•Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode.
•Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.
•Peripheral with large configurability and flexibility allowing to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
out.
•Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame.
•Number of bits by frame may be configurable.
•Frame synchronization active level configurable (offset, bit length, level).
•First active bit position in the slot is configurable.
•LSB first or MSB first for data transfer.
•Mute mode.
•Stereo/Mono audio frame capability.
•Communication clock strobing edge configurable (SCK).
•Error flags with associated interrupts if enabled respectively.
– Overrun and underrun detection.
– Anticipated frame synchronization signal detection in slave mode.
– Late frame synchronization signal detection in slave mode.
– Codec not ready for the AC’97 mode in reception.
•Interruption sources when enabled:
–Errors.
– FIFO requests.
•DMA interface with 2 dedicated channels to handle access to the dedicated integrated
FIFO of each SAI audio sub-block.
Functional overview STM32L471xx
54/229 DS10741 Rev 2
3.30 Single wire protocol master interface (SWPMI)
The Single wire protocol master interface (SWPMI) is the master interface corresponding to
the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The
main features are:
•full-duplex communication mode
•automatic SWP bus state management (active, suspend, resume)
•configurable bitrate up to 2 Mbit/s
•automatic SOF, EOF and CRC handling
SWPMI can be served by the DMA controller.
3.31 Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
Table 14. SAI implementation
SAI features(1)
1. X: supported
SAI1 SAI2
I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X
Mute mode X X
Stereo/Mono audio frame capability. X X
16 slots X X
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X X
FIFO Size X (8 Word) X (8 Word)
SPDIF X X
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STM32L471xx Functional overview
58
The CAN peripheral supports:
•Supports CAN protocol version 2.0 A, B Active
•Bit rates up to 1 Mbit/s
•Transmission
– Three transmit mailboxes
– Configurable transmit priority
•Reception
– Two receive FIFOs with three stages
– 14 Scalable filter banks
– Identifier list feature
– Configurable FIFO overrun
•Time-triggered communication option
– Disable automatic retransmission mode
– 16-bit free running timer
– Time Stamp sent in last two data bytes
•Management
– Maskable interrupts
– Software-efficient mailbox mapping at a unique address space
3.32 Secure digital input/output and MultiMediaCards Interface
(SDMMC)
The card host interface (SDMMC) provides an interface between the APB peripheral bus
and MultiMediaCards (MMCs), SD memory cards and SDIO cards.
The SDMMC features include the following:
•Full compliance with MultiMediaCard System Specification Version 4.2. Card support
for three different databus modes: 1-bit (default), 4-bit and 8-bit
•Full compatibility with previous versions of MultiMediaCards (forward compatibility)
•Full compliance with SD Memory Card Specifications Version 2.0
•Full compliance with SD I/O Card Specification Version 2.0: card support for two
different databus modes: 1-bit (default) and 4-bit
•Data transfer up to 48 MHz for the 8 bit mode
•Data write and read with DMA capability
3.33 Flexible static memory controller (FSMC)
The Flexible static memory controller (FSMC) includes two memory controllers:
•The NOR/PSRAM memory controller
•The NAND/memory controller
This memory controller is also named Flexible memory controller (FMC).
Functional overview STM32L471xx
56/229 DS10741 Rev 2
The main features of the FMC controller are the following:
•Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR Flash memory/OneNAND Flash memory
– PSRAM (4 memory banks)
– NAND Flash memory with ECC hardware to check up to 8 Kbyte of data
•8-,16- bit data bus width
•Independent Chip Select control for each memory bank
•Independent configuration for each memory bank
•Write FIFO
•The Maximum FMC_CLK frequency for synchronous accesses is HCLK/2.
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
3.34 Quad SPI memory interface (QUADSPI)
The Quad SPI is a specialized communication interface targeting single, dual or quad SPI
flash memories. It can operate in any of the three following modes:
•Indirect mode: all the operations are performed using the QUADSPI registers
•Status polling mode: the external flash status register is periodically read and an
interrupt can be generated in case of flag setting
•Memory-mapped mode: the external Flash is memory mapped and is seen by the
system as if it were an internal memory
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STM32L471xx Functional overview
58
The Quad SPI interface supports:
•Three functional modes: indirect, status-polling, and memory-mapped
•SDR and DDR support
•Fully programmable opcode for both indirect and memory mapped mode
•Fully programmable frame format for both indirect and memory mapped mode
•Each of the 5 following phases can be configured independently (enable, length,
single/dual/quad communication)
– Instruction phase
– Address phase
– Alternate bytes phase
– Dummy cycles phase
– Data phase
•Integrated FIFO for reception and transmission
•8, 16, and 32-bit data accesses are allowed
•DMA channel for indirect mode operations
•Programmable masking for external flash flag management
•Timeout management
•Interrupt generation on FIFO threshold, timeout, status match, operation complete, and
access error
Functional overview STM32L471xx
58/229 DS10741 Rev 2
3.35 Development support
3.35.1 Serial wire JTAG debug port (SWJ-DP)
The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.35.2 Embedded Trace Macrocell™
The Arm® Embedded Trace Macrocell™ provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32L471xx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then
formatted for display on the host computer that runs the debugger software. TPA hardware
is commercially available from common development tool vendors.
The Embedded Trace Macrocell™ operates with third party debugger software tools.
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DS10741 Rev 2 59/229
STM32L471xx Pinouts and pin description
94
4 Pinouts and pin description
Figure 6. STM32L471Zx LQFP144 pinout(1)
1. The above figure shows the package top view.
MSv36860V2
LQFP144
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PF13
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS
VDD
37
38
39
40
41
42
43
53
44
45
46
47
48
49
50
51
52
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
VDD
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
PF1
PF2
PF3
PF4
PF5
VSS
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PA0
PA1
PA2
1
2
3
4
5
6
7
17
8
9
10
11
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
92
101
100
99
98
97
96
95
94
93
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD
VSS
VDD
PA13
PA12
PA11
PA10
PG7
PA9
PA8
PC9
PC8
PC7
PC6
VDDIO2
VSS
PG8
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PG10
PD2
PD3
PD4
PD5
VSS
VDD
PD6
PD7
PG9
PG11
PG12
PG13
PG14
VSS
VDDIO2
PG15
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS
VDD
109
110
111
112
113
114
115
125
116
117
118
119
120
121
122
123
124
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Pinouts and pin description STM32L471xx
60/229 DS10741 Rev 2
Figure 7. STM32L471Zx UFBGA144 ballout(1)
1. The above figure shows the package top view.
Figure 8. STM32L471Qx UFBGA132 ballout(1)
1. The above figure shows the package top view.
MSv50901V1
VSS PE0 PB8 BOOT0 PB7 PG14 PG12 PD7 PD6 PD1 PD0 VSS
123456789101112
A
B
C
D
E
F
G
H
J
K
L
M
VBAT PE4 PE3 PE1 PB6 PG15 PG11 PD5 PC12 PC10 PA12 PA11
PC15-
OSC32_OUT PE5 PE2 PB9 PB5 PD4 PC11 PA14 PA13 PA10
PF4 PC14-
OSC32_IN PE6 PA15 PA9 PA8
PF6 PF1 PF0 PC6 PC9 PC8
PF8 PF7 PG8 PC7
PH1-
OSC_OUT PH0-OSC_IN PG3 PG5
PC2 PC0 PC1 PD11 PD14 PG2
VSSA VREF- PA0 PB14 PD10 PD15
VREF+ VDDA PA1 PA6 PB2 PE11 PB11 PB12 PD8 PD9
OPAMP1
_VINM PA2 PA4 OPAMP2
_VINM PB0 PF13 PE8 PE12 PE13 PE14 PB10 PB15
VSS PA3 PA5 PA7 PC5 PB1 PF14 PE7 PF15 PE10 PE15 VSS
PC13 PB4 PG13 PG10
PB3 PG9
PD3 PD2
VSS VDDVDDIO2 VDDPF2 VSS
PF5 PG6VDDIO2 PG7VSS VSSPF3 VDD
PF10 PD13VDD PG4VSS VSSPF9 VDD
VSS PD12VDD VDDNRST
PE9 PB13PF11 PG1PC3 PC4
PF12 PG0
VSS
MSv36862V6
PE3 PE1 PB8 BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12
123456789101112
A
B
C
D
E
F
G
H
J
K
L
M
PE4 PE2 PB9 PB7 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11
PC13 PE5 PE0 VDD PB5 PD2 PD0 PC11 VDD PA10
PC14-
OSC32_IN PE6 VSS PA9 PA8 PC9
PC15-
OSC32_OUT VBAT VSS PC8 PC7 PC6
PH0-OSC_IN VSS VSS VSS
PH1-
OSC_OUT VDD VDD VDD
PC0 NRST VDD PD15 PD14 PD13
VSSA/VREF- PC1 PC2 PD12 PD11 PD10
PG15 PC3 PA2 PA5 PC4 PD9 PD8 PB15 PB14 PB13
VREF+ PA0 PA3 PA6 PC5 PB2 PE8 PE10 PE12 PB10 PB11 PB12
VDDA PA1 OPAMP1_
VINM
OPAMP2_
VINM PB0 PB1 PE7 PE9 PE11 PE13 PE14 PE15
PG14 PG13
PF2 PF1 PF0 PG12 PG10 PG9
VSS VSS
VDD VDDIO2
PF4
PG11
PF3
PF5
PG6
PG7
PA4 PA7 PG8 PF12 PF14 PF15
PF11 PF13
PG5
PG3
PG1
PG0
PG4
PG2
PEZ
PEI!
PEA
PE)
PR
vs“
PC13
PCMVOSCE)? w
Pcmnscaz out
vss
vnu
PHflrOSC w
PHHJSC out
NRSI
Pco
P61
P62
PCS
VSSA
VREFr
VREFO
vnm
no
PM
w
LQFPlOD
van
P613
P61408032 w
P015 osczz our
PHOVOSC w
Pmosc our
NRsr
my
Pm
F02
F03
VSSANREF
VDDANREFO
PM:
PM
PM
LQFP64
DS10741 Rev 2 61/229
STM32L471xx Pinouts and pin description
94
Figure 9. STM32L471Vx LQFP100 pinout(1)
1. The above figure shows the package top view.
Figure 10. STM32L471Rx LQFP64 pinout(1)
1. The above figure shows the package top view.
MSv36861V2
LQFP100
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PE11
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE12
PE13
PE14
PE15
PB10
PB11
VSS
VDD
26
27
28
29
30
31
32
42
33
34
35
36
37
38
39
40
41
43
44
45
46
47
48
49
50
VBAT
PE2
PE3
PE4
PE5
PE6
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
VSS
VDD
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PA0
PA1
PA2
6
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
70
75
74
73
72
71
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PA11
VDD
VSS
VDD
PA13
PA12
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PD0
PA14
PA15
PC10
PC11
PC12
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS
VDD
81
76
77
78
79
80
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
MSv36863V2
LQFP64
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PB10
PB11
VSS
VDD
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA/VREF-
VDDA/VREF+
PA0
PA1
PA2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
VSS
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
PA14
PA15
PC10
PC11
PC12
PD2
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
VSS
VDD
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Pinouts and pin description STM32L471xx
62/229 DS10741 Rev 2
Table 15. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin type
S Supply pin
I Input only pin
I/O Input / output pin
I/O structure
FT 5 V tolerant I/O
TT 3.6 V tolerant I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Option for TT or FT I/Os
_f (1) I/O, Fm+ capable
_a (2) I/O, with Analog switch function supplied by VDDA
_s (3) I/O supplied only by VDDIO2
Notes Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.
Pin
functions
Alternate
functions Functions selected through GPIOx_AFR registers
Additional
functions Functions directly selected/enabled through peripheral registers
1. The related I/O structures in Table 16 are: FT_f, FT_fa.
2. The related I/O structures in Table 16 are: FT_a, FT_fa, TT_a.
3. The related I/O structures in Table 16 are: FT_s, FT_fs.
Table 16. STM32L471xx pin definitions
Pin Number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin functions
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA144
Alternate functions Additional
functions
- 1 B2 1 C3 PE2 I/O FT -
TRACECK, TIM3_ETR,
TSC_G7_IO1, FMC_A23,
SAI1_MCLK_A,
EVENTOUT
-
- 2 A1 2 B3 PE3 I/O FT -
TRACED0, TIM3_CH1,
TSC_G7_IO2, FMC_A19,
SAI1_SD_B, EVENTOUT
-
- 3 B1 3 B2 PE4 I/O FT -
TRACED1, TIM3_CH2,
DFSDM1_DATIN3,
TSC_G7_IO3, FMC_A20,
SAI1_FS_A, EVENTOUT
-
DS10741 Rev 2 63/229
STM32L471xx Pinouts and pin description
94
- 4 C2 4 C2 PE5 I/O FT -
TRACED2, TIM3_CH3,
DFSDM1_CKIN3,
TSC_G7_IO4, FMC_A21,
SAI1_SCK_A, EVENTOUT
-
- 5 D2 5 D3 PE6 I/O FT -
TRACED3, TIM3_CH4,
FMC_A22, SAI1_SD_A,
EVENTOUT
RTC_TAMP3/
WKUP3
16E26B1 VBAT S - - - -
2 7 C1 7 D4 PC13 I/O FT
(1)
(2) EVENTOUT
RTC_TAMP1/
RTC_TS/
RTC_OUT/
WKUP2
38D18D2
PC14-
OSC32_IN
(PC14)
I/O FT
(1)
(2) EVENTOUT OSC32_IN
49E19C1
PC15-
OSC32_OUT
(PC15)
I/O FT
(1)
(2) EVENTOUT OSC32_OUT
- - D6 10 E3 PF0 I/O FT_f - I2C2_SDA, FMC_A0,
EVENTOUT -
- - D5 11 E2 PF1 I/O FT_f - I2C2_SCL, FMC_A1,
EVENTOUT -
- - D4 12 E4 PF2 I/O FT - I2C2_SMBA, FMC_A2,
EVENTOUT -
- - E4 13 F4 PF3 I/O FT_a - FMC_A3, EVENTOUT ADC3_IN6
- - F3 14 D1 PF4 I/O FT_a - FMC_A4, EVENTOUT ADC3_IN7
- - F4 15 F3 PF5 I/O FT_a - FMC_A5, EVENTOUT ADC3_IN8
-10F216F6 VSS S - - - -
-11G217G5 VDD S - - - -
- - - 18 E1 PF6 I/O FT_a - TIM5_ETR, TIM5_CH1,
SAI1_SD_B, EVENTOUT ADC3_IN9
- - - 19 F2 PF7 I/O FT_a -
TIM5_CH2,
SAI1_MCLK_B,
EVENTOUT
ADC3_IN10
- - - 20 F1 PF8 I/O FT_a - TIM5_CH3, SAI1_SCK_B,
EVENTOUT ADC3_IN11
- - - 21 G4 PF9 I/O FT_a - TIM5_CH4, SAI1_FS_B,
TIM15_CH1, EVENTOUT ADC3_IN12
- - - 22 G3 PF10 I/O FT_a - TIM15_CH2, EVENTOUT ADC3_IN13
Table 16. STM32L471xx pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin functions
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA144
Alternate functions Additional
functions
Pinouts and pin description STM32L471xx
64/229 DS10741 Rev 2
512F123G2 PH0-OSC_IN
(PH0) I/O FT - EVENTOUT OSC_IN
613G124G1
PH1-OSC_OUT
(PH1) I/O FT - EVENTOUT OSC_OUT
7 14 H2 25 H4 NRST I/O RST - - -
8 15 H1 26 H2 PC0 I/O FT_fa -
LPTIM1_IN1, I2C3_SCL,
DFSDM1_DATIN4,
LPUART1_RX,
LPTIM2_IN1, EVENTOUT
ADC123_IN1
9 16 J2 27 H3 PC1 I/O FT_fa -
LPTIM1_OUT, I2C3_SDA,
DFSDM1_CKIN4,
LPUART1_TX,
EVENTOUT
ADC123_IN2
10 17 J3 28 H1 PC2 I/O FT_a -
LPTIM1_IN2, SPI2_MISO,
DFSDM1_CKOUT,
EVENTOUT
ADC123_IN3
11 18 K2 29 J4 PC3 I/O FT_a -
LPTIM1_ETR, SPI2_MOSI,
SAI1_SD_A,
LPTIM2_ETR, EVENTOUT
ADC123_IN4
- 19 - 30 J1 VSSA S - - - -
- 20 - 31 J2 VREF- S - - - -
12 - J1 - - VSSA/VREF- S - - - -
-21L132K1 VREF+ S - - - VREFBUF_
OUT
- 22 M1 33 K2 VDDA S - - - -
13----VDDA/VREF+S - - - -
14 23 L2 34 J3 PA0 I/O FT_a -
TIM2_CH1, TIM5_CH1,
TIM8_ETR, USART2_CTS,
UART4_TX,
SAI1_EXTCLK,
TIM2_ETR, EVENTOUT
OPAMP1_VINP,
ADC12_IN5,
RTC_TAMP2/
WKUP1
- - M3 - L1 OPAMP1_VINM I TT - - -
15 24 M2 35 K3 PA1 I/O FT_a (3)
TIM2_CH2, TIM5_CH2,
USART2_RTS_DE,
UART4_RX, TIM15_CH1N,
EVENTOUT
OPAMP1_VINM
, ADC12_IN6
16 25 K3 36 L2 PA2 I/O FT_a -
TIM2_CH3, TIM5_CH3,
USART2_TX,
SAI2_EXTCLK,
TIM15_CH1, EVENTOUT
ADC12_IN7,
WKUP4/LSCO
Table 16. STM32L471xx pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin functions
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA144
Alternate functions Additional
functions
DS10741 Rev 2 65/229
STM32L471xx Pinouts and pin description
94
17 26 L3 37 M2 PA3 I/O TT_a -
TIM2_CH4, TIM5_CH4,
USART2_RX, TIM15_CH2,
EVENTOUT
OPAMP1_
VOUT,
ADC12_IN8
18 27 E3 38 F7 VSS S - - - -
19 28 H3 39 G8 VDD S - - - -
20 29 J4 40 L3 PA4 I/O TT_a -
SPI1_NSS, SPI3_NSS,
USART2_CK, SAI1_FS_B,
LPTIM2_OUT, EVENTOUT
ADC12_IN9,
DAC1_OUT1
21 30 K4 41 M3 PA5 I/O TT_a -
TIM2_CH1, TIM2_ETR,
TIM8_CH1N, SPI1_SCK,
LPTIM2_ETR, EVENTOUT
ADC12_IN10,
DAC1_OUT2
22 31 L4 42 K4 PA6 I/O FT_a -
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN, SPI1_MISO,
USART3_CTS,
QUADSPI_BK1_IO3,
TIM1_BKIN_COMP2,
TIM8_BKIN_COMP2,
TIM16_CH1, EVENTOUT
OPAMP2_VINP,
ADC12_IN11
- - M4 - L4 OPAMP2_VINM I TT - - -
23 32 J5 43 M4 PA7 I/O FT_a (3)
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N, SPI1_MOSI,
QUADSPI_BK1_IO2,
TIM17_CH1, EVENTOUT
OPAMP2_VINM
, ADC12_IN12
24 33 K5 44 J5 PC4 I/O FT_a - USART3_TX, EVENTOUT COMP1_INM,
ADC12_IN13
25 34 L5 45 M5 PC5 I/O FT_a - USART3_RX, EVENTOUT
COMP1_INP,
ADC12_IN14,
WKUP5
26 35 M5 46 L5 PB0 I/O TT_a -
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N,
USART3_CK,
QUADSPI_BK1_IO1,
COMP1_OUT, EVENTOUT
OPAMP2_
VOUT,
ADC12_IN15
27 36 M6 47 M6 PB1 I/O FT_a -
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N,
DFSDM1_DATIN0,
USART3_RTS_DE,
QUADSPI_BK1_IO0,
LPTIM2_IN1, EVENTOUT
COMP1_INM,
ADC12_IN16
Table 16. STM32L471xx pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin functions
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA144
Alternate functions Additional
functions
Pinouts and pin description STM32L471xx
66/229 DS10741 Rev 2
28 37 L6 48 K5 PB2 I/O FT_a -
RTC_OUT, LPTIM1_OUT,
I2C3_SMBA,
DFSDM1_CKIN0,
EVENTOUT
COMP1_INP
- - K6 49 J6 PF11 I/O FT - EVENTOUT -
- - J7 50 K6 PF12 I/O FT - FMC_A6, EVENTOUT -
- - - 51 G6 VSS S - - - -
-- -52H6 VDD S - - - -
- - K7 53 L6 PF13 I/O FT - DFSDM1_DATIN6,
FMC_A7, EVENTOUT -
- - J8 54 M7 PF14 I/O FT -
DFSDM1_CKIN6,
TSC_G8_IO1, FMC_A8,
EVENTOUT
-
- - J9 55 M9 PF15 I/O FT - TSC_G8_IO2, FMC_A9,
EVENTOUT -
- - H9 56 K7 PG0 I/O FT - TSC_G8_IO3, FMC_A10,
EVENTOUT -
- - G9 57 J7 PG1 I/O FT - TSC_G8_IO4, FMC_A11,
EVENTOUT -
- 38 M7 58 M8 PE7 I/O FT -
TIM1_ETR,
DFSDM1_DATIN2,
FMC_D4, SAI1_SD_B,
EVENTOUT
-
- 39 L7 59 L7 PE8 I/O FT -
TIM1_CH1N,
DFSDM1_CKIN2,
FMC_D5, SAI1_SCK_B,
EVENTOUT
-
- 40 M8 60 J8 PE9 I/O FT -
TIM1_CH1,
DFSDM1_CKOUT,
FMC_D6, SAI1_FS_B,
EVENTOUT
-
- - F6 61 G7 VSS S - - - -
- - G6 62 E7 VDD S - - - -
- 41 L8 63 M10 PE10 I/O FT -
TIM1_CH2N,
DFSDM1_DATIN4,
TSC_G5_IO1,
QUADSPI_CLK, FMC_D7,
SAI1_MCLK_B,
EVENTOUT
-
Table 16. STM32L471xx pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin functions
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA144
Alternate functions Additional
functions
DS10741 Rev 2 67/229
STM32L471xx Pinouts and pin description
94
- 42 M9 64 K8 PE11 I/O FT -
TIM1_CH2,
DFSDM1_CKIN4,
TSC_G5_IO2,
QUADSPI_NCS, FMC_D8,
EVENTOUT
-
- 43 L9 65 L8 PE12 I/O FT -
TIM1_CH3N, SPI1_NSS,
DFSDM1_DATIN5,
TSC_G5_IO3,
QUADSPI_BK1_IO0,
FMC_D9, EVENTOUT
-
- 44 M10 66 L9 PE13 I/O FT -
TIM1_CH3, SPI1_SCK,
DFSDM1_CKIN5,
TSC_G5_IO4,
QUADSPI_BK1_IO1,
FMC_D10, EVENTOUT
-
- 45 M11 67 L10 PE14 I/O FT -
TIM1_CH4, TIM1_BKIN2,
TIM1_BKIN2_COMP2,
SPI1_MISO,
QUADSPI_BK1_IO2,
FMC_D11, EVENTOUT
-
- 46 M12 68 M11 PE15 I/O FT -
TIM1_BKIN,
TIM1_BKIN_COMP1,
SPI1_MOSI,
QUADSPI_BK1_IO3,
FMC_D12, EVENTOUT
-
29 47 L10 69 L11 PB10 I/O FT_f -
TIM2_CH3, I2C2_SCL,
SPI2_SCK,
DFSDM1_DATIN7,
USART3_TX,
LPUART1_RX,
QUADSPI_CLK,
COMP1_OUT,
SAI1_SCK_A, EVENTOUT
-
30 48 L11 70 K9 PB11 I/O FT_f -
TIM2_CH4, I2C2_SDA,
DFSDM1_CKIN7,
USART3_RX,
LPUART1_TX,
QUADSPI_NCS,
COMP2_OUT, EVENTOUT
-
31 49 F12 71 H5 VSS S - - - -
32 50 G12 72 - VDD S - - - -
Table 16. STM32L471xx pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin functions
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA144
Alternate functions Additional
functions
Pinouts and pin description STM32L471xx
68/229 DS10741 Rev 2
33 51 L12 73 K10 PB12 I/O FT -
TIM1_BKIN,
TIM1_BKIN_COMP2,
I2C2_SMBA, SPI2_NSS,
DFSDM1_DATIN1,
USART3_CK,
LPUART1_RTS_DE,
TSC_G1_IO1,
SWPMI1_IO, SAI2_FS_A,
TIM15_BKIN, EVENTOUT
-
34 52 K12 74 J9 PB13 I/O FT_f -
TIM1_CH1N, I2C2_SCL,
SPI2_SCK,
DFSDM1_CKIN1,
USART3_CTS,
LPUART1_CTS,
TSC_G1_IO2,
SWPMI1_TX,
SAI2_SCK_A,
TIM15_CH1N, EVENTOUT
-
35 53 K11 75 J10 PB14 I/O FT_f -
TIM1_CH2N, TIM8_CH2N,
I2C2_SDA, SPI2_MISO,
DFSDM1_DATIN2,
USART3_RTS_DE,
TSC_G1_IO3,
SWPMI1_RX,
SAI2_MCLK_A,
TIM15_CH1, EVENTOUT
-
36 54 K10 76 L12 PB15 I/O FT -
RTC_REFIN, TIM1_CH3N,
TIM8_CH3N, SPI2_MOSI,
DFSDM1_CKIN2,
TSC_G1_IO4,
SWPMI1_SUSPEND,
SAI2_SD_A, TIM15_CH2,
EVENTOUT
-
- 55 K9 77 K11 PD8 I/O FT - USART3_TX, FMC_D13,
EVENTOUT -
- 56 K8 78 K12 PD9 I/O FT -
USART3_RX, FMC_D14,
SAI2_MCLK_A,
EVENTOUT
-
- 57 J12 79 J11 PD10 I/O FT -
USART3_CK,
TSC_G6_IO1, FMC_D15,
SAI2_SCK_A, EVENTOUT
-
- 58 J11 80 H10 PD11 I/O FT -
USART3_CTS,
TSC_G6_IO2, FMC_A16,
SAI2_SD_A,
LPTIM2_ETR, EVENTOUT
-
Table 16. STM32L471xx pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin functions
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA144
Alternate functions Additional
functions
DS10741 Rev 2 69/229
STM32L471xx Pinouts and pin description
94
- 59 J10 81 H9 PD12 I/O FT -
TIM4_CH1,
USART3_RTS_DE,
TSC_G6_IO3, FMC_A17,
SAI2_FS_A, LPTIM2_IN1,
EVENTOUT
-
- 60 H12 82 G10 PD13 I/O FT -
TIM4_CH2, TSC_G6_IO4,
FMC_A18, LPTIM2_OUT,
EVENTOUT
-
- - - 83 E5 VSS S - - - -
-- -84F5 VDD S - - - -
- 61 H11 85 H11 PD14 I/O FT - TIM4_CH3, FMC_D0,
EVENTOUT -
- 62 H10 86 J12 PD15 I/O FT - TIM4_CH4, FMC_D1,
EVENTOUT -
- - G10 87 H12 PG2 I/O FT_s - SPI1_SCK, FMC_A12,
SAI2_SCK_B, EVENTOUT -
- - F9 88 G11 PG3 I/O FT_s - SPI1_MISO, FMC_A13,
SAI2_FS_B, EVENTOUT -
- - F10 89 G9 PG4 I/O FT_s -
SPI1_MOSI, FMC_A14,
SAI2_MCLK_B,
EVENTOUT
-
- - E9 90 G12 PG5 I/O FT_s -
SPI1_NSS,
LPUART1_CTS,
FMC_A15, SAI2_SD_B,
EVENTOUT
-
- - G4 91 F10 PG6 I/O FT_s -
I2C3_SMBA,
LPUART1_RTS_DE,
EVENTOUT
-
- - H4 92 F9 PG7 I/O FT_fs - I2C3_SCL, LPUART1_TX,
FMC_INT, EVENTOUT -
- - J6 93 F11 PG8 I/O FT_fs - I2C3_SDA, LPUART1_RX,
EVENTOUT -
- - - 94 M12 VSS S - - - -
- - - 95 F8 VDDIO2 S - - - -
37 63 E12 96 E10 PC6 I/O FT -
TIM3_CH1, TIM8_CH1,
DFSDM1_CKIN3,
TSC_G4_IO1,
SDMMC1_D6,
SAI2_MCLK_A,
EVENTOUT
-
Table 16. STM32L471xx pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin functions
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA144
Alternate functions Additional
functions
Pinouts and pin description STM32L471xx
70/229 DS10741 Rev 2
38 64 E11 97 F12 PC7 I/O FT -
TIM3_CH2, TIM8_CH2,
DFSDM1_DATIN3,
TSC_G4_IO2,
SDMMC1_D7,
SAI2_MCLK_B,
EVENTOUT
-
39 65 E10 98 E12 PC8 I/O FT -
TIM3_CH3, TIM8_CH3,
TSC_G4_IO3,
SDMMC1_D0, EVENTOUT
-
40 66 D12 99 E11 PC9 I/O FT -
TIM8_BKIN2, TIM3_CH4,
TIM8_CH4, TSC_G4_IO4,
SDMMC1_D1,
SAI2_EXTCLK,
TIM8_BKIN2_COMP1,
EVENTOUT
-
41 67 D11 100 D12 PA8 I/O FT -
MCO, TIM1_CH1,
USART1_CK,
LPTIM2_OUT, EVENTOUT
-
42 68 D10 101 D11 PA9 I/O FT - TIM1_CH2, USART1_TX,
TIM15_BKIN, EVENTOUT -
43 69 C12 102 C12 PA10 I/O FT - TIM1_CH3, USART1_RX,
TIM17_BKIN, EVENTOUT -
44 70 B12 103 B12 PA11 I/O FT -
TIM1_CH4, TIM1_BKIN2,
USART1_CTS, CAN1_RX,
TIM1_BKIN2_COMP1,
EVENTOUT
-
45 71 A12 104 B11 PA12 I/O FT -
TIM1_ETR,
USART1_RTS_DE,
CAN1_TX, EVENTOUT
-
46 72 A11 105 C11 PA13
(JTMS-SWDIO) I/O FT (4) JTMS-SWDIO, IR_OUT,
EVENTOUT -
47 - - - E8 VSS S - - - -
48 73 C11 106 E9 VDD S - - - -
- 74 F11 107 H8 VSS S - - - -
- 75 G11 108 H7 VDD S - - - -
49 76 A10 109 C10 PA14
(JTCK-SWCLK) I/O FT (4) JTCK-SWCLK,
EVENTOUT -
Table 16. STM32L471xx pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin functions
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA144
Alternate functions Additional
functions
DS10741 Rev 2 71/229
STM32L471xx Pinouts and pin description
94
50 77 A9 110 D10 PA15 (JTDI) I/O FT (4)
JTDI, TIM2_CH1,
TIM2_ETR, SPI1_NSS,
SPI3_NSS,
UART4_RTS_DE,
TSC_G3_IO1, SAI2_FS_B,
EVENTOUT
-
51 78 B11 111 B10 PC10 I/O FT -
SPI3_SCK, USART3_TX,
UART4_TX, TSC_G3_IO2,
SDMMC1_D2,
SAI2_SCK_B, EVENTOUT
-
52 79 C10 112 C9 PC11 I/O FT -
SPI3_MISO, USART3_RX,
UART4_RX, TSC_G3_IO3,
SDMMC1_D3,
SAI2_MCLK_B,
EVENTOUT
-
53 80 B10 113 B9 PC12 I/O FT -
SPI3_MOSI, USART3_CK,
UART5_TX, TSC_G3_IO4,
SDMMC1_CK,
SAI2_SD_B, EVENTOUT
-
- 81 C9 114 A11 PD0 I/O FT -
SPI2_NSS,
DFSDM1_DATIN7,
CAN1_RX, FMC_D2,
EVENTOUT
-
- 82 B9 115 A10 PD1 I/O FT -
SPI2_SCK,
DFSDM1_CKIN7,
CAN1_TX, FMC_D3,
EVENTOUT
-
54 83 C8 116 D9 PD2 I/O FT -
TIM3_ETR,
USART3_RTS_DE,
UART5_RX, TSC_SYNC,
SDMMC1_CMD,
EVENTOUT
-
- 84 B8 117 D8 PD3 I/O FT -
SPI2_MISO,
DFSDM1_DATIN0,
USART2_CTS, FMC_CLK,
EVENTOUT
-
- 85 B7 118 C8 PD4 I/O FT -
SPI2_MOSI,
DFSDM1_CKIN0,
USART2_RTS_DE,
FMC_NOE, EVENTOUT
-
- 86 A6 119 B8 PD5 I/O FT - USART2_TX, FMC_NWE,
EVENTOUT -
- - - 120 A1 VSS S - - - -
Table 16. STM32L471xx pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin functions
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA144
Alternate functions Additional
functions
Pinouts and pin description STM32L471xx
72/229 DS10741 Rev 2
- - - 121 - VDD S - - - -
- 87 B6 122 A9 PD6 I/O FT -
DFSDM1_DATIN1,
USART2_RX,
FMC_NWAIT, SAI1_SD_A,
EVENTOUT
-
- 88 A5 123 A8 PD7 I/O FT -
DFSDM1_CKIN1,
USART2_CK, FMC_NE1,
EVENTOUT
-
- - D9 124 C7 PG9 I/O FT_s -
SPI3_SCK, USART1_TX,
FMC_NCE/FMC_NE2,
SAI2_SCK_A,
TIM15_CH1N, EVENTOUT
-
- - D8 125 D7 PG10 I/O FT_s -
LPTIM1_IN1, SPI3_MISO,
USART1_RX, FMC_NE3,
SAI2_FS_A, TIM15_CH1,
EVENTOUT
-
- - G3 126 B7 PG11 I/O FT_s -
LPTIM1_IN2, SPI3_MOSI,
USART1_CTS,
SAI2_MCLK_A,
TIM15_CH2, EVENTOUT
-
- - D7 127 A7 PG12 I/O FT_s -
LPTIM1_ETR, SPI3_NSS,
USART1_RTS_DE,
FMC_NE4, SAI2_SD_A,
EVENTOUT
-
- - C7 128 D6 PG13 I/O FT_fs - I2C1_SDA, USART1_CK,
FMC_A24, EVENTOUT -
- - C6 129 A6 PG14 I/O FT_fs - I2C1_SCL, FMC_A25,
EVENTOUT -
- - F7 130 A12 VSS S - - - -
- - G7 131 E6 VDDIO2 S - - - -
- - K1 132 B6 PG15 I/O FT_s - LPTIM1_OUT,
I2C1_SMBA, EVENTOUT -
55 89 A8 133 C6
PB3
(JTDO-
TRACESWO)
I/O FT_a (4)
JTDO-TRACESWO,
TIM2_CH2, SPI1_SCK,
SPI3_SCK,
USART1_RTS_DE,
SAI1_SCK_B, EVENTOUT
COMP2_INM
Table 16. STM32L471xx pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin functions
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA144
Alternate functions Additional
functions
DS10741 Rev 2 73/229
STM32L471xx Pinouts and pin description
94
56 90 A7 134 D5 PB4
(NJTRST) I/O FT_a (4)
NJTRST, TIM3_CH1,
SPI1_MISO, SPI3_MISO,
USART1_CTS,
UART5_RTS_DE,
TSC_G2_IO1,
SAI1_MCLK_B,
TIM17_BKIN, EVENTOUT
COMP2_INP
57 91 C5 135 C5 PB5 I/O FT_a -
LPTIM1_IN1, TIM3_CH2,
I2C1_SMBA, SPI1_MOSI,
SPI3_MOSI, USART1_CK,
UART5_CTS,
TSC_G2_IO2,
COMP2_OUT,
SAI1_SD_B, TIM16_BKIN,
EVENTOUT
-
58 92 B5 136 B5 PB6 I/O FT_fa -
LPTIM1_ETR, TIM4_CH1,
TIM8_BKIN2, I2C1_SCL,
DFSDM1_DATIN5,
USART1_TX,
TSC_G2_IO3,
TIM8_BKIN2_COMP2,
SAI1_FS_B, TIM16_CH1N,
EVENTOUT
COMP2_INP
59 93 B4 137 A5 PB7 I/O FT_fa -
LPTIM1_IN2, TIM4_CH2,
TIM8_BKIN, I2C1_SDA,
DFSDM1_CKIN5,
USART1_RX,
UART4_CTS,
TSC_G2_IO4, FMC_NL,
TIM8_BKIN_COMP1,
TIM17_CH1N, EVENTOUT
COMP2_INM,
PVD_IN
60 94 A4 138 A4 BOOT0 I - - - -
61 95 A3 139 A3 PB8 I/O FT_f -
TIM4_CH3, I2C1_SCL,
DFSDM1_DATIN6,
CAN1_RX, SDMMC1_D4,
SAI1_MCLK_A,
TIM16_CH1, EVENTOUT
-
62 96 B3 140 C4 PB9 I/O FT_f -
IR_OUT, TIM4_CH4,
I2C1_SDA, SPI2_NSS,
DFSDM1_CKIN6,
CAN1_TX, SDMMC1_D5,
SAI1_FS_A, TIM17_CH1,
EVENTOUT
-
- 97 C3 141 A2 PE0 I/O FT - TIM4_ETR, FMC_NBL0,
TIM16_CH1, EVENTOUT -
Table 16. STM32L471xx pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin functions
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA144
Alternate functions Additional
functions
Pinouts and pin description STM32L471xx
74/229 DS10741 Rev 2
- 98 A2 142 B4 PE1 I/O FT - FMC_NBL1, TIM17_CH1,
EVENTOUT -
63 99 D3 143 M1 VSS S - - - -
64 100 C4 144 - VDD S - - - -
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of
the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup
domain and RTC register descriptions in the RM0392 reference manual.
3. OPAMPx_VINM pins are not available as additional functions on pins PA1 and PA7 on UFBGA packages. On UFBGA
packages, use the OPAMPx_VINM dedicated pins.
4. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4
pins and the internal pull-down on PA14 pin are activated.
Table 16. STM32L471xx pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin functions
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA144
Alternate functions Additional
functions
STM32L471xx Pinouts and pin description
DS10741 Rev 2 75/229
Table 17. Alternate function AF0 to AF7 (1)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
SYS_AF
TIM1/TIM2/
TIM5/TIM8/
LPTIM1
TIM1/TIM2/
TIM3/TIM4/
TIM5
TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM
USART1/
USART2/
USART3
Port A
PA0 - TIM2_CH1 TIM5_CH1 TIM8_ETR - - - USART2_CTS
PA1 - TIM2_CH2 TIM5_CH2 - - - - USART2_RTS_
DE
PA2 - TIM2_CH3 TIM5_CH3 - - - - USART2_TX
PA3 - TIM2_CH4 TIM5_CH4 - - - - USART2_RX
PA4-----SPI1_NSSSPI3_NSSUSART2_CK
PA5 - TIM2_CH1 TIM2_ETR TIM8_CH1N - SPI1_SCK - -
PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN - SPI1_MISO - USART3_CTS
PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N - SPI1_MOSI - -
PA8MCOTIM1_CH1---- -USART1_CK
PA9-TIM1_CH2---- -USART1_TX
PA10-TIM1_CH3---- -USART1_RX
PA11 - TIM1_CH4 TIM1_BKIN2 - - - - USART1_CTS
PA12-TIM1_ETR---- -
USART1_RTS_
DE
PA13 JTMS-SWDIO IR_OUT - - - - - -
PA14JTCK-SWCLK----- - -
PA15 JTDI TIM2_CH1 TIM2_ETR - - SPI1_NSS SPI3_NSS -
Pinouts and pin description STM32L471xx
76/229 DS10741 Rev 2
Port B
PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N - - - USART3_CK
PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - - DFSDM1_
DATIN0
USART3_RTS_
DE
PB2 RTC_OUT LPTIM1_OUT - - I2C3_SMBA - DFSDM1_
CKIN0 -
PB3 JTDO-
TRACESWO TIM2_CH2 - - - SPI1_SCK SPI3_SCK USART1_RTS_
DE
PB4 NJTRST - TIM3_CH1 - - SPI1_MISO SPI3_MISO USART1_CTS
PB5 - LPTIM1_IN1 TIM3_CH2 - I2C1_SMBA SPI1_MOSI SPI3_MOSI USART1_CK
PB6 - LPTIM1_ETR TIM4_CH1 TIM8_BKIN2 I2C1_SCL - DFSDM1_
DATIN5 USART1_TX
PB7 - LPTIM1_IN2 TIM4_CH2 TIM8_BKIN I2C1_SDA - DFSDM1_CKIN5 USART1_RX
PB8 - - TIM4_CH3 - I2C1_SCL - DFSDM1_
DATIN6 -
PB9 - IR_OUT TIM4_CH4 - I2C1_SDA SPI2_NSS DFSDM1_
CKIN6 -
PB10 - TIM2_CH3 - - I2C2_SCL SPI2_SCK DFSDM1_
DATIN7 USART3_TX
PB11 - TIM2_CH4 - - I2C2_SDA - DFSDM1_CKIN7 USART3_RX
PB12 - TIM1_BKIN - TIM1_BKIN_
COMP2 I2C2_SMBA SPI2_NSS DFSDM1_
DATIN1 USART3_CK
PB13 - TIM1_CH1N - - I2C2_SCL SPI2_SCK DFSDM1_CKIN1 USART3_CTS
PB14 - TIM1_CH2N - TIM8_CH2N I2C2_SDA SPI2_MISO DFSDM1_
DATIN2
USART3_RTS_
DE
PB15 RTC_REFIN TIM1_CH3N - TIM8_CH3N - SPI2_MOSI DFSDM1_CKIN2 -
Table 17. Alternate function AF0 to AF7 (1) (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
SYS_AF
TIM1/TIM2/
TIM5/TIM8/
LPTIM1
TIM1/TIM2/
TIM3/TIM4/
TIM5
TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM
USART1/
USART2/
USART3
STM32L471xx Pinouts and pin description
DS10741 Rev 2 77/229
Port C
PC0 - LPTIM1_IN1 - - I2C3_SCL - DFSDM1_
DATIN4 -
PC1 - LPTIM1_OUT - - I2C3_SDA - DFSDM1_CKIN4 -
PC2 - LPTIM1_IN2 - - - SPI2_MISO DFSDM1_
CKOUT -
PC3 - LPTIM1_ETR - - - SPI2_MOSI - -
PC4------ -USART3_TX
PC5------ -USART3_RX
PC6 - - TIM3_CH1 TIM8_CH1 - - DFSDM1_CKIN3 -
PC7 - - TIM3_CH2 TIM8_CH2 - - DFSDM1_
DATIN3 -
PC8 - - TIM3_CH3 TIM8_CH3 - - - -
PC9 - TIM8_BKIN2 TIM3_CH4 TIM8_CH4 - - - -
PC10------SPI3_SCKUSART3_TX
PC11------SPI3_MISOUSART3_RX
PC12------SPI3_MOSIUSART3_CK
PC13------ - -
PC14------ - -
PC15------ - -
Table 17. Alternate function AF0 to AF7 (1) (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
SYS_AF
TIM1/TIM2/
TIM5/TIM8/
LPTIM1
TIM1/TIM2/
TIM3/TIM4/
TIM5
TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM
USART1/
USART2/
USART3
Pinouts and pin description STM32L471xx
78/229 DS10741 Rev 2
Port D
PD0-----SPI2_NSS
DFSDM1_
DATIN7 -
PD1-----SPI2_SCKDFSDM1_CKIN7-
PD2 - - TIM3_ETR - - - - USART3_RTS_
DE
PD3-----SPI2_MISO
DFSDM1_
DATIN0 USART2_CTS
PD4-----SPI2_MOSIDFSDM1_CKIN0
USART2_RTS_
DE
PD5------ -USART2_TX
PD6------
DFSDM1_
DATIN1 USART2_RX
PD7------DFSDM1_CKIN1USART2_CK
PD8------ -USART3_TX
PD9------ -USART3_RX
PD10------ -USART3_CK
PD11------ -USART3_CTS
PD12 - - TIM4_CH1 - - - - USART3_RTS_
DE
PD13 - - TIM4_CH2 - - - - -
PD14 - - TIM4_CH3 - - - - -
PD15 - - TIM4_CH4 - - - - -
Table 17. Alternate function AF0 to AF7 (1) (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
SYS_AF
TIM1/TIM2/
TIM5/TIM8/
LPTIM1
TIM1/TIM2/
TIM3/TIM4/
TIM5
TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM
USART1/
USART2/
USART3
STM32L471xx Pinouts and pin description
DS10741 Rev 2 79/229
Port E
PE0--TIM4_ETR--- - -
PE1------ - -
PE2 TRACECK - TIM3_ETR - - - - -
PE3 TRACED0 - TIM3_CH1 - - - - -
PE4 TRACED1 - TIM3_CH2 - - - DFSDM1_
DATIN3 -
PE5 TRACED2 - TIM3_CH3 - - - DFSDM1_CKIN3 -
PE6 TRACED3 - TIM3_CH4 - - - - -
PE7-TIM1_ETR----
DFSDM1_
DATIN2 -
PE8-TIM1_CH1N----DFSDM1_CKIN2-
PE9-TIM1_CH1----
DFSDM1_
CKOUT -
PE10-TIM1_CH2N----
DFSDM1_
DATIN4 -
PE11-TIM1_CH2----DFSDM1_CKIN4-
PE12 - TIM1_CH3N - - - SPI1_NSS DFSDM1_
DATIN5 -
PE13 - TIM1_CH3 - - - SPI1_SCK DFSDM1_CKIN5 -
PE14 - TIM1_CH4 TIM1_BKIN2 TIM1_BKIN2_
COMP2 - SPI1_MISO - -
PE15 - TIM1_BKIN - TIM1_BKIN_
COMP1 - SPI1_MOSI - -
Table 17. Alternate function AF0 to AF7 (1) (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
SYS_AF
TIM1/TIM2/
TIM5/TIM8/
LPTIM1
TIM1/TIM2/
TIM3/TIM4/
TIM5
TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM
USART1/
USART2/
USART3
Pinouts and pin description STM32L471xx
80/229 DS10741 Rev 2
Port F
PF0----I2C2_SDA- - -
PF1----I2C2_SCL- - -
PF2----I2C2_SMBA- - -
PF3------ - -
PF4------ - -
PF5------ - -
PF6 - TIM5_ETR TIM5_CH1 - - - - -
PF7 - - TIM5_CH2 - - - - -
PF8 - - TIM5_CH3 - - - - -
PF9 - - TIM5_CH4 - - - - -
PF10------ - -
PF11------ - -
PF12------ - -
PF13------
DFSDM1_
DATIN6 -
PF14------DFSDM1_CKIN6-
PF15------ - -
Table 17. Alternate function AF0 to AF7 (1) (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
SYS_AF
TIM1/TIM2/
TIM5/TIM8/
LPTIM1
TIM1/TIM2/
TIM3/TIM4/
TIM5
TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM
USART1/
USART2/
USART3
STM32L471xx Pinouts and pin description
DS10741 Rev 2 81/229
Port G
PG0------ - -
PG1------ - -
PG2-----SPI1_SCK- -
PG3-----SPI1_MISO- -
PG4-----SPI1_MOSI- -
PG5-----SPI1_NSS- -
PG6----I2C3_SMBA- - -
PG7----I2C3_SCL- - -
PG8----I2C3_SDA- - -
PG9------SPI3_SCKUSART1_TX
PG10-LPTIM1_IN1----SPI3_MISOUSART1_RX
PG11-LPTIM1_IN2----SPI3_MOSIUSART1_CTS
PG12-LPTIM1_ETR----SPI3_NSS
USART1_RTS_
DE
PG13----I2C1_SDA- -USART1_CK
PG14----I2C1_SCL- - -
PG15 - LPTIM1_OUT - - I2C1_SMBA - - -
Port H
PH0------ - -
PH1------ - -
1. Please refer to Table 18 for AF8 to AF15.
Table 17. Alternate function AF0 to AF7 (1) (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
SYS_AF
TIM1/TIM2/
TIM5/TIM8/
LPTIM1
TIM1/TIM2/
TIM3/TIM4/
TIM5
TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM
USART1/
USART2/
USART3
Pinouts and pin description STM32L471xx
82/229 DS10741 Rev 2
- Table 18. Alternate function AF8 to AF15(1)
Port
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
UART4,
UART5,
LPUART1
CAN1, TSC QUADSPI -
SDMMC1, COMP1,
COMP2, FMC,
SWPMI1
SAI1, SAI2
TIM2, TIM15,
TIM16, TIM17,
LPTIM2
EVENTOUT
Port A
PA0 UART4_TX - - - - SAI1_EXTCLK TIM2_ETR EVENTOUT
PA1 UART4_RX - - - - - TIM15_CH1N EVENTOUT
PA2 - - - - - SAI2_EXTCLK TIM15_CH1 EVENTOUT
PA3 - - - - - - TIM15_CH2 EVENTOUT
PA4 - - - - - SAI1_FS_B LPTIM2_OUT EVENTOUT
PA5 - - - - - - LPTIM2_ETR EVENTOUT
PA6 - - QUADSPI_BK1_IO3 - TIM1_BKIN_
COMP2
TIM8_BKIN_
COMP2 TIM16_CH1 EVENTOUT
PA7 - - QUADSPI_BK1_IO2 - - - TIM17_CH1 EVENTOUT
PA8 - - - - - - LPTIM2_OUT EVENTOUT
PA9 - - - - - - TIM15_BKIN EVENTOUT
PA10 - - - - - - TIM17_BKIN EVENTOUT
PA11 - CAN1_RX - - TIM1_BKIN2_
COMP1 - - EVENTOUT
PA12 - CAN1_TX - - - - - EVENTOUT
PA13 - - - - - - - EVENTOUT
PA14 - - - - - - - EVENTOUT
PA15 UART4_RTS
_DE TSC_G3_IO1 - - - SAI2_FS_B - EVENTOUT
STM32L471xx Pinouts and pin description
DS10741 Rev 2 83/229
Port B
PB0 - - QUADSPI_BK1_IO1 - COMP1_OUT - - EVENTOUT
PB1 - - QUADSPI_BK1_IO0 - - - LPTIM2_IN1 EVENTOUT
PB2 - - - - - - - EVENTOUT
PB3 - - - - - SAI1_SCK_B - EVENTOUT
PB4 UART5_RTS
_DE TSC_G2_IO1 - - - SAI1_MCLK_
BTIM17_BKIN EVENTOUT
PB5 UART5_CTS TSC_G2_IO2 - - COMP2_OUT SAI1_SD_B TIM16_BKIN EVENTOUT
PB6 - TSC_G2_IO3 - - TIM8_BKIN2_
COMP2 SAI1_FS_B TIM16_CH1N EVENTOUT
PB7 UART4_CTS TSC_G2_IO4 - - FMC_NL TIM8_BKIN_
COMP1 TIM17_CH1N EVENTOUT
PB8 - CAN1_RX - - SDMMC1_D4 SAI1_MCLK_
ATIM16_CH1 EVENTOUT
PB9 - CAN1_TX - - SDMMC1_D5 SAI1_FS_A TIM17_CH1 EVENTOUT
PB10 LPUART1_
RX - QUADSPI_CLK - COMP1_OUT SAI1_SCK_A - EVENTOUT
PB11 LPUART1_TX - QUADSPI_NCS - COMP2_OUT - - EVENTOUT
PB12 LPUART1_
RTS_DE TSC_G1_IO1 - - SWPMI1_IO SAI2_FS_A TIM15_BKIN EVENTOUT
PB13 LPUART1_
CTS TSC_G1_IO2 - - SWPMI1_TX SAI2_SCK_A TIM15_CH1N EVENTOUT
PB14 - TSC_G1_IO3 - - SWPMI1_RX SAI2_MCLK_
ATIM15_CH1 EVENTOUT
PB15 - TSC_G1_IO4 - - SWPMI1_SUSPEND SAI2_SD_A TIM15_CH2 EVENTOUT
Table 18. Alternate function AF8 to AF15(1) (continued)
Port
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
UART4,
UART5,
LPUART1
CAN1, TSC QUADSPI -
SDMMC1, COMP1,
COMP2, FMC,
SWPMI1
SAI1, SAI2
TIM2, TIM15,
TIM16, TIM17,
LPTIM2
EVENTOUT
Pinouts and pin description STM32L471xx
84/229 DS10741 Rev 2
Port C
PC0 LPUART1_
RX - - - - - LPTIM2_IN1 EVENTOUT
PC1 LPUART1_TX - - - - - - EVENTOUT
PC2 - - - - - - - EVENTOUT
PC3 - - - - - SAI1_SD_A LPTIM2_ETR EVENTOUT
PC4 - - - - - - - EVENTOUT
PC5 - - - - - - - EVENTOUT
PC6 - TSC_G4_IO1 - - SDMMC1_D6 SAI2_MCLK_
A- EVENTOUT
PC7 - TSC_G4_IO2 - - SDMMC1_D7 SAI2_MCLK_
B- EVENTOUT
PC8 - TSC_G4_IO3 - - SDMMC1_D0 - - EVENTOUT
PC9 - TSC_G4_IO4 - - SDMMC1_D1 SAI2_EXTCLK TIM8_BKIN2_
COMP1 EVENTOUT
PC10 UART4_TX TSC_G3_IO2 - - SDMMC1_D2 SAI2_SCK_B - EVENTOUT
PC11 UART4_RX TSC_G3_IO3 - - SDMMC1_D3 SAI2_MCLK_
B- EVENTOUT
PC12 UART5_TX TSC_G3_IO4 - - SDMMC1_CK SAI2_SD_B - EVENTOUT
PC13 - - - - - - - EVENTOUT
PC14 - - - - - - - EVENTOUT
PC15 - - - - - - - EVENTOUT
Table 18. Alternate function AF8 to AF15(1) (continued)
Port
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
UART4,
UART5,
LPUART1
CAN1, TSC QUADSPI -
SDMMC1, COMP1,
COMP2, FMC,
SWPMI1
SAI1, SAI2
TIM2, TIM15,
TIM16, TIM17,
LPTIM2
EVENTOUT
STM32L471xx Pinouts and pin description
DS10741 Rev 2 85/229
Port D
PD0 - CAN1_RX - - FMC_D2 - - EVENTOUT
PD1 - CAN1_TX - - FMC_D3 - - EVENTOUT
PD2 UART5_RX TSC_SYNC - - SDMMC1_CMD - - EVENTOUT
PD3 - - - - FMC_CLK - - EVENTOUT
PD4 - - - - FMC_NOE - - EVENTOUT
PD5 - - - - FMC_NWE - - EVENTOUT
PD6 - - - - FMC_NWAIT SAI1_SD_A - EVENTOUT
PD7 - - - - FMC_NE1 - - EVENTOUT
PD8 - - - - FMC_D13 - - EVENTOUT
PD9 - - - - FMC_D14 SAI2_MCLK_
A- EVENTOUT
PD10 - TSC_G6_IO1 - - FMC_D15 SAI2_SCK_A - EVENTOUT
PD11 - TSC_G6_IO2 - - FMC_A16 SAI2_SD_A LPTIM2_ETR EVENTOUT
PD12 - TSC_G6_IO3 - - FMC_A17 SAI2_FS_A LPTIM2_IN1 EVENTOUT
PD13 - TSC_G6_IO4 - - FMC_A18 - LPTIM2_OUT EVENTOUT
PD14 - - - - FMC_D0 - - EVENTOUT
PD15 - - - - FMC_D1 - - EVENTOUT
Table 18. Alternate function AF8 to AF15(1) (continued)
Port
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
UART4,
UART5,
LPUART1
CAN1, TSC QUADSPI -
SDMMC1, COMP1,
COMP2, FMC,
SWPMI1
SAI1, SAI2
TIM2, TIM15,
TIM16, TIM17,
LPTIM2
EVENTOUT
Pinouts and pin description STM32L471xx
86/229 DS10741 Rev 2
Port E
PE0 - - - - FMC_NBL0 - TIM16_CH1 EVENTOUT
PE1 - - - - FMC_NBL1 - TIM17_CH1 EVENTOUT
PE2 - TSC_G7_IO1 - - FMC_A23 SAI1_MCLK_
A- EVENTOUT
PE3 - TSC_G7_IO2 - - FMC_A19 SAI1_SD_B - EVENTOUT
PE4 - TSC_G7_IO3 - - FMC_A20 SAI1_FS_A - EVENTOUT
PE5 - TSC_G7_IO4 - - FMC_A21 SAI1_SCK_A - EVENTOUT
PE6 - - - - FMC_A22 SAI1_SD_A - EVENTOUT
PE7 - - - - FMC_D4 SAI1_SD_B - EVENTOUT
PE8 - - - - FMC_D5 SAI1_SCK_B - EVENTOUT
PE9 - - - - FMC_D6 SAI1_FS_B - EVENTOUT
PE10 - TSC_G5_IO1 QUADSPI_CLK - FMC_D7 SAI1_MCLK_
B- EVENTOUT
PE11 - TSC_G5_IO2 QUADSPI_NCS - FMC_D8 - - EVENTOUT
PE12 - TSC_G5_IO3 QUADSPI_BK1_IO0 - FMC_D9 - - EVENTOUT
PE13 - TSC_G5_IO4 QUADSPI_BK1_IO1 - FMC_D10 - - EVENTOUT
PE14 - - QUADSPI_BK1_IO2 - FMC_D11 - - EVENTOUT
PE15 - - QUADSPI_BK1_IO3 - FMC_D12 - - EVENTOUT
Table 18. Alternate function AF8 to AF15(1) (continued)
Port
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
UART4,
UART5,
LPUART1
CAN1, TSC QUADSPI -
SDMMC1, COMP1,
COMP2, FMC,
SWPMI1
SAI1, SAI2
TIM2, TIM15,
TIM16, TIM17,
LPTIM2
EVENTOUT
STM32L471xx Pinouts and pin description
DS10741 Rev 2 87/229
Port F
PF0 - - - - FMC_A0 - - EVENTOUT
PF1 - - - - FMC_A1 - - EVENTOUT
PF2 - - - - FMC_A2 - - EVENTOUT
PF3 - - - - FMC_A3 - - EVENTOUT
PF4 - - - - FMC_A4 - - EVENTOUT
PF5 - - - - FMC_A5 - - EVENTOUT
PF6 - - - - - SAI1_SD_B - EVENTOUT
PF7 - - - - - SAI1_MCLK_
B- EVENTOUT
PF8 - - - - - SAI1_SCK_B - EVENTOUT
PF9 - - - - - SAI1_FS_B TIM15_CH1 EVENTOUT
PF10 - - - - - - TIM15_CH2 EVENTOUT
PF11 - - - - - - - EVENTOUT
PF12 - - - - FMC_A6 - - EVENTOUT
PF13 - - - - FMC_A7 - - EVENTOUT
PF14 - TSC_G8_IO1 - - FMC_A8 - - EVENTOUT
PF15 - TSC_G8_IO2 - - FMC_A9 - - EVENTOUT
Table 18. Alternate function AF8 to AF15(1) (continued)
Port
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
UART4,
UART5,
LPUART1
CAN1, TSC QUADSPI -
SDMMC1, COMP1,
COMP2, FMC,
SWPMI1
SAI1, SAI2
TIM2, TIM15,
TIM16, TIM17,
LPTIM2
EVENTOUT
Pinouts and pin description STM32L471xx
88/229 DS10741 Rev 2
Port G
PG0 - TSC_G8_IO3 - - FMC_A10 - - EVENTOUT
PG1 - TSC_G8_IO4 - - FMC_A11 - - EVENTOUT
PG2 - - - - FMC_A12 SAI2_SCK_B - EVENTOUT
PG3 - - - - FMC_A13 SAI2_FS_B - EVENTOUT
PG4 - - - - FMC_A14 SAI2_MCLK_
B- EVENTOUT
PG5 LPUART1_
CTS - - - FMC_A15 SAI2_SD_B - EVENTOUT
PG6 LPUART1_
RTS_DE - - - - - - EVENTOUT
PG7 LPUART1_
TX - - - FMC_INT - - EVENTOUT
PG8 LPUART1_
RX - - - - - - EVENTOUT
PG9 - - - - FMC_NCE/
FMC_NE2 SAI2_SCK_A TIM15_CH1N EVENTOUT
PG10 - - - - FMC_NE3 SAI2_FS_A TIM15_CH1 EVENTOUT
PG11 - - - - - SAI2_MCLK_
ATIM15_CH2 EVENTOUT
PG12 - - - - FMC_NE4 SAI2_SD_A - EVENTOUT
PG13 - - - - FMC_A24 - - EVENTOUT
PG14 - - - - FMC_A25 - - EVENTOUT
PG15 - - - - - - - EVENTOUT
Table 18. Alternate function AF8 to AF15(1) (continued)
Port
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
UART4,
UART5,
LPUART1
CAN1, TSC QUADSPI -
SDMMC1, COMP1,
COMP2, FMC,
SWPMI1
SAI1, SAI2
TIM2, TIM15,
TIM16, TIM17,
LPTIM2
EVENTOUT
STM32L471xx Pinouts and pin description
DS10741 Rev 2 89/229
Port H
PH0 - - - - - - - EVENTOUT
PH1 - - - - - - - EVENTOUT
1. Please refer to Table 17 for AF0 to AF7.
Table 18. Alternate function AF8 to AF15(1) (continued)
Port
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
UART4,
UART5,
LPUART1
CAN1, TSC QUADSPI -
SDMMC1, COMP1,
COMP2, FMC,
SWPMI1
SAI1, SAI2
TIM2, TIM15,
TIM16, TIM17,
LPTIM2
EVENTOUT
Memory mapping STM32L471xx
90/229 DS10741 Rev 2
5 Memory mapping
Figure 11. STM32L471xx memory map
MS34100V3
0xFFFF FFFF
0xE000 0000
0xC000 0000
0xA000 0000
0x8000 0000
0x6000 0000
0x4000 0000
0x2000 0000
0x0000 0000
0
1
2
3
4
5
6
7
Cortex™-M4
with FPU
Internal
Peripherals
Peripherals
SRAM1
CODE
OTP area
System memory
Flash memory
Flash, system memory
or SRAM, depending on
BOOT configuration
AHB2
AHB1
APB2
APB1
0x5006 0C00
0x4800 0000
0x4002 4400
0x4002 0000
0x4001 6400
0x4001 0000
0x4000 9800
0x4000 0000
0x1FFF FFFF
0x1FFF F810
0x1FFF 0000
0x0810 0000
0x0800 0000
0x0010 0000
0x0000 0000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x1000 8000
0x1000 0000
SRAM2
FMC and
QUADSPI
registers
FMC bank 3
FMC bank 1 &
bank 2
Option Bytes
System memory
Options Bytes
0x1FFF F800
0x1FFF 7000
0x1FFF 7400
0x1FFF 7800
0x1FFF 7810
0x1FFF 8000
0x1FFF F000
Reserved
Reserved
QUADSPI registers
FMC registers
0xBFFF FFFF
0xA000 1400
0xA000 1000
0xA000 0000
Reserved
Reserved
Reserved
Reserved
0x5FFF FFFF
0x9000 0000
QUADSPI Flash
bank
DS10741 Rev 2 91/229
STM32L471xx Memory mapping
94
Table 19. STM32L471xx memory map and peripheral register boundary addresses(1)
Bus Boundary address Size
(bytes) Peripheral
AHB3
0xA000 1000 - 0xA000 13FF 1 KB QUADSPI
0xA000 0000 - 0xA000 0FFF 4 KB FMC
AHB2
0x5006 0800 - 0x5006 0BFF 1 KB RNG
0x5004 0400 - 0x5006 07FF 129 KB Reserved
0x5004 0000 - 0x5004 03FF 1 KB ADC
0x5000 0000 - 0x5003 FFFF 16 KB Reserved
0x4800 2000 - 0x4FFF FFFF ~127 MB Reserved
0x4800 1C00 - 0x4800 1FFF 1 KB GPIOH
0x4800 1800 - 0x4800 1BFF 1 KB GPIOG
0x4800 1400 - 0x4800 17FF 1 KB GPIOF
0x4800 1000 - 0x4800 13FF 1 KB GPIOE
0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD
0x4800 0800 - 0x4800 0BFF 1 KB GPIOC
0x4800 0400 - 0x4800 07FF 1 KB GPIOB
0x4800 0000 - 0x4800 03FF 1 KB GPIOA
-0x4002 4400 - 0x47FF FFFF ~127 MB Reserved
AHB1
0x4002 4000 - 0x4002 43FF 1 KB TSC
0x4002 3400 - 0x4002 3FFF 1 KB Reserved
0x4002 3000 - 0x4002 33FF 1 KB CRC
0x4002 2400 - 0x4002 2FFF 3 KB Reserved
0x4002 2000 - 0x4002 23FF 1 KB FLASH registers
0x4002 1400 - 0x4002 1FFF 3 KB Reserved
0x4002 1000 - 0x4002 13FF 1 KB RCC
0x4002 0800 - 0x4002 0FFF 2 KB Reserved
0x4002 0400 - 0x4002 07FF 1 KB DMA2
0x4002 0000 - 0x4002 03FF 1 KB DMA1
Memory mapping STM32L471xx
92/229 DS10741 Rev 2
APB2
0x4001 6400 - 0x4001 FFFF 39 KB Reserved
0x4001 6000 - 0x4000 63FF 1 KB DFSDM1
0x4001 5C00 - 0x4000 5FFF 1 KB Reserved
0x4001 5800 - 0x4000 5BFF 1 KB SAI2
0x4001 5400 - 0x4000 57FF 1 KB SAI1
0x4001 4C00 - 0x4000 53FF 2 KB Reserved
0x4001 4800 - 0x4001 4BFF 1 KB TIM17
0x4001 4400 - 0x4001 47FF 1 KB TIM16
0x4001 4000 - 0x4001 43FF 1 KB TIM15
APB2
0x4001 3C00 - 0x4001 3FFF 1 KB Reserved
0x4001 3800 - 0x4001 3BFF 1 KB USART1
0x4001 3400 - 0x4001 37FF 1 KB TIM8
0x4001 3000 - 0x4001 33FF 1 KB SPI1
0x4001 2C00 - 0x4001 2FFF 1 KB TIM1
0x4001 2800 - 0x4001 2BFF 1 KB SDMMC1
0x4001 2000 - 0x4001 27FF 2 KB Reserved
0x4001 1C00 - 0x4001 1FFF 1 KB FIREWALL
0x4001 0800- 0x4001 1BFF 5 KB Reserved
0x4001 0400 - 0x4001 07FF 1 KB EXTI
0x4001 0200 - 0x4001 03FF
1 KB
COMP
0x4001 0030 - 0x4001 01FF VREFBUF
0x4001 0000 - 0x4001 002F SYSCFG
Table 19. STM32L471xx memory map and peripheral register boundary addresses(1)
(continued)
Bus Boundary address Size
(bytes) Peripheral
DS10741 Rev 2 93/229
STM32L471xx Memory mapping
94
APB1
0x4000 9800 - 0x4000 FFFF 26 KB Reserved
0x4000 9400 - 0x4000 97FF 1 KB LPTIM2
0x4000 8C00 - 0x4000 93FF 2 KB Reserved
0x4000 8800 - 0x4000 8BFF 1 KB SWPMI1
0x4000 8400 - 0x4000 87FF 1 KB Reserved
0x4000 8000 - 0x4000 83FF 1 KB LPUART1
0x4000 7C00 - 0x4000 7FFF 1 KB LPTIM1
0x4000 7800 - 0x4000 7BFF 1 KB OPAMP
0x4000 7400 - 0x4000 77FF 1 KB DAC1
0x4000 7000 - 0x4000 73FF 1 KB PWR
0x4000 6800 - 0x4000 6FFF 1 KB Reserved
0x4000 6400 - 0x4000 67FF 1 KB CAN1
0x4000 6000 - 0x4000 63FF 1 KB Reserved
0x4000 5C00- 0x4000 5FFF 1 KB I2C3
0x4000 5800 - 0x4000 5BFF 1 KB I2C2
0x4000 5400 - 0x4000 57FF 1 KB I2C1
0x4000 5000 - 0x4000 53FF 1 KB UART5
0x4000 4C00 - 0x4000 4FFF 1 KB UART4
0x4000 4800 - 0x4000 4BFF 1 KB USART3
0x4000 4400 - 0x4000 47FF 1 KB USART2
Table 19. STM32L471xx memory map and peripheral register boundary addresses(1)
(continued)
Bus Boundary address Size
(bytes) Peripheral
Memory mapping STM32L471xx
94/229 DS10741 Rev 2
APB1
0x4000 4000 - 0x4000 43FF 1 KB Reserved
0x4000 3C00 - 0x4000 3FFF 1 KB SPI3
0x4000 3800 - 0x4000 3BFF 1 KB SPI2
0x4000 3400 - 0x4000 37FF 1 KB Reserved
0x4000 3000 - 0x4000 33FF 1 KB IWDG
0x4000 2C00 - 0x4000 2FFF 1 KB WWDG
0x4000 2800 - 0x4000 2BFF 1 KB RTC
0x4000 1800 - 0x4000 27FF 4 KB Reserved
0x4000 1400 - 0x4000 17FF 1 KB TIM7
0x4000 1000 - 0x4000 13FF 1 KB TIM6
0x4000 0C00- 0x4000 0FFF 1 KB TIM5
0x4000 0800 - 0x4000 0BFF 1 KB TIM4
0x4000 0400 - 0x4000 07FF 1 KB TIM3
0x4000 0000 - 0x4000 03FF 1 KB TIM2
1. The gray color is used for reserved boundary addresses.
Table 19. STM32L471xx memory map and peripheral register boundary addresses(1)
(continued)
Bus Boundary address Size
(bytes) Peripheral
Figure 12. Pin loading conditions
5L
Figure 13. Pin input voltage
DS10741 Rev 2 95/229
STM32L471xx Electrical characteristics
206
6 Electrical characteristics
6.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3).
6.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2).
6.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 12.
6.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 13.
Figure 12. Pin loading conditions Figure 13. Pin input voltage
MS19210V1
MCU pin
C = 50 pF
MS19211V1
MCU pin
V
IN
Electrical characteristics STM32L471xx
96/229 DS10741 Rev 2
6.1.6 Power supply scheme
Figure 14. Power supply scheme
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
VDDIO2
VDD
MS35001V1
Level shifter
IO
logic
Kernel logic
(CPU, Digital
& Memories)
Backup circuitry
(LSE, RTC,
Backup registers)
IN
OUT
Regulator
GPIOs
1.55 – 3.6 V
IN
OUT
GPIOs
n x 100 nF
+1 x 4.7 μF
m x100 nF
Level shifter
IO
logic
+4.7 μF
m x VDDIO2
m x VSS
n x VSS
n x VDD
VBAT
VCORE
Power switch
VDDIO2
VDDIO1
ADCs/
DACs/
OPAMPs/
COMPs/
VREF
VREF+
VREF-
VDDA
10 nF
+1 μF
VDDA
VSSA
V
DDIO2
V
DD
Level shifter
IO
logic
Kernel logic
(CPU, Digital
& Memories)
Backup circuitry
(LSE, RTC,
Backup registers)
IN
OUT
Regulator
GPIOs
1.55 – 3.6 V
IN
OUT
GPIOs
n x 100 nF
+1 x 4.7 μF
m x100 nF
Level shifter
IO
logic
+4.7 μF
m x VDDIO2
m x VSS
n x VSS
n x VDD
VBAT
V
CORE
Power switch
V
DDIO2
V
DDIO1
ADCs/
DACs/
OPAMPs/
COMPs/
VREF
V
REF+
V
REF-
V
DDA
10 nF
+1 μF
VDDA
VSSA
V
REF
100 nF +1 μF
MS35001V3
VDDIO2
VDD
Level shifter
IO
logic
Kernel logic
(CPU, Digital
& Memories)
Backup circuitry
(LSE, RTC,
Backup registers)
IN
OUT
Regulator
GPIOs
1.55 – 3.6 V
IN
OUT
GPIOs
n x 100 nF
+1 x 4.7 μF
m x100 nF
Level shifter
IO
logic
+4.7 μF
m x VDDIO2
m x VSS
n x VSS
n x VDD
VBAT
VCORE
Power switch
VDDIO2
VDDIO1
ADCs/
DACs/
OPAMPs/
COMPs/
VREFBUF
VREF+
VREF-
VDDA
10 nF
+1 μF
VDDA
VSSA
VREF
100 nF +1 μF
DS10741 Rev 2 97/229
STM32L471xx Electrical characteristics
206
6.1.7 Current consumption measurement
Figure 15. Current consumption measurement scheme
6.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 20: Voltage characteristics,
Table 21: Current characteristics and Table 22: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 qualification standard, extended mission profiles are
available on demand.
MSv36865V1
VBAT
VDD
VDDA
IDD
IDDA
IDD_VBAT
VDDIO2
Table 20. Voltage characteristics(1)
Symbol Ratings Min Max Unit
VDDX - VSS
External main supply voltage (including
VDD, VDDA, VDDIO2, VBAT)-0.3 4.0 V
VIN(2)
Input voltage on FT_xxx pins VSS-0.3 min (VDD, VDDA, VDDIO2)
+ 4.0(3)(4)
V
Input voltage on TT_xx pins VSS-0.3 4.0
Input voltage on BOOT0 pin VSS 9.0
Input voltage on any other pins VSS-0.3 4.0
|VDDx|Variations between different VDDX power
pins of the same domain -50mV
|VSSx-VSS|Variations between all the different ground
pins(5) -50mV
1. All main power (VDD, VDDA, VDDIO2, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 21: Current characteristics for the maximum allowed injected
current values.
3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.
4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
H)
Electrical characteristics STM32L471xx
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5. Include VREF- pin.
Table 21. Current characteristics
Symbol Ratings Max Unit
IVDD Total current into sum of all VDD power lines (source)(1) 150
mA
IVSS Total current out of sum of all VSS ground lines (sink)(1) 150
IVDD(PIN) Maximum current into each VDD power pin (source)(1) 100
IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) 100
IIO(PIN)
Output current sunk by any I/O and control pin except FT_f 20
Output current sunk by any FT_f pin 20
Output current sourced by any I/O and control pin 20
IIO(PIN)
Total output current sunk by sum of all I/Os and control pins(2) 100
Total output current sourced by sum of all I/Os and control pins(2) 100
IINJ(PIN)(3)
Injected current on FT_xxx, TT_xx, RST and B pins, except PA4,
PA5 -5/+0(4)
Injected current on PA4, PA5 -5/0
|IINJ(PIN)| Total injected current (sum of all I/Os and control pins)(5) 25
1. All main power (VDD, VDDA, VDDIO2, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power
supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
3. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 20: Voltage
characteristics for the minimum allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum |IINJ(PIN)| is the absolute sum of the negative
injected currents (instantaneous values).
Table 22. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C
TJMaximum junction temperature 150 °C
DS10741 Rev 2 99/229
STM32L471xx Electrical characteristics
206
6.3 Operating conditions
6.3.1 General operating conditions
Table 23. General operating conditions
Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency - 0 80
MHzfPCLK1 Internal APB1 clock frequency - 0 80
fPCLK2 Internal APB2 clock frequency - 0 80
VDD Standard operating voltage - 1.71
(1) 3.6 V
VDDIO2 PG[15:2] I/Os supply voltage
At least one I/O in PG[15:2] used 1.08 3.6
V
PG[15:2] not used 0 3.6
VDDA Analog supply voltage
ADC or COMP used 1.62
3.6 V
DAC or OPAMP used 1.8
VREFBUF used 2.4
ADC, DAC, OPAMP, COMP,
VREFBUF not used 0
VBAT Backup operating voltage - 1.55 3.6 V
VIN I/O input voltage
TT_xx I/O -0.3 VDDIOx+0.3
V
BOOT0 0 9
All I/O except BOOT0 and TT_xx -0.3
Min(Min(VDD, VDDA,
VDDIO2)+3.6 V,
5.5 V)(2)(3)
PD
Power dissipation at
TA = 85 °C for suffix 6
or
TA = 105 °C for suffix 7(4)
LQFP144 - - 625
mW
LQFP100 - - 476
LQFP64 - - 444
UFBGA144 - - 377
UFBGA132 - - 363
PD
Power dissipation at TA =
125 °C for suffix 3(4)
LQFP144 - - 156
mW
LQFP100 - - 119
LQFP64 - - 111
UFBGA144 - - 94
UFBGA132 - - 90
Electrical characteristics STM32L471xx
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6.3.2 Operating conditions at power-up / power-down
The parameters given in Table 24 are derived from tests performed under the ambient
temperature condition summarized in Table 23.
The requirements for power-up/down sequence specified in Section 3.9.1: Power supply
schemes must be respected.
6.3.3 Embedded reset and power control block characteristics
The parameters given in Table 25 are derived from tests performed under the ambient
temperature conditions summarized in Table 23: General operating conditions.
TA
Ambient temperature for the
suffix 6 version
Maximum power dissipation –40 85
°C
Low-power dissipation(5) –40 105
Ambient temperature for the
suffix 7 version
Maximum power dissipation –40 105
Low-power dissipation(5) –40 125
Ambient temperature for the
suffix 3 version
Maximum power dissipation –40 125
Low-power dissipation(5) –40 130
TJ Junction temperature range
Suffix 6 version –40 105
°CSuffix 7 version –40 125
Suffix 3 version –40 130
1. When RESET is released functionality is guaranteed down to VBOR0 Min.
2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.
Maximum I/O input voltage is the smallest value between Min(VDD, VDDA, VDDIO2)+3.6 V and 5.5V.
3. For operation with voltage higher than Min (VDD, VDDA, VDDIO2) +0.3 V, the internal Pull-up and Pull-Down resistors must be
disabled.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.6: Thermal characteristics).
5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.6:
Thermal characteristics).
Table 23. General operating conditions (continued)
Symbol Parameter Conditions Min Max Unit
Table 24. Operating conditions at power-up / power-down
Symbol Parameter Conditions Min Max Unit
tVDD
VDD rise time rate
-
0
µs/V
VDD fall time rate 10
tVDDA
VDDA rise time rate
-
0
µs/V
VDDA fall time rate 10
tVDDIO2
VDDIO2 rise time rate
-
0
µs/V
VDDIO2 fall time rate 10
DS10741 Rev 2 101/229
STM32L471xx Electrical characteristics
206
Table 25. Embedded reset and power control block characteristics
Symbol Parameter Conditions(1) Min Typ Max Unit
tRSTTEMPO(2) Reset temporization after
BOR0 is detected VDD rising - 250 400 s
VBOR0(2) Brown-out reset threshold 0
Rising edge 1.62 1.66 1.7
V
Falling edge 1.6 1.64 1.69
VBOR1 Brown-out reset threshold 1
Rising edge 2.06 2.1 2.14
V
Falling edge 1.96 2 2.04
VBOR2 Brown-out reset threshold 2
Rising edge 2.26 2.31 2.35
V
Falling edge 2.16 2.20 2.24
VBOR3 Brown-out reset threshold 3
Rising edge 2.56 2.61 2.66
V
Falling edge 2.47 2.52 2.57
VBOR4 Brown-out reset threshold 4
Rising edge 2.85 2.90 2.95
V
Falling edge 2.76 2.81 2.86
VPVD0
Programmable voltage
detector threshold 0
Rising edge 2.1 2.15 2.19
V
Falling edge 2 2.05 2.1
VPVD1 PVD threshold 1
Rising edge 2.26 2.31 2.36
V
Falling edge 2.15 2.20 2.25
VPVD2 PVD threshold 2
Rising edge 2.41 2.46 2.51
V
Falling edge 2.31 2.36 2.41
VPVD3 PVD threshold 3
Rising edge 2.56 2.61 2.66
V
Falling edge 2.47 2.52 2.57
VPVD4 PVD threshold 4
Rising edge 2.69 2.74 2.79
V
Falling edge 2.59 2.64 2.69
VPVD5 PVD threshold 5
Rising edge 2.85 2.91 2.96
V
Falling edge 2.75 2.81 2.86
VPVD6 PVD threshold 6
Rising edge 2.92 2.98 3.04
V
Falling edge 2.84 2.90 2.96
Vhyst_BORH0 Hysteresis voltage of BORH0
Hysteresis in
continuous
mode
-20-
mV
Hysteresis in
other mode -30-
Vhyst_BOR_PVD
Hysteresis voltage of BORH
(except BORH0) and PVD --100-mV
IDD
(BOR_PVD)(2)
BOR(3) (except BOR0) and
PVD consumption from VDD
--1.11.6µA
VPVM2
VDDIO2 peripheral voltage
monitoring - 0.92 0.96 1 V
Electrical characteristics STM32L471xx
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VPVM3
VDDA peripheral voltage
monitoring
Rising edge 1.61 1.65 1.69
V
Falling edge 1.6 1.64 1.68
VPVM4
VDDA peripheral voltage
monitoring
Rising edge 1.78 1.82 1.86
V
Falling edge 1.77 1.81 1.85
Vhyst_PVM3 PVM3 hysteresis - - 10 - mV
Vhyst_PVM4 PVM4 hysteresis - - 10 - mV
IDD
(PVM1/PVM2)
(2)
PVM1 and PVM2
consumption from VDD
--0.2-µA
IDD
(PVM3/PVM4)
(2)
PVM3 and PVM4
consumption from VDD
--2-µA
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power
sleep modes.
2. Guaranteed by design.
3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply
current characteristics tables.
Table 25. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions(1) Min Typ Max Unit
DS10741 Rev 2 103/229
STM32L471xx Electrical characteristics
206
6.3.4 Embedded voltage reference
The parameters given in Table 26 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 23: General operating
conditions.
Table 26. Embedded internal voltage reference
Symbol Parameter Conditions Min Typ Max Unit
VREFINT Internal reference voltage –40 °C < TA < +130 °C 1.182 1.212 1.232 V
tS_vrefint (1)
ADC sampling time when
reading the internal reference
voltage
-4
(2) --µs
tstart_vrefint
Start time of reference voltage
buffer when ADC is enable --812
(2) µs
IDD(VREFINTBUF)
VREFINT buffer consumption
from VDD when converted by
ADC
- - 12.5 20(2) µA
VREFINT
Internal reference voltage
spread over the temperature
range
VDD = 3 V - 5 7.5(2) mV
TCoeff
Average temperature
coefficient –40°C < TA < +130°C - 30 50(2) ppm/°C
ACoeff Long term stability 1000 hours, T = 25°C - 300 1000(2) ppm
VDDCoeff Average voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200(2) ppm/V
VREFINT_DIV1 1/4 reference voltage
-
24 25 26
%
VREFINT
VREFINT_DIV2 1/2 reference voltage 49 50 51
VREFINT_DIV3 3/4 reference voltage 74 75 76
1. The shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design.
DS10741 Rev 2 105/229
STM32L471xx Electrical characteristics
206
6.3.5 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 15: Current consumption
measurement scheme.
The IDD_ALL parameters given in Table 27 to Table 39 represent the total MCU consumption
including the current supplying VDD, VDDIO2, VDDA and VBAT.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•All I/O pins are in analog input mode
•All peripherals are disabled except when explicitly mentioned
•The Flash memory access time is adjusted with the minimum wait states number,
depending on the fHCLK frequency (refer to the table “Number of wait states according
to CPU clock (HCLK) frequency” available in the RM0392 reference manual).
•When the peripherals are enabled fPCLK = fHCLK
The parameters given in Table 27 to Table 40 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 23: General
operating conditions.
Electrical characteristics STM32L471xx
106/229 DS10741 Rev 2
Table 27. Current consumption in Run and Low-power run modes, code with data processing
running from Flash, ART enable (Cache ON Prefetch OFF)
Symbol Parameter
Conditions TYP MAX(1)
Unit
-Voltage
scaling fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL
(Run)
Supply
current in
Run mode
fHCLK = fHSE up to
48MHz included,
bypass mode
PLL ON above
48 MHz all
peripherals disable
Range 2
26 MHz 2.88 2.93 3.05 3.23 3.58 3.20 3.37 3.51 3.93 4.76
mA
16 MHz 1.83 1.87 1.98 2.16 2.49 2.01 2.16 2.30 2.72 3.34
8 MHz 0.98 1.02 1.12 1.29 1.62 1.10 1.17 1.31 1.73 2.56
4 MHz 0.55 0.59 0.69 0.85 1.18 0.61 0.70 0.89 1.24 1.95
2 MHz 0.34 0.37 0.47 0.64 0.96 0.37 0.46 0.64 0.98 1.71
1 MHz 0.23 0.26 0.36 0.53 0.85 0.27 0.33 0.50 0.86 1.57
100 kHz 0.14 0.17 0.27 0.43 0.75 0.17 0.21 0.38 0.74 1.44
Range 1
80 MHz 10.2 10.3 10.5 10.7 11.1 11.22 11.8 12.1 12.5 13.3
72 MHz 9.24 9.31 9.47 9.69 10.1 10.16 10.7 11.0 11.4 12.2
64 MHz 8.25 8.32 8.46 8.68 9.09 9.08 9.6 9.9 10.3 11.1
48 MHz 6.28 6.35 6.5 6.72 7.11 6.91 7.3 7.6 8.0 8.8
32 MHz 4.24 4.30 4.44 4.65 5.04 4.66 4.97 5.26 5.67 6.51
24 MHz 3.21 3.27 3.4 3.61 3.98 3.53 3.76 4.05 4.46 5.30
16 MHz 2.19 2.24 2.36 2.56 2.94 2.41 2.66 2.95 3.16 3.99
IDD_ALL
(LPRun)
Supply
current in
Low-power
run mode
fHCLK = fMSI
all peripherals disable
2 MHz 272 303 413 592 958 330 393 579 954 1704
µA
1 MHz 154 184 293 473 835 195 265 457 822 1572
400 kHz 78 108 217 396 758 110 180 380 755 1505
100 kHz 42 73 182 360 723 75 138 331 706 1456
1. Guaranteed by characterization results, unless otherwise specified.
STM32L471xx Electrical characteristics
DS10741 Rev 2 107/229
Table 28. Current consumption in Run and Low-power run modes, code with data processing
running from Flash, ART disable
Symbol Parameter
Conditions TYP MAX(1)
Unit
-Voltage
scaling fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL
(Run)
Supply
current in
Run mode
fHCLK = fHSE up to
48MHz included,
bypass mode
PLL ON above
48 MHz all
peripherals disable
Range 2
26 MHz 3.15 3.19 3.31 3.50 3.85 3.47 3.70 3.84 4.26 4.88
mA
16 MHz 2.24 2.28 2.39 2.57 2.90 2.46 2.60 2.74 3.16 3.78
8 MHz 1.26 1.29 1.40 1.57 1.89 1.40 1.50 1.64 2.06 2.68
4 MHz 0.71 0.75 0.85 1.02 1.34 0.79 0.88 1.06 1.38 2.21
2 MHz 0.42 0.45 0.55 0.72 1.04 0.46 0.55 0.73 1.09 1.88
1 MHz 0.27 0.30 0.40 0.57 0.89 0.30 0.38 0.57 0.90 1.61
100 kHz 0.14 0.17 0.27 0.43 0.75 0.17 0.22 0.40 0.74 1.44
Range 1
80 MHz 10.0 10.1 10.3 10.6 11.0 11.00 11.35 11.64 12.26 13.10
72 MHz 9.06 9.13 9.28 9.51 9.92 9.97 10.36 10.65 11.06 11.69
64 MHz 8.96 9.04 9.22 9.48 9.92 9.86 10.25 10.54 10.95 11.79
48 MHz 7.64 7.72 7.91 8.17 8.62 8.40 8.76 8.90 9.52 10.36
32 MHz 5.49 5.57 5.74 5.98 6.40 6.04 6.40 6.69 7.10 7.94
24 MHz 4.16 4.22 4.36 4.57 4.96 4.60 4.86 5.15 5.56 6.19
16 MHz 2.93 2.99 3.13 3.35 3.75 3.22 3.43 3.72 4.13 4.97
IDD_ALL
(LPRun)
Supply
current in
Low-power
run
fHCLK = fMSI
all peripherals disable
2 MHz 358 392 503 683 1050 435 501 694 1069 1819
µA
1 MHz 197 230 340 519 880 245 312 512 887 1637
400 kHz 97 126 235 414 778 130 202 402 777 1527
100 kHz 47 77 186 365 726 85 147 347 711 1472
1. Guaranteed by characterization results, unless otherwise specified.
Electrical characteristics STM32L471xx
108/229 DS10741 Rev 2
Table 29. Current consumption in Run and Low-power run modes, code with data processing
running from SRAM1
Symbol Parameter
Conditions TYP MAX(1)
Unit
-Voltage
scaling fHCLK 25 °C 55 °C 85 °C 105
°C
125
°C 25 °C 55 °C 85 °C 105
°C
125
°C
IDD_ALL
(Run)
Supply
current in
Run mode
fHCLK = fHSE up to
48MHz included,
bypass mode
PLL ON above
48 MHz all
peripherals disable
Range 2
26 MHz 2.88 2.94 3.05 3.23 3.58 3.18 3.26 3.40 4.02 4.65
mA
16 MHz 1.83 1.87 1.98 2.15 2.50 2.01 2.16 2.30 2.72 3.34
8 MHz 0.97 1.00 1.11 1.27 1.62 1.07 1.16 1.32 1.73 2.36
4 MHz 0.54 0.57 0.67 0.84 1.18 0.59 0.69 0.88 1.23 1.96
2 MHz 0.33 0.36 0.46 0.62 0.96 0.37 0.45 0.63 0.98 1.70
1 MHz 0.22 0.25 0.35 0.51 0.85 0.25 0.33 0.50 0.86 1.57
100 kHz 0.12 0.15 0.25 0.41 0.75 0.15 0.21 0.39 0.74 1.45
Range 1
80 MHz 10.2 10.3 10.5 10.7 11.1 11.22 11.57 11.86 12.07 13.11
72 MHz 9.25 9.31 9.46 9.68 10.1 10.18 10.41 10.55 10.76 11.80
64 MHz 8.25 8.31 8.46 8.67 9.08 9.08 9.37 9.66 9.87 10.91
48 MHz 6.26 6.33 6.48 6.69 7.11 6.89 7.11 7.25 7.67 8.50
32 MHz 4.22 4.28 4.42 4.63 5.03 4.64 4.86 5.15 5.56 6.19
24 MHz 3.20 3.25 3.38 3.59 3.99 3.52 3.70 3.84 4.26 5.09
16 MHz 2.18 2.22 2.35 2.55 2.94 2.40 2.55 2.84 3.25 4.09
IDD_ALL
(LPRun)
Supply
current in
low-power
run mode
fHCLK = fMSI
all peripherals disable
FLASH in power-down
2 MHz 242 275 384 562 924 300 380 573 927 1677
µA
1 MHz 130 162 269 445 809 180 243 435 810 1560
400 kHz 61 90 197 374 734 95 160 353 728 1478
100 kHz 26 56 163 339 702 55 122 314 679 1429
1. Guaranteed by characterization results, unless otherwise specified.
DS10741 Rev 2 109/229
STM32L471xx Electrical characteristics
206
Table 30. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF)
Symbol Parameter
Conditions TYP
Unit
TYP
Unit
-Voltage
scaling Code 25 °C 25 °C
IDD_ALL
(Run)
Supply
current in
Run mode
fHCLK = fHSE up
to 48 MHz
included, bypass
mode PLL ON
above 48 MHz
all peripherals
disable
Range 2
fHCLK = 26 MHz
Reduced code(1) 2.9
mA
111
µA/MHz
Coremark 3.1 118
Dhrystone 2.1 3.1 119
Fibonacci 2.9 112
While(1) 2.8 108
Range 1
fHCLK = 80 MHz
Reduced code(1) 10.2
mA
127
µA/MHz
Coremark 10.9 136
Dhrystone 2.1 11.0 137
Fibonacci 10.5 131
While(1) 9.9 124
IDD_ALL
(LPRun)
Supply
current in
Low-power
run
fHCLK = fMSI = 2 MHz
all peripherals disable
Reduced code(1) 272
µA
136
µA/MHz
Coremark 291 145
Dhrystone 2.1 302 151
Fibonacci 269 135
While(1) 269 135
1. Reduced code used for characterization results provided in Table 27, Table 28, Table 29.
Table 31. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART disable
Symbol Parameter
Conditions TYP
Unit
TYP
Unit
-Voltage
scaling Code 25 °C 25 °C
IDD_ALL
(Run)
Supply
current in
Run mode
fHCLK = fHSE up to
48 MHz included,
bypass mode
PLL ON above
48 MHz
all peripherals
disable
Range 2
fHCLK = 26 MHz
Reduced code(1) 3.1
mA
119
µA/MHz
Coremark 2.9 111
Dhrystone 2.1 2.8 111
Fibonacci 2.7 104
While(1) 2.6 100
Range 1
fHCLK = 80 MHz
Reduced code(1) 10.0
mA
125
µA/MHz
Coremark 9.4 117
Dhrystone 2.1 9.1 114
Fibonacci 9.0 112
While(1) 9.3 116
Electrical characteristics STM32L471xx
110/229 DS10741 Rev 2
IDD_ALL
(LPRun)
Supply
current in
Low-power
run
fHCLK = fMSI = 2 MHz
all peripherals disable
Reduced code(1) 358
µA
179
µA/MHz
Coremark 392 196
Dhrystone 2.1 390 195
Fibonacci 385 192
While(1) 385 192
1. Reduced code used for characterization results provided in Table 27, Table 28, Table 29.
Table 31. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART disable (continued)
Symbol Parameter
Conditions TYP
Unit
TYP
Unit
-Voltage
scaling Code 25 °C 25 °C
Table 32. Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM1
Symbol Parameter
Conditions TYP
Unit
TYP
Unit
-Voltage
scaling Code 25 °C 25 °C
IDD_ALL
(Run)
Supply
current in
Run mode
fHCLK = fHSE up to
48 MHz included,
bypass mode
PLL ON above
48 MHz all
peripherals
disable
Range 2
fHCLK = 26 MHz
Reduced code(1) 2.9
mA
111
µA/MHz
Coremark 2.9 111
Dhrystone 2.1 2.9 111
Fibonacci 2.6 100
While(1) 2.6 100
Range 1
fHCLK = 80 MHz
Reduced code(1) 10.2
mA
127
µA/MHz
Coremark 10.4 130
Dhrystone 2.1 10.3 129
Fibonacci 9.6 120
While(1) 9.3 116
IDD_ALL
(LPRun)
Supply
current in
Low-power
run
fHCLK = fMSI = 2 MHz
all peripherals disable
Reduced code(1) 242
µA
121
µA/MHz
Coremark 242 121
Dhrystone 2.1 242 121
Fibonacci 225 112
While(1) 242 121
1. Reduced code used for characterization results provided in Table 27, Table 28, Table 29.
STM32L471xx Electrical characteristics
DS10741 Rev 2 111/229
Table 33. Current consumption in Sleep and Low-power sleep modes, Flash ON
Symbol Parameter
Conditions TYP MAX(1)
Unit
-Voltage
scaling fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL
(Sleep)
Supply
current in
sleep
mode,
fHCLK = fHSE up
to 48 MHz
included, bypass
mode
PLL ON above
48 MHz all
peripherals
disable
Range 2
26 MHz 0.92 0.96 1.07 1.25 1.59 1.012 1.14 1.36 1.77 2.40
mA
16 MHz 0.61 0.65 0.75 0.92 1.27 0.69 0.78 0.97 1.32 2.04
8 MHz 0.36 0.40 0.50 0.66 1.01 0.42 0.50 0.68 1.03 1.75
4 MHz 0.24 0.27 0.37 0.53 0.87 0.28 0.36 0.54 0.89 1.60
2 MHz 0.18 0.20 0.30 0.47 0.81 0.215 0.29 0.46 0.82 1.53
1 MHz 0.15 0.17 0.27 0.43 0.77 0.18 0.25 0.44 0.78 1.49
100 kHz 0.12 0.14 0.24 0.41 0.74 0.15 0.21 0.39 0.74 1.44
Range 1
80 MHz 2.96 3.00 3.13 3.33 3.73 3.26 3.43 3.72 4.13 4.97
72 MHz 2.69 2.73 2.85 3.05 3.45 2.96 3.21 3.50 3.71 4.54
64 MHz 2.41 2.45 2.58 2.77 3.17 2.65 2.88 3.17 3.58 4.21
48 MHz 1.88 1.93 2.07 2.27 2.67 2.10 2.27 2.41 2.83 3.66
32 MHz 1.30 1.35 1.48 1.68 2.08 1.43 1.56 1.85 2.26 3.10
24 MHz 1.01 1.05 1.17 1.37 1.76 1.11 1.23 1.52 1.93 2.77
16 MHz 0.71 0.75 0.87 1.07 1.45 0.80 0.90 1.19 1.60 2.44
IDD_ALL
(LPSleep)
Supply
current in
low-power
sleep
mode
fHCLK = fMSI
all peripherals disable
2 MHz 96 126 233 412 775 130 202 402 777 1527
µA
1 MHz 65 94 202 381 742 95 166 358 733 1483
400 kHz 43 73 181 359 718 75 138 331 706 1456
100 kHz 33 63 171 348 708 65 128 322 691 1441
1. Guaranteed by characterization results, unless otherwise specified.
Electrical characteristics STM32L471xx
112/229 DS10741 Rev 2
Table 34. Current consumption in Low-power sleep modes, Flash in power-down
Symbol Parameter
Conditions TYP MAX(1)
Unit
-Voltage
scaling fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL
(LPSleep)
Supply current
in low-power
sleep mode
fHCLK = fMSI
all peripherals disable
2 MHz 81 110 217 395 754 115 182 375 750 1500
µA
1 MHz 50 78 185 362 720 80 149 342 717 1456
400 kHz 28 57 163 340 698 60 122 314 689 1429
100 kHz 18 47 155 332 686 50 114 313 688 1438
1. Guaranteed by characterization results, unless otherwise specified.
Table 35. Current consumption in Stop 2 mode
Symbol Parameter
Conditions TYP MAX(1)
Unit
-V
DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL
(Stop 2)
Supply current in
Stop 2 mode,
RTC disabled
-
1.8 V 1.14 3.77 14.7 34.7 77 2.7 9 37 87 193
µA
2.4 V 1.15 3.86 15 35.5 79.1 2.7 10 38 89 198
3 V 1.18 3.97 15.4 36.4 81.3 2.8 10 39 91 203
3.6 V 1.26 4.11 16 38 85.1 3.0 10 40 95(2) 213
IDD_ALL
(Stop 2 with
RTC)
Supply current in
Stop 2 mode,
RTC enabled
RTC clocked by LSI
1.8 V 1.42 4.04 15 34.9 77.2 3.1 10 38 87 193
µA
2.4 V 1.5 4.22 15.4 35.7 79.2 3.2 11 39 89 198
3 V 1.64 4.37 15.8 36.7 81.4 3.4 11 40 92 204
3.6 V 1.79 4.65 16.6 38.4 85.4 3.6 12 42 96 214
RTC clocked by LSE
bypassed at 32768 Hz
1.8 V 1.5 4.13 15.2 35.3 77.6 3.2 10 38 88 194
2.4 V 1.63 4.33 15.6 36 79.6 3.4 11 39 90 199
3 V 1.79 4.55 16.1 37 81.8 3.6 11 40 93 205
3.6 V 2.04 4.9 16.8 38.7 85.6 3.9 12 42 97 214
RTC clocked by LSE
quartz(3)
in low drive mode
1.8 V 1.43 3.99 14.7 35 - 3.2 10 37 88 -
2.4 V 1.54 4.11 15 35.8 - 3.3 10 38 90 -
3 V 1.67 4.29 15.5 36.7 - 3.4 11 39 92 -
3.6 V 1.87 4.57 16.2 38.3 - 3.7 11 41 96 -
STM32L471xx Electrical characteristics
DS10741 Rev 2 113/229
IDD_ALL
(wakeup from
Stop 2)
Supply current
during wakeup
from Stop 2
mode
Wakeup clock is
MSI = 48 MHz,
voltage Range 1.
See (4).
3 V 1.9 - - - -
-mA
Wakeup clock is
MSI = 4 MHz,
voltage Range 2.
See (4).
3 V 2.24 - - - -
Wakeup clock is
HSI16 = 16 MHz,
voltage Range 1.
See (4).
3 V 2.1 - - - -
1. Guaranteed by characterization results, unless otherwise specified.
2. Guaranteed by test in production.
3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 42: Low-power mode wakeup timings.
Table 35. Current consumption in Stop 2 mode (continued)
Symbol Parameter
Conditions TYP MAX(1)
Unit
-V
DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
Table 36. Current consumption in Stop 1 mode
Symbol Parameter Conditions TYP MAX(1)
Unit
-V
DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL
(Stop 1)
Supply
current in
Stop 1 mode,
RTC disabled
-
1.8 V 6.59 24.7 92.7 208 437 16 62 232 520 1093
µA
2.4 V 6.65 24.8 92.9 209 439 17 62 232 523 1098
3 V 6.65 24.9 93.3 210 442 17 62 233 525 1105
3.6 V 6.70 25.1 93.8 212 447 17 63 235 530 1118
Electrical characteristics STM32L471xx
114/229 DS10741 Rev 2
IDD_ALL
(Stop 1 with
RTC)
Supply
current in stop
1 mode,
RTC enabled
RTC clocked by LSI
1.8 V 6.88 25.0 93.1 209 439 17 63 233 523 1098
µA
2.4 V 7.02 25.2 93.7 210 441 18 63 234 525 1103
3 V 7.12 25.4 94.2 212 444 18 64 236 530 1110
3.6 V 7.25 25.7 95.2 214 449 18 64 238 535 1123
RTC clocked by LSE
bypassed, at 32768 Hz
1.8 V 6.91 25.2 93.4 210 440 17 63 234 525 1100
2.4 V 7.04 25.3 94.2 211 443 18 63 236 528 1108
3 V 7.19 25.7 95.0 212 446 18 64 238 530 1115
3.6 V 7.97 26.0 96.1 215 451 20 65 240 538 1128
RTC clocked by LSE quartz(2)
in low drive mode
1.8 V 6.85 25.0 93.0 208.3 - 17 63 233 521 -
2.4 V 6.94 25.1 93.2 209.3 - 17 63 233 523 -
3 V 7.10 25.2 93.6 210.3 - 18 63 234 526 -
3.6 V 7.34 25.4 94.1 212.3 - 18 64 235 531 -
IDD_ALL
(wakeup
from Stop1)
Supply
current during
wakeup from
Stop 1
Wakeup clock MSI = 48 MHz,
voltage Range 1,
See (3).
3 V 1.47 - - - -
-mA
Wakeup clock MSI = 4 MHz,
voltage Range 2,
See (3).
3 V 1.7 - - - -
Wakeup clock
HSI16 = 16 MHz,
voltage Range 1,
See (3).
3 V 1.62 - - - -
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 42: Low-power mode wakeup timings.
Table 36. Current consumption in Stop 1 mode (continued)
Symbol Parameter
Conditions TYP MAX(1)
Unit
-V
DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
STM32L471xx Electrical characteristics
DS10741 Rev 2 115/229
Table 37. Current consumption in Stop 0 mode
Symbol Parameter
Conditions TYP MAX(1)
1. Guaranteed by characterization results, unless otherwise specified.
Unit
VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL
(Stop 0)
Supply
current in
Stop 0 mode,
RTC disabled
1.8 V 108 132 217 356 631 153 213 426 773 1461
µA
2.4 V 110 134 219 358 634 158 218 431 778 1468
3 V 111 135 220 360 637 161 221 433 783 1476
3.6 V 113 137 222 363 642 166 226 438 791(2)
2. Guaranteed by test in production.
1488
Electrical characteristics STM32L471xx
116/229 DS10741 Rev 2
Table 38. Current consumption in Standby mode
Symbol Parameter
Conditions TYP MAX(1)
Unit
-V
DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL
(Standby)
Supply current
in Standby
mode (backup
registers
retained),
RTC disabled
no independent watchdog
1.8 V 114 355 1540 4146 10735 176 888 3850 10365 26838
nA
2.4 V 138 407 1795 4828 12451 223 1018 4488 12070 31128
3 V 150 486 2074 5589 14291 263 1215 5185 13973 35728
3.6 V 198 618 2608 6928 17499 383 1545 6520 17320
(2) 43748
with independent
watchdog
1.8 V 317 - - - - - - - - -
2.4 V 391 - - - - - - - - -
3 V 438 - - - - - - - - -
3.6 V 566 - - - - - - - - -
IDD_ALL
(Standby
with RTC)
Supply current
in Standby
mode (backup
registers
retained),
RTC enabled
RTC clocked by LSI, no
independent watchdog
1.8 V 377 621 1873 4564 11318 491 1207 4250 10867 27537
nA
2.4 V 464 756 2210 5348 13166 614 1436 4986 12694 31986
3 V 572 913 2599 6219 15197 770 1727 5815 14729 36815
3.6 V 722 1144 3253 7724 18696 1012 2176 7294 18275 45184
RTC clocked by LSI, with
independent watchdog
1.8 V 456 - - - - - - - - -
2.4 V 557 - - - - - - - - -
3 V 663 - - - - - - - - -
3.6 V 885 - - - - - - - - -
RTC clocked by LSE
bypassed at 32768Hz
1.8 V 289 527 1747 4402 11009 - - - - -
nA
2.4 V 396 671 2108 5202 12869 - - - - -
3 V 528 853 2531 6095 14915 - - - - -
3.6 V 710 1111 3115 7470 18221 - - - - -
RTC clocked by LSE
quartz (3) in low drive mode
1.8 V 416 640 1862 4479 11908 - - - - -
2.4 V 514 796 2193 5236 13689 - - - - -
3 V 652 961 2589 6103 15598 - - - - -
3.6 V 821 1226 3235 7551 17947 - - - - -
STM32L471xx Electrical characteristics
DS10741 Rev 2 117/229
IDD_ALL
(SRAM2)(4)
Supply current
to be added in
Standby mode
when SRAM2
is retained
-
1.8 V 235 641 2293 5192 11213 588 1603 5733 12980 28033
nA
2.4 V 237 645 2303 5213 11246 593 1613 5758 13033 28115
3 V 236 647 2306 5221 11333 593 1618 5765 13053 28333
3.6 V 235 646 2308 5200 11327 595 1620 5770 13075 28350
IDD_ALL
(wakeup
from
Standby)
Supply current
during wakeup
from Standby
mode
Wakeup clock is
MSI = 4 MHz.
See (5).
3 V 1.7 - - - - - mA
1. Guaranteed by characterization results, unless otherwise specified.
2. Guaranteed by test in production.
3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
4. The supply current in Standby with SRAM2 mode is: IDD_ALL(Standby) + IDD_ALL(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: IDD_ALL(Standby
+ RTC) + IDD_ALL(SRAM2).
5. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 42: Low-power mode wakeup timings.
Table 38. Current consumption in Standby mode (continued)
Symbol Parameter
Conditions TYP MAX(1)
Unit
-V
DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
Table 39. Current consumption in Shutdown mode
Symbol Parameter
Conditions TYP MAX(1)
Unit
-V
DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_ALL
(Shutdown)
Supply current
in Shutdown
mode
(backup
registers
retained) RTC
disabled
-
1.8 V 29.8 194 1110 3250 9093 75 485 2775 8125 22733
nA
2.4 V 44.3 237 1310 3798 10473 111 593 3275 9495 26183
3 V 64.1 293 1554 4461 12082 160 733 3885 11153 30205
3.6 V 112 420 2041 5689 15186 280 1050 5103 14223 37965
Electrical characteristics STM32L471xx
118/229 DS10741 Rev 2
IDD_ALL
(Shutdown
with RTC)
Supply current
in Shutdown
mode
(backup
registers
retained) RTC
enabled
RTC clocked by LSE
bypassed at 32768 Hz
1.8 V 210 378 1299 3437 9357 - - - - -
nA
2.4 V 303 499 1577 4056 10825 - - - - -
3 V 422 655 1925 4820 12569 - - - - -
3.6 V 584 888 2511 6158 15706 - - - - -
RTC clocked by LSE
quartz (2) in low drive
mode
1.8 V 329 499 1408 3460 - - - - - -
2.4 V 431 634 1688 4064 - - - - - -
3 V 554 791 2025 4795 - - - - - -
3.6 V 729 1040 2619 6129 - - - - - -
IDD_ALL
(wakeup from
Shutdown)
Supply current
during wakeup
from Shutdown
mode
Wakeup clock is
MSI = 4 MHz.
See (3).
3 V 0.6 - - - - - - - - - mA
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 42: Low-power mode wakeup timings.
Table 39. Current consumption in Shutdown mode (continued)
Symbol Parameter
Conditions TYP MAX(1)
Unit
-V
DD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
STM32L471xx Electrical characteristics
DS10741 Rev 2 119/229
Table 40. Current consumption in VBAT mode
Symbol Parameter
Conditions TYP MAX(1)
Unit
-V
BAT 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
IDD_VBAT
Backup domain
supply current
RTC disabled
1.8 V 4 29 196 587 1663 10.8 73 490 1468 4158
nA
2.4 V 5.27 36 226 673 1884 13.2 90 565 1683 4710
3 V 6 42 264 775 2147 15.5 106 660 1938 5368
3.6 V 10 58 323 919 2488 25.8 144 808 2298 6220
RTC enabled and
clocked by LSE
bypassed at 32768 Hz
1.8 V 183 201 367 729 - - - - - -
2.4 V 268 295 486 901 - - - - - -
3 V 376 412 602 1075 - - - - - -
3.6 V 508 558 752 1299 - - - - - -
RTC enabled and
clocked by LSE
quartz(2)
1.8 V 302 344 521 915 1978 - - - - -
2.4 V 388 436 639 1091 2289 - - - - -
3 V 494 549 784 1301 2656 - - - - -
3.6 V 630 692 971 1571 3115 - - - - -
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
Electrical characteristics STM32L471xx
120/229 DS10741 Rev 2
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 60: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 41: Peripheral current consumption), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDIOx is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
ISW VDDIOx fSW C××=
DS10741 Rev 2 121/229
STM32L471xx Electrical characteristics
206
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 41. The MCU is placed
under the following conditions:
•All I/O pins are in Analog mode
•The given value is calculated by measuring the difference of the current consumptions:
– when the peripheral is clocked on
– when the peripheral is clocked off
•Ambient operating temperature and supply voltage conditions summarized in Table 20:
Voltage characteristics
•The power consumption of the digital part of the on-chip peripherals is given in
Table 41. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 41. Peripheral current consumption
Peripheral Range 1 Range 2 Low-power run
and sleep Unit
AHB
Bus Matrix(1) 4.5 3.7 4.1
µA/MHz
ADC independent clock domain 0.4 0.1 0.2
ADC AHB clock domain 5.5 4.7 5.5
CRC 0.4 0.2 0.3
DMA1 1.4 1.3 1.4
DMA2 1.5 1.3 1.4
FLASH 6.2 5.2 5.8
FMC 8.9 7.5 8.4
GPIOA(2) 4.8 3.8 4.4
GPIOB(2) 4.8 4.0 4.6
GPIOC(2) 4.5 3.8 4.3
GPIOD(2) 4.6 3.9 4.4
GPIOE(2) 5.2 4.5 4.9
GPIOF(2) 5.9 4.9 5.7
GPIOG(2) 4.3 3.8 4.2
GPIOH(2) 0.7 0.6 0.8
QUADSPI 7.8 6.7 7.3
RNG independent clock domain 2.2 N/A N/A
RNG AHB clock domain 0.6 N/A N/A
SRAM1 0.9 0.8 0.9
AHB
SRAM2 1.6 1.4 1.6
µA/MHzTSC 1.8 1.4 1.6
All AHB Peripherals 118.5 77.3 87.6
Electrical characteristics STM32L471xx
122/229 DS10741 Rev 2
APB1
AHB to APB1 bridge(3) 0.9 0.7 0.9
µA/MHz
CAN1 4.6 4.0 4.4
DAC1 2.4 1.9 2.2
I2C1 independent clock domain 3.7 3.1 3.2
I2C1 APB clock domain 1.3 1.1 1.5
I2C2 independent clock domain 3.7 3.0 3.2
I2C2 APB clock domain 1.4 1.1 1.5
I2C3 independent clock domain 2.9 2.3 2.5
I2C3 APB clock domain 0.9 0.9 1.1
LPUART1 independent clock
domain 2.1 1.6 2.0
LPUART1 APB clock domain 0.6 0.6 0.6
LPTIM1 independent clock
domain 3.3 2.6 2.9
LPTIM1 APB clock domain 0.9 0.8 1.0
LPTIM2 independent clock
domain 3.1 2.7 2.9
LPTIM2 APB clock domain 0.8 0.6 0.7
OPAMP 0.4 0.4 0.3
PWR 0.5 0.5 0.4
SPI2 1.8 1.6 1.6
SPI3 2.1 1.7 1.8
SWPMI1 independent clock
domain 2.3 1.8 2.2
SWPMI1 APB clock domain 1.1 1.1 1.0
TIM2 6.8 5.7 6.3
TIM3 5.4 4.6 5.0
TIM4 5.2 4.4 4.9
TIM5 6.5 5.5 6.1
TIM6 1.1 1.0 1.0
TIM7 1.1 0.9 1.0
Table 41. Peripheral current consumption (continued)
Peripheral Range 1 Range 2 Low-power run
and sleep Unit
DS10741 Rev 2 123/229
STM32L471xx Electrical characteristics
206
APB1
USART2 independent clock
domain 4.1 3.6 3.8
µA/MHz
USART2 APB clock domain 1.4 1.1 1.5
USART3 independent clock
domain 4.7 4.1 4.2
USART3 APB clock domain 1.5 1.3 1.7
UART4 independent clock
domain 3.9 3.2 3.5
UART4 APB clock domain 1.5 1.3 1.6
UART5 independent clock
domain 3.9 3.2 3.5
UART5 APB clock domain 1.3 1.2 1.4
WWDG 0.5 0.5 0.5
All APB1 on 84.2 70.7 80.2
APB2
AHB to APB2 bridge(4) 1.0 0.9 0.9
DFSDM1 5.6 4.6 5.3
FW 0.7 0.5 0.7
SAI1 independent clock domain 2.6 2.1 2.3
SAI1 APB clock domain 2.1 1.8 2.0
SAI2 independent clock domain 3.3 2.7 3.0
SAI2 APB clock domain 2.4 2.1 2.2
SDMMC1 independent clock
domain 4.7 3.9 4.2
SDMMC1 APB clock domain 2.5 1.9 2.1
SPI1 2.0 1.6 1.9
SYSCFG/VREFBUF/COMP 0.6 0.4 0.5
TIM1 8.3 6.9 7.9
TIM8 8.6 7.1 8.1
TIM15 4.1 3.4 3.9
TIM16 3.0 2.5 2.9
TIM17 3.0 2.4 2.9
USART1 independent clock
domain 4.9 4.0 4.4
USART1 APB clock domain 1.5 1.3 1.7
All APB2 on 56.8 43.3 48.2
ALL 256.8 189.6 215.5
Table 41. Peripheral current consumption (continued)
Peripheral Range 1 Range 2 Low-power run
and sleep Unit
Electrical characteristics STM32L471xx
124/229 DS10741 Rev 2
6.3.6 Wakeup time from low-power modes and voltage scaling
transition times
The wakeup times given in Table 42 are the latency between the event and the execution of
the first user instruction.
The device goes in low-power mode after the WFE (Wait For Event) instruction.
1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).
2. The GPIOx (x= A…H) dynamic current consumption is approximately divided by a factor two versus this table values when
the GPIO port is locked thanks to LCKK and LCKy bits in the GPIOx_LCKR register. In order to save the full GPIOx current
consumption, the GPIOx clock should be disabled in the RCC when all port I/Os are used in alternate function or analog
mode (clock is only required to read or write into GPIO registers, and is not used in AF or analog modes).
3. The AHB to APB1 Bridge is automatically active when at least one peripheral is ON on the APB1.
4. The AHB to APB2 Bridge is automatically active when at least one peripheral is ON on the APB2.
Table 42. Low-power mode wakeup timings(1)
Symbol Parameter Conditions Typ Max Unit
tWUSLEEP
Wakeup time from Sleep
mode to Run mode -66
Nb of
CPU
cycles
tWULPSLEEP
Wakeup time from Low-
power sleep mode to Low-
power run mode
Wakeup in Flash with Flash in power-down during
low-power sleep mode (SLEEP_PD=1 in
FLASH_ACR) and with clock MSI = 2 MHz
69.3
tWUSTOP0
Wake up time from Stop 0
mode to Run mode in Flash
Range 1
Wakeup clock MSI = 48 MHz 5.6 10.9
µs
Wakeup clock HSI16 = 16 MHz 4.7 10.4
Range 2
Wakeup clock MSI = 24 MHz 5.7 11.1
Wakeup clock HSI16 = 16 MHz 4.5 10.5
Wakeup clock MSI = 4 MHz 6.6 14.2
Wake up time from Stop 0
mode to Run mode in
SRAM1
Range 1
Wakeup clock MSI = 48 MHz 0.7 2.05
Wakeup clock HSI16 = 16 MHz 1.7 2.8
Range 2
Wakeup clock MSI = 24 MHz 0.8 2.72
Wakeup clock HSI16 = 16 MHz 1.7 2.8
Wakeup clock MSI = 4 MHz 2.4 11.32
DS10741 Rev 2 125/229
STM32L471xx Electrical characteristics
206
tWUSTOP1
Wake up time from Stop 1
mode to Run mode in Flash
Range 1
Wakeup clock MSI = 48 MHz 6.2 10.2
µs
Wakeup clock HSI16 = 16 MHz 6.3 8.99
Range 2
Wakeup clock MSI = 24 MHz 6.3 10.46
Wakeup clock HSI16 = 16 MHz 6.3 8.87
Wakeup clock MSI = 4 MHz 8.0 13.23
Wake up time from Stop 1
mode to Run mode in
SRAM1
Range 1
Wakeup clock MSI = 48 MHz 4.5 5.78
Wakeup clock HSI16 = 16 MHz 5.5 7.1
Range 2
Wakeup clock MSI = 24 MHz 5.0 6.5
Wakeup clock HSI16 = 16 MHz 5.5 7.1
Wakeup clock MSI = 4 MHz 8.2 13.5
Wake up time from Stop 1
mode to Low-power run
mode in Flash Regulator in
low-power
mode (LPR=1 in
PWR_CR1)
Wakeup clock MSI = 2 MHz
12.7 20
Wake up time from Stop 1
mode to Low-power run
mode in SRAM1
10.7 21.5
tWUSTOP2
Wake up time from Stop 2
mode to Run mode in Flash
Range 1
Wakeup clock MSI = 48 MHz 8.0 9.4
µs
Wakeup clock HSI16 = 16 MHz 7.3 9.3
Range 2
Wakeup clock MSI = 24 MHz 8.2 9.9
Wakeup clock HSI16 = 16 MHz 7.3 9.3
Wakeup clock MSI = 4 MHz 10.6 15.8
Wake up time from Stop 2
mode to Run mode in
SRAM1
Range 1
Wakeup clock MSI = 48 MHz 5.1 6.7
Wakeup clock HSI16 = 16 MHz 5.7 8
Range 2
Wakeup clock MSI = 24 MHz 5.5 6.65
Wakeup clock HSI16 = 16 MHz 5.7 7.53
Wakeup clock MSI = 4 MHz 8.2 16.6
tWUSTBY
Wakeup time from Standby
mode to Run mode Range 1
Wakeup clock MSI = 8 MHz 14.3 20.8
µs
Wakeup clock MSI = 4 MHz 20.1 35.5
tWUSTBY
SRAM2
Wakeup time from Standby
with SRAM2 to Run mode Range 1
Wakeup clock MSI = 8 MHz 14.3 24.3
µs
Wakeup clock MSI = 4 MHz 20.1 38.5
tWUSHDN
Wakeup time from
Shutdown mode to Run
mode
Range 1 Wakeup clock MSI = 4 MHz 256 330.6 µs
1. Guaranteed by characterization results.
Table 42. Low-power mode wakeup timings(1) (continued)
Symbol Parameter Conditions Typ Max Unit
Electrical characteristics STM32L471xx
126/229 DS10741 Rev 2
6.3.7 External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 17: High-speed external clock
source AC timing diagram.
Table 43. Regulator modes transition times(1)
Symbol Parameter Conditions Typ Max Unit
tWULPRUN
Wakeup time from Low-power run mode to
Run mode(2) Code run with MSI 2 MHz 5 7
µs
tVOST
Regulator transition time from Range 2 to
Range 1 or Range 1 to Range 2(3) Code run with MSI 24 MHz 20 40
1. Guaranteed by characterization results.
2. Time until REGLPF flag is cleared in PWR_SR2.
3. Time until VOSF flag is cleared in PWR_SR2.
Table 44. Wakeup time using USART/LPUART(1)
Symbol Parameter Conditions Typ Max Unit
tWUUSART
tWULPUART
Wakeup time needed to calculate the
maximum USART/LPUART baudrate
allowing to wakeup up from stop mode
when USART/LPUART clock source is
HSI16
Stop 0 mode - 1.7
µs
Stop 1 mode and Stop 2
mode -8.5
1. Guaranteed by design.
Table 45. High-speed external user clock characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fHSE_ext User external clock source frequency
Voltage scaling
Range 1 -848
MHz
Voltage scaling
Range 2 -826
VHSEH OSC_IN input pin high level voltage - 0.7 VDDIOx -V
DDIOx V
VHSEL OSC_IN input pin low level voltage - VSS - 0.3 VDDIOx
tw(HSEH)
tw(HSEL)
OSC_IN high or low time
Voltage scaling
Range 1 7- -
ns
Voltage scaling
Range 2 18 - -
1. Guaranteed by design.
DS10741 Rev 2 127/229
STM32L471xx Electrical characteristics
206
Figure 17. High-speed external clock source AC timing diagram
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 18.
Figure 18. Low-speed external clock source AC timing diagram
MS19214V2
VHSEH
tf(HSE)
90%
10%
THSE
t
tr(HSE)
VHSEL
tw(HSEH)
tw(HSEL)
Table 46. Low-speed external user clock characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fLSE_ext User external clock source frequency - - 32.768 1000 kHz
VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIOx -V
DDIOx V
VLSEL OSC32_IN input pin low level voltage - VSS -0.3 V
DDIOx
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time - 250 - - ns
1. Guaranteed by design.
MS19215V2
VLSEH
tf(LSE)
90%
10%
TLSE
t
tr(LSE)
VLSEL
tw(LSEH)
tw(LSEL)
Electrical characteristics STM32L471xx
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High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 47. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 19). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Table 47. HSE oscillator characteristics(1)
1. Guaranteed by design.
Symbol Parameter Conditions(2)
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
Min Typ Max Unit
fOSC_IN Oscillator frequency - 4 8 48 MHz
RFFeedback resistor - - 200 - k
IDD(HSE) HSE current consumption
During startup(3)
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
--5.5
mA
VDD = 3 V,
Rm = 30 ,
CL = 10 pF@8 MHz
-0.44-
VDD = 3 V,
Rm = 45 ,
CL = 10 pF@8 MHz
-0.45-
VDD = 3 V,
Rm = 30 ,
CL = 5 pF@48 MHz
-0.68-
VDD = 3 V,
Rm = 30 ,
CL = 10 pF@48 MHz
-0.94-
VDD = 3 V,
Rm = 30 ,
CL = 20 pF@48 MHz
-1.77-
Gm
Maximum critical crystal
transconductance Startup - - 1.5 mA/V
tSU(HSE)(4)
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
Startup time VDD is stabilized - 2 - ms
DS10741 Rev 2 129/229
STM32L471xx Electrical characteristics
206
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 19. Typical application with an 8 MHz crystal
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 48. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
MS19876V1
(1)
OSC_IN
OSC_OUT
RF
Bias
controlled
gain
fHSE
REXT
8 MHz
resonator
Resonator with integrated
capacitors
CL1
CL2
Table 48. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)
Symbol Parameter Conditions(2) Min Typ Max Unit
IDD(LSE) LSE current consumption
LSEDRV[1:0] = 00
Low drive capability -250-
nA
LSEDRV[1:0] = 01
Medium low drive capability -315-
LSEDRV[1:0] = 10
Medium high drive capability -500-
LSEDRV[1:0] = 11
High drive capability -630-
Gmcritmax
Maximum critical crystal
gm
LSEDRV[1:0] = 00
Low drive capability --0.5
µA/V
LSEDRV[1:0] = 01
Medium low drive capability - - 0.75
LSEDRV[1:0] = 10
Medium high drive capability --1.7
LSEDRV[1:0] = 11
High drive capability --2.7
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
Electrical characteristics STM32L471xx
130/229 DS10741 Rev 2
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 20. Typical application with a 32.768 kHz crystal
Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
MS30253V2
OSC32_IN
OSC32_OUT
Drive
programmable
amplifier
fLSE
32.768 kHz
resonator
Resonator with integrated
capacitors
CL1
CL2
DS10741 Rev 2 131/229
STM32L471xx Electrical characteristics
206
6.3.8 Internal clock source characteristics
The parameters given in Table 49 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 23: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI16) RC oscillator
Table 49. HSI16 oscillator characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fHSI16 HSI16 Frequency VDD=3.0 V, TA=30 °C 15.88 - 16.08 MHz
TRIM HSI16 user trimming step
Trimming code is not a
multiple of 64 0.2 0.3 0.4
%
Trimming code is a
multiple of 64 -4 -6 -8
DuCy(HSI16)(2) Duty Cycle - 45 - 55 %
Tem p (HSI16) HSI16 oscillator frequency
drift over temperature
TA= 0 to 85 °C -1 - 1 %
TA= -40 to 125 °C -2 - 1.5 %
VDD(HSI16) HSI16 oscillator frequency
drift over VDD
VDD=1.62 V to 3.6 V -0.1 - 0.05 %
tsu(HSI16)(2) HSI16 oscillator start-up
time --0.81.2s
tstab(HSI16)(2) HSI16 oscillator
stabilization time --35s
IDD(HSI16)(2) HSI16 oscillator power
consumption - - 155 190 A
1. Guaranteed by characterization results.
2. Guaranteed by design.
DS10741 Rev 2 133/229
STM32L471xx Electrical characteristics
206
Multi-speed internal (MSI) RC oscillator
Table 50. MSI oscillator characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fMSI
MSI frequency
after factory
calibration, done
at VDD=3 V and
TA=30 °C
MSI mode
Range 0 99 100 101
kHz
Range 1 198 200 202
Range 2 396 400 404
Range 3 792 800 808
Range 4 0.99 1 1.01
MHz
Range 5 1.98 2 2.02
Range 6 3.96 4 4.04
Range 7 7.92 8 8.08
Range 8 15.8 16 16.16
Range 9 23.8 24 24.4
Range 10 31.7 32 32.32
Range 11 47.5 48 48.48
PLL mode
XTAL=
32.768 kHz
Range 0 - 98.304 -
kHz
Range 1 - 196.608 -
Range 2 - 393.216 -
Range 3 - 786.432 -
Range 4 - 1.016 -
MHz
Range 5 - 1.999 -
Range 6 - 3.998 -
Range 7 - 7.995 -
Range 8 - 15.991 -
Range 9 - 23.986 -
Range 10 - 32.014 -
Range 11 - 48.005 -
TEMP(MSI)(2)
MSI oscillator
frequency drift
over temperature
MSI mode
TA= -0 to 85 °C -3.5 - 3
%
TA= -40 to 125 °C -8 - 6
Electrical characteristics STM32L471xx
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VDD(MSI)(2)
MSI oscillator
frequency drift
over VDD
(reference is 3 V)
MSI mode
Range 0 to 3
VDD=1.62 V
to 3.6 V -1.2 -
0.5
%
VDD=2.4 V
to 3.6 V -0.5 -
Range 4 to 7
VDD=1.62 V
to 3.6 V -2.5 -
0.7
VDD=2.4 V
to 3.6 V -0.8 -
Range 8 to 11
VDD=1.62 V
to 3.6 V -5 -
1
VDD=2.4 V
to 3.6 V -1.6 -
FSAMPLING
(MSI)(2)(4)
Frequency
variation in
sampling mode(3)
MSI mode
TA= -40 to 85 °C - 1 2
%
TA= -40 to 125 °C - 2 4
CC jitter(MSI)(4) RMS cycle-to-
cycle jitter PLL mode Range 11 - - 60 - ps
P jitter(MSI)(4) RMS Period jitter PLL mode Range 11 - - 50 - ps
tSU(MSI)(4) MSI oscillator
start-up time
Range 0 - - 10 20
us
Range 1 - - 5 10
Range 2 - - 4 8
Range 3 - - 3 7
Range 4 to 7 - - 3 6
Range 8 to 11 - - 2.5 6
tSTAB(MSI)(4) MSI oscillator
stabilization time
PLL mode
Range 11
10 % of final
frequency - - 0.25 0.5
ms
5 % of final
frequency --0.51.25
1 % of final
frequency ---2.5
Table 50. MSI oscillator characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
[HA] +RangeDt03—O—Rang24tu7+Range$lull
256
128
54
32
16
3 lMHz
IDDKHZ SOGKHZ
0‘5
0‘1 {12 0.4 0.8 L6
3.2
BMHZ
6.4
16MHZ
12.8
256
48MHz
Freq
[MHz]
DS10741 Rev 2 135/229
STM32L471xx Electrical characteristics
206
Figure 22. Typical current consumption versus MSI frequency
IDD(MSI)(4)
MSI oscillator
power
consumption
MSI and
PLL mode
Range 0 - - 0.6 1
µA
Range 1 - - 0.8 1.2
Range 2 - - 1.2 1.7
Range 3 - - 1.9 2.5
Range 4 - - 4.7 6
Range 5 - - 6.5 9
Range 6 - - 11 15
Range 7 - - 18.5 25
Range 8 - - 62 80
Range 9 - - 85 110
Range 10 - - 110 130
Range 11 - - 155 190
1. Guaranteed by characterization results.
2. This is a deviation for an individual part once the initial frequency has been measured.
3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.
4. Guaranteed by design.
Table 50. MSI oscillator characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
Electrical characteristics STM32L471xx
136/229 DS10741 Rev 2
Low-speed internal (LSI) RC oscillator
6.3.9 PLL characteristics
The parameters given in Table 52 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 23: General operating conditions.
Table 51. LSI oscillator characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fLSI LSI Frequency
VDD = 3.0 V, TA = 30 °C 31.04 - 32.96
kHz
VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 29.5 - 34
tSU(LSI)(2) LSI oscillator start-
up time --80130s
tSTAB(LSI)(2) LSI oscillator
stabilization time 5% of final frequency - 125 180 s
IDD(LSI)(2) LSI oscillator power
consumption --110180nA
1. Guaranteed by characterization results.
2. Guaranteed by design.
Table 52. PLL, PLLSAI1, PLLSAI2 characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fPLL_IN
PLL input clock(2) -4-16MHz
PLL input clock duty cycle - 45 - 55 %
fPLL_P_OUT PLL multiplier output clock P Voltage scaling Range 1 2.0645 - 80 MHz
Voltage scaling Range 2 2.0645 - 26
fPLL_Q_OUT PLL multiplier output clock Q Voltage scaling Range 1 8 - 80 MHz
Voltage scaling Range 2 8 - 26
fPLL_R_OUT PLL multiplier output clock R Voltage scaling Range 1 8 - 80 MHz
Voltage scaling Range 2 8 - 26
fVCO_OUT PLL VCO output Voltage scaling Range 1 64 - 344 MHz
Voltage scaling Range 2 64 - 128
tLOCK PLL lock time - - 15 40 s
Jitter RMS cycle-to-cycle jitter System clock 80 MHz -40-
±ps
RMS period jitter - 30 -
IDD(PLL) PLL power consumption on
VDD(1)
VCO freq = 64 MHz - 150 200
A
VCO freq = 96 MHz - 200 260
VCO freq = 192 MHz - 300 380
VCO freq = 344 MHz - 520 650
1. Guaranteed by design.
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between the 3 PLLs.
DS10741 Rev 2 137/229
STM32L471xx Electrical characteristics
206
6.3.10 Flash memory characteristics
Table 53. Flash memory characteristics(1)
1. Guaranteed by design.
Symbol Parameter Conditions Typ Max Unit
tprog 64-bit programming time - 81.69 90.76 µs
tprog_row
one row (32 double
word) programming time
normal programming 2.61 2.90
ms
fast programming 1.91 2.12
tprog_page
one page (2 Kbyte)
programming time
normal programming 20.91 23.24
fast programming 15.29 16.98
tERASE Page (2 KB) erase time - 22.02 24.47
tprog_bank
one bank (512 Kbyte)
programming time
normal programming 5.35 5.95
s
fast programming 3.91 4.35
tME
Mass erase time
(one or two banks) - 22.13 24.59 ms
IDD
Average consumption
from VDD
Write mode 3.4 -
mA
Erase mode 3.4 -
Maximum current (peak)
Write mode 7 (for 2 s) -
Erase mode 7 (for 41 s) -
Table 54. Flash memory endurance and data retention
Symbol Parameter Conditions Min(1)
1. Guaranteed by characterization results.
Unit
NEND Endurance TA = –40 to +105 °C 10 kcycles
tRET Data retention
1 kcycle(2) at TA = 85 °C
2. Cycling performed over the whole temperature range.
30
Years
1 kcycle(2) at TA = 105 °C 15
1 kcycle(2) at TA = 125 °C 7
10 kcycles(2) at TA = 55 °C 30
10 kcycles(2) at TA = 85 °C 15
10 kcycles(2) at TA = 105 °C 10
Electrical characteristics STM32L471xx
138/229 DS10741 Rev 2
6.3.11 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 55. They are based on the EMS levels and classes
defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•Corrupted program counter
•Unexpected reset
•Critical Data corruption (control registers...)
Table 55. EMS characteristics
Symbol Parameter Conditions Level/
Class
VFESD
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VDD = 3.3 V, TA = +25 °C,
fHCLK = 80 MHz,
conforming to IEC 61000-4-2
3B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, TA = +25 °C,
fHCLK = 80 MHz,
conforming to IEC 61000-4-4
4A
DS10741 Rev 2 139/229
STM32L471xx Electrical characteristics
206
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
6.3.12 Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 56. EMI characteristics
Symbol Parameter Conditions Monitored
frequency band
Max vs. [fHSE/fHCLK]
Unit
fMSI = 24 MHz 8 MHz / 80 MHz
SEMI Peak level
VDD = 3.6 V, TA = 25 °C,
LQFP144 package
compliant with
IEC 61967-2
0.1 MHz to 30 MHz -9 2
dBµV30 MHz to 130 MHz -8 3
130 MHz to 1 GHz -10 14
EMI Level 1.5 3.5 -
Table 57. ESD absolute maximum ratings
Symbol Ratings Conditions Class Maximum
value(1)
1. Guaranteed by characterization results.
Unit
VESD(HBM)
Electrostatic discharge
voltage (human body model)
TA = +25 °C, conforming
to ANSI/ESDA/JEDEC
JS-001
2 2000
V
VESD(CDM)
Electrostatic discharge
voltage (charge device
model)
TA = +25 °C,
conforming to ANSI/ESD
STM5.3.1
C3 250
Electrical characteristics STM32L471xx
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Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•A supply overvoltage is applied to each power supply pin.
•A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
6.3.13 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 59.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
Table 58. Electrical sensitivities
Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 °C conforming to JESD78A II level A(1)
1. Negative injection is limited to -30 mA for PF0, PF1, PG6, PG7, PG8, PG12, PG13, PG14.
Table 59. I/O current injection susceptibility
Symbol Description
Functional
susceptibility
Unit
Negative
injection
Positive
injection
IINJ
Injected current on BOOT0 pin -0 0
mAInjected current on pins except PA4, PA5, BOOT0 -5 N/A(1)
1. Injection is not possible.
Injected current on PA4, PA5 pins -5 0
DS10741 Rev 2 141/229
STM32L471xx Electrical characteristics
206
6.3.14 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 60 are derived from tests
performed under the conditions summarized in Table 23: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant (except BOOT0).
Table 60. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL(1)
I/O input low level
voltage except
BOOT0
1.62 V<VDDIOx<3.6 V - - 0.3xVDDIOx(2)
V
I/O input low level
voltage except
BOOT0
1.62 V<VDDIOx<3.6 V - - 0.39xVDDIOx-0.06(3)
I/O input low level
voltage except
BOOT0
1.08 V<VDDIOx<1.62 V - - 0.43xVDDIOx-0.1(3)
BOOT0 I/O input low
level voltage 1.62 V<VDDIOx<3.6 V - - 0.17xVDDIOx(3)
VIH(1)
I/O input high level
voltage except
BOOT0
1.62 V<VDDIOx<3.6 V 0.7xVDDIOx(2) --
V
I/O input high level
voltage except
BOOT0
1.62 V<VDDIOx<3.6 V 0.49xVDDIOX+0.26(3) --
I/O input high level
voltage except
BOOT0
1.08 V<VDDIOx<1.62 V 0.61xVDDIOX+0.05(3) --
BOOT0 I/O input high
level voltage 1.62 V<VDDIOx<3.6 V 0.77xVDDIOX(3) --
Vhys(3)
TT_xx, FT_xxx and
NRST I/O input
hysteresis
1.62 V<VDDIOx<3.6 V - 200 -
mV
FT_sx 1.08 V<VDDIOx<1.62 V - 150 -
BOOT0 I/O input
hysteresis 1.62 V<VDDIOx<3.6 V - 200 -
Electrical characteristics STM32L471xx
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Ilkg(4)
FT_xx input leakage
current(3)(5)
VIN
Max(VDDXXX)(6)(7) - - ±100
nA
Max(VDDXXX) VIN
Max(VDDXXX)+1 V(6)(7) --650
Max(VDDXXX)+1 V <
VIN 5.5 V(6)(7) --200
PA9, PA10, PA11,
PA12 and PC3 I/Os
VIN Max(VDDXXX)
(6)(7) - - ±150
Max(VDDXXX) VIN
Max(VDDXXX)+1 V(6)(7) - - 2500(3)
Max(VDDXXX)+1 V <
VIN 5.5 V(6)(7) --250
TT_xx input leakage
current
VIN Max(VDDXXX)(6) - - ±150
Max(VDDXXX) VIN <
3.6 V(6) - - 2000(3)
OPAMPx_VINM
(x=1,2) dedicated
input leakage current
(UFBGA132 and
UFBGA144 only)
---
(8)
RPU
Weak pull-up
equivalent resistor (9) VIN = VSS 25 40 55 k
RPD
Weak pull-down
equivalent resistor(9) VIN = VDDIOx 25 40 55 k
CIO I/O pin capacitance - - 5 - pF
1. Refer to Figure 23: I/O input characteristics.
2. Guaranteed by test in production.
3. Guaranteed by design.
4. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula:
ITotal_Ileak_max = 10 µA + [number of IOs where VIN is applied on the pad] Ilkg(Max).
5. All FT_xx GPIOs except PA9, PA10, PA11, PA12 and PC3 I/Os.
6. Max(VDDXXX) is the maximum value of all the I/O supplies.
7. To sustain a voltage higher than Min(VDD, VDDA, VDDIO2) +0.3 V, the internal Pull-up and Pull-Down resistors must be
disabled.
8. Refer to Ibias in Table 76: OPAMP characteristics for the values of the OPAMP dedicated input leakage current.
9. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
Table 60. I/O static characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
V‘I-Vih 3“ IO except BOOTD
3
2 5
2 ,.‘
—vH spec 30%
g —vm spec 70%
g 1 5 —vH spec «1
§ / —vm spec m
—VIl_Me
‘ ’ —vm_m>e
a 5
u
1 1 5 2.5 3 3'5
DS10741 Rev 2 143/229
STM32L471xx Electrical characteristics
206
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 23 for standard I/Os, and in Figure 23 for
5 V tolerant I/Os.
Figure 23. I/O input characteristics
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ± 20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 20: Voltage characteristics).
•The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating IVSS (see
Table 20: Voltage characteristics).
MSv37613V1
Tested in production CMOS requirement Vih min = 0.7xVDDIOx
Based on simulation Vih min = 0.61xV
DDIOx
+0.05 for 1.08<V
DDIOx
<1.62 or 0.49xV
DDIOx
+0.26 for V
DDIOx
>1.62
Based on simulation Vil max =0.43xV
DDIOx
-0.1 for 1.08<V
DDIOx
<1.62 or 0.39xV
DDIOx
-0.06 for V
DDIOx
>1.62
Tested in production CMOS requirement Vil max = 0.3xVdd
TTL requirement Vih min = 2V
TTL requirement Vil max = 0.8V
Electrical characteristics STM32L471xx
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Output voltage levels
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 23: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT
unless otherwise specified).
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 24 and
Table 62, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 23: General
operating conditions.
Table 61. Output voltage characteristics(1)
Symbol Parameter Conditions Min Max Unit
VOL Output low level voltage for an I/O pin CMOS port(2)
|IIO| = 8 mA
VDDIOx 2.7 V
-0.4
V
VOH Output high level voltage for an I/O pin VDDIOx-0.4 -
VOL(3) Output low level voltage for an I/O pin TTL port(2)
|IIO| = 8 mA
VDDIOx 2.7 V
-0.4
VOH(3) Output high level voltage for an I/O pin 2.4 -
VOL(3) Output low level voltage for an I/O pin |IIO| = 20 mA
VDDIOx 2.7 V
-1.3
VOH(3) Output high level voltage for an I/O pin VDDIOx-1.3 -
VOL(3) Output low level voltage for an I/O pin |IIO| = 4 mA
VDDIOx 1.62 V
-0.45
VOH(3) Output high level voltage for an I/O pin VDDIOx-0.45 -
VOL(3) Output low level voltage for an I/O pin |IIO| = 2 mA
1.62 V VDDIOx 1.08 V
-0.35VDDIOx
VOH(3) Output high level voltage for an I/O pin 0.65VDDIOx -
VOLFM+
(3)
Output low level voltage for an FT I/O
pin in FM+ mode (FT I/O with "f"
option)
|IIO| = 20 mA
VDDIOx 2.7 V -0.4
|IIO| = 10 mA
VDDIOx 1.62 V -0.4
|IIO| = 2 mA
1.62 V VDDIOx 1.08 V -0.4
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 20:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings IIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
DS10741 Rev 2 145/229
STM32L471xx Electrical characteristics
206
Table 62. I/O AC characteristics(1)(2)
Speed Symbol Parameter Conditions Min Max Unit
00
Fmax Maximum frequency
C=50 pF, 2.7 VVDDIOx3.6 V - 5
MHz
C=50 pF, 1.62 VVDDIOx2.7 V - 1
C=50 pF, 1.08 VVDDIOx1.62 V - 0.1
C=10 pF, 2.7 VVDDIOx3.6 V - 10
C=10 pF, 1.62 VVDDIOx2.7 V - 1.5
C=10 pF, 1.08 VVDDIOx1.62 V - 0.1
Tr/Tf Output rise and fall time
C=50 pF, 2.7 VVDDIOx3.6 V - 25
ns
C=50 pF, 1.62 VVDDIOx2.7 V - 52
C=50 pF, 1.08 VVDDIOx1.62 V - 140
C=10 pF, 2.7 VVDDIOx3.6 V - 17
C=10 pF, 1.62 VVDDIOx2.7 V - 37
C=10 pF, 1.08 VVDDIOx1.62 V - 110
01
Fmax Maximum frequency
C=50 pF, 2.7 VVDDIOx3.6 V - 25
MHz
C=50 pF, 1.62 VVDDIOx2.7 V - 10
C=50 pF, 1.08 VVDDIOx1.62 V - 1
C=10 pF, 2.7 VVDDIOx3.6 V - 50
C=10 pF, 1.62 VVDDIOx2.7 V - 15
C=10 pF, 1.08 VVDDIOx1.62 V - 1
Tr/Tf Output rise and fall time
C=50 pF, 2.7 VVDDIOx3.6 V - 9
ns
C=50 pF, 1.62 VVDDIOx2.7 V - 16
C=50 pF, 1.08 VVDDIOx1.62 V - 40
C=10 pF, 2.7 VVDDIOx3.6 V - 4.5
C=10 pF, 1.62 VVDDIOx2.7 V - 9
C=10 pF, 1.08 VVDDIOx1.62 V - 21
Electrical characteristics STM32L471xx
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10
Fmax Maximum frequency
C=50 pF, 2.7 VVDDIOx3.6 V - 50
MHz
C=50 pF, 1.62 VVDDIOx2.7 V - 25
C=50 pF, 1.08 VVDDIOx1.62 V - 5
C=10 pF, 2.7 VVDDIOx3.6 V - 100(3)
C=10 pF, 1.62 VVDDIOx2.7 V - 37.5
C=10 pF, 1.08 VVDDIOx1.62 V - 5
Tr/Tf Output rise and fall time
C=50 pF, 2.7 VVDDIOx3.6 V - 5.8
ns
C=50 pF, 1.62 VVDDIOx2.7 V - 11
C=50 pF, 1.08 VVDDIOx1.62 V - 28
C=10 pF, 2.7 VVDDIOx3.6 V - 2.5
C=10 pF, 1.62 VVDDIOx2.7 V - 5
C=10 pF, 1.08 VVDDIOx1.62 V - 12
11
Fmax Maximum frequency
C=30 pF, 2.7 VVDDIOx3.6 V - 120(3)
MHz
C=30 pF, 1.62 VVDDIOx2.7 V - 50
C=30 pF, 1.08 VVDDIOx1.62 V - 10
C=10 pF, 2.7 VVDDIOx3.6 V - 180(3)
C=10 pF, 1.62 VVDDIOx2.7 V - 75
C=10 pF, 1.08 VVDDIOx1.62 V - 10
Tr/Tf Output rise and fall time
C=30 pF, 2.7 VVDDIOx3.6 V - 3.3
nsC=30 pF, 1.62 VVDDIOx2.7 V - 6
C=30 pF, 1.08 VVDDIOx1.62 V - 16
Fm+
Fmax Maximum frequency
C=50 pF, 1.6 VVDDIOx3.6 V
-1MHz
Tf Output fall time(4) -5ns
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.
Refer to the RM0392 reference manual for a description of GPIO Port configuration register.
2. Guaranteed by design.
3. This value represents the I/O capability but the maximum system frequency is limited to 80 MHz.
4. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.
Table 62. I/O AC characteristics(1)(2) (continued)
Speed Symbol Parameter Conditions Min Max Unit
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STM32L471xx Electrical characteristics
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Figure 24. I/O AC characteristics definition(1)
1. Refer to Table 62: I/O AC characteristics.
6.3.15 NRST pin characteristics
The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 23: General operating conditions.
MS32132V2
T
10%
50%
90% 10%
50%
90%
Maximum frequency is achieved if (t + t (≤ 2/3)T and if the duty cycle is (45-55%)
when loaded by the specified capacitance.
rf
r(IO)out
tf(IO)out
t
Table 63. NRST pin characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
VIL(NRST)
NRST input low level
voltage ---0.3VDDIOx
V
VIH(NRST)
NRST input high level
voltage -0.7VDDIOx --
Vhys(NRST)
NRST Schmitt trigger
voltage hysteresis --200-mV
RPU
Weak pull-up
equivalent resistor(2) VIN = VSS 25 40 55 k
VF(NRST) NRST input filtered
pulse ---70ns
VNF(NRST)
NRST input not filtered
pulse 1.71 V VDD 3.6 V 350 - - ns
1. Guaranteed by design.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
Electrical characteristics STM32L471xx
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Figure 25. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 63: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
6.3.16 Extended interrupt and event controller input (EXTI) characteristics
The pulse on the interrupt input must have a minimal length in order to guarantee that it is
detected by the event controller.
6.3.17 Analog switches booster
MS19878V3
RPU
VDD
Internal reset
External
reset circuit(1)
NRST(2)
Filter
0.1 μF
Table 64. EXTI input characteristics(1)
1. Guaranteed by design.
Symbol Parameter Conditions Min Typ Max Unit
PLEC Pulse length to event
controller -20--ns
Table 65. Analog switches booster characteristics(1)
1. Guaranteed by design.
Symbol Parameter Min Typ Max Unit
VDD Supply voltage 1.62 - 3.6 V
tSU(BOOST) Booster startup time - - 240 µs
IDD(BOOST)
Booster consumption for
1.62 V VDD 2.0 V --250
µA
Booster consumption for
2.0 V VDD 2.7 V --500
Booster consumption for
2.7 V VDD 3.6 V --900
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STM32L471xx Electrical characteristics
206
6.3.18 Analog-to-Digital converter characteristics
Unless otherwise specified, the parameters given in Table 66 are preliminary values derived
from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage
conditions summarized in Table 23: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.
Table 66. ADC characteristics(1) (2)
Symbol Parameter Conditions Min Typ Max Unit
VDDA Analog supply voltage - 1.62 - 3.6 V
VREF+ Positive reference voltage
VDDA 2 V 2 - VDDA V
VDDA < 2 V VDDA V
VREF-
Negative reference
voltage -V
SSA V
fADC ADC clock frequency
Range 1 0.14 - 80
MHz
Range 2 0.14 - 26
fs
Sampling rate for FAST
channels
Resolution = 12 bits - - 5.33
Msps
Resolution = 10 bits - - 6.15
Resolution = 8 bits - - 7.27
Resolution = 6 bits - - 8.88
Sampling rate for SLOW
channels
Resolution = 12 bits - - 4.21
Resolution = 10 bits - - 4.71
Resolution = 8 bits - - 5.33
Resolution = 6 bits - - 6.15
fTRIG External trigger frequency
fADC = 80 MHz
Resolution = 12 bits - - 5.33 MHz
Resolution = 12 bits - - 15 1/fADC
VAIN (3) Conversion voltage
range(2) -0-V
REF+ V
RAIN External input impedance - - - 50 k
CADC
Internal sample and hold
capacitor --5-pF
tSTAB Power-up time - 1 conversion
cycle
tCAL Calibration time
fADC = 80 MHz 1.45 µs
-1161/f
ADC
tLATR
Trigger conversion
latency Regular and
injected channels without
conversion abort
CKMODE = 00 1.5 2 2.5
1/fADC
CKMODE = 01 - - 2.0
CKMODE = 10 - - 2.25
CKMODE = 11 - - 2.125
Electrical characteristics STM32L471xx
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The maximum value of RAIN can be found in Table 67: Maximum ADC RAIN.
tLATRINJ
Trigger conversion
latency Injected channels
aborting a regular
conversion
CKMODE = 00 2.5 3 3.5
1/fADC
CKMODE = 01 - - 3.0
CKMODE = 10 - - 3.25
CKMODE = 11 - - 3.125
tsSampling time
fADC = 80 MHz 0.03125 - 8.00625 µs
- 2.5 - 640.5 1/fADC
tADCVREG_STUP
ADC voltage regulator
start-up time ---20
µs
tCONV
Total conversion time
(including sampling time)
fADC = 80 MHz
Resolution = 12 bits 0.1875 - 8.1625 µs
Resolution = 12 bits
ts + 12.5 cycles for
successive approximation
= 15 to 653
1/fADC
IDDA(ADC) ADC consumption from
the VDDA supply
fs = 5 Msps - 730 830
µAfs = 1 Msps - 160 220
fs = 10 ksps - 16 50
IDDV_S(ADC)
ADC consumption from
the VREF+ single ended
mode
fs = 5 Msps - 130 160
µAfs = 1 Msps - 30 40
fs = 10 ksps - 0.6 2
IDDV_D(ADC)
ADC consumption from
the VREF+ differential
mode
fs = 5 Msps - 260 310
µAfs = 1 Msps - 60 70
fs = 10 ksps - 1.3 3
1. Guaranteed by design
2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4V). It is disable when VDDA 2.4 V.
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 4: Pinouts and pin description for further details.
Table 66. ADC characteristics(1) (2) (continued)
Symbol Parameter Conditions Min Typ Max Unit
AIN
DS10741 Rev 2 151/229
STM32L471xx Electrical characteristics
206
Table 67. Maximum ADC RAIN(1)(2)
Resolution Sampling cycle
@80 MHz
Sampling time [ns]
@80 MHz
RAIN max (Ω)
Fast channels(3) Slow channels(4)
12 bits
2.5 31.25 100 N/A
6.5 81.25 330 100
12.5 156.25 680 470
24.5 306.25 1500 1200
47.5 593.75 2200 1800
92.5 1156.25 4700 3900
247.5 3093.75 12000 10000
640.5 8006.75 39000 33000
10 bits
2.5 31.25 120 N/A
6.5 81.25 390 180
12.5 156.25 820 560
24.5 306.25 1500 1200
47.5 593.75 2200 1800
92.5 1156.25 5600 4700
247.5 3093.75 12000 10000
640.5 8006.75 47000 39000
8 bits
2.5 31.25 180 N/A
6.5 81.25 470 270
12.5 156.25 1000 680
24.5 306.25 1800 1500
47.5 593.75 2700 2200
92.5 1156.25 6800 5600
247.5 3093.75 15000 12000
640.5 8006.75 50000 50000
6 bits
2.5 31.25 220 N/A
6.5 81.25 560 330
12.5 156.25 1200 1000
24.5 306.25 2700 2200
47.5 593.75 3900 3300
92.5 1156.25 8200 6800
247.5 3093.75 18000 15000
640.5 8006.75 50000 50000
1. Guaranteed by design.
Electrical characteristics STM32L471xx
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2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4V). It is disable when VDDA 2.4 V.
3. Fast channels are: PC0, PC1, PC2, PC3, PA0.
4. Slow channels are: all ADC inputs except the fast channels.
DS10741 Rev 2 153/229
STM32L471xx Electrical characteristics
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Table 68. ADC accuracy - limited test conditions 1(1)(2)(3)
Sym-
bol Parameter Conditions(4) Min Typ Max Unit
ET
To t a l
unadjusted
error
ADC clock frequency
80 MHz,
Sampling rate 5.33 Msps,
VDDA = VREF+ = 3 V,
TA = 25 °C
Single
ended
Fast channel (max speed) - 4 5
LSB
Slow channel (max speed) - 4 5
Differential
Fast channel (max speed) - 3.5 4.5
Slow channel (max speed) - 3.5 4.5
EO Offset
error
Single
ended
Fast channel (max speed) - 1 2.5
Slow channel (max speed) - 1 2.5
Differential
Fast channel (max speed) - 1.5 2.5
Slow channel (max speed) - 1.5 2.5
EG Gain error
Single
ended
Fast channel (max speed) - 2.5 4.5
Slow channel (max speed) - 2.5 4.5
Differential
Fast channel (max speed) - 2.5 3.5
Slow channel (max speed) - 2.5 3.5
ED
Differential
linearity
error
Single
ended
Fast channel (max speed) - 1 1.5
Slow channel (max speed) - 1 1.5
Differential
Fast channel (max speed) - 1 1.2
Slow channel (max speed) - 1 1.2
EL
Integral
linearity
error
Single
ended
Fast channel (max speed) - 1.5 2.5
Slow channel (max speed) - 1.5 2.5
Differential
Fast channel (max speed) - 1 2
Slow channel (max speed) - 1 2
ENOB
Effective
number of
bits
Single
ended
Fast channel (max speed) 10.4 10.5 -
bits
Slow channel (max speed) 10.4 10.5 -
Differential
Fast channel (max speed) 10.8 10.9 -
Slow channel (max speed) 10.8 10.9 -
SINAD
Signal-to-
noise and
distortion
ratio
Single
ended
Fast channel (max speed) 64.4 65 -
dB
Slow channel (max speed) 64.4 65 -
Differential
Fast channel (max speed) 66.8 67.4 -
Slow channel (max speed) 66.8 67.4 -
SNR Signal-to-
noise ratio
Single
ended
Fast channel (max speed) 65 66 -
Slow channel (max speed) 65 66 -
Differential
Fast channel (max speed) 67 68 -
Slow channel (max speed) 67 68 -
Electrical characteristics STM32L471xx
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THD
To t a l
harmonic
distortion
ADC clock frequency
80 MHz,
Sampling rate 5.33 Msps,
VDDA = VREF+ = 3 V,
TA = 25 °C
Single
ended
Fast channel (max speed) - -74 -73
dB
Slow channel (max speed) - -74 -73
Differential
Fast channel (max speed) - -79 -76
Slow channel (max speed) - -79 -76
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4 V). It is disable when VDDA 2.4 V. No oversampling.
Table 68. ADC accuracy - limited test conditions 1(1)(2)(3) (continued)
Sym-
bol Parameter Conditions(4) Min Typ Max Unit
DS10741 Rev 2 155/229
STM32L471xx Electrical characteristics
206
Table 69. ADC accuracy - limited test conditions 2(1)(2)(3)
Sym-
bol Parameter Conditions(4) Min Typ Max Unit
ET
To t a l
unadjusted
error
ADC clock frequency
80 MHz,
Sampling rate 5.33 Msps,
2 V VDDA
Single
ended
Fast channel (max speed) - 4 6.5
LSB
Slow channel (max speed) - 4 6.5
Differential
Fast channel (max speed) - 3.5 5.5
Slow channel (max speed) - 3.5 5.5
EO Offset
error
Single
ended
Fast channel (max speed) - 1 4.5
Slow channel (max speed) - 1 5
Differential
Fast channel (max speed) - 1.5 3
Slow channel (max speed) - 1.5 3
EG Gain error
Single
ended
Fast channel (max speed) - 2.5 6
Slow channel (max speed) - 2.5 6
Differential
Fast channel (max speed) - 2.5 3.5
Slow channel (max speed) - 2.5 3.5
ED
Differential
linearity
error
Single
ended
Fast channel (max speed) - 1 1.5
Slow channel (max speed) - 1 1.5
Differential
Fast channel (max speed) - 1 1.2
Slow channel (max speed) - 1 1.2
EL
Integral
linearity
error
Single
ended
Fast channel (max speed) - 1.5 3.5
Slow channel (max speed) - 1.5 3.5
Differential
Fast channel (max speed) - 1 3
Slow channel (max speed) - 1 2.5
ENOB
Effective
number of
bits
Single
ended
Fast channel (max speed) 10 10.5 -
bits
Slow channel (max speed) 10 10.5 -
Differential
Fast channel (max speed) 10.7 10.9 -
Slow channel (max speed) 10.7 10.9 -
SINAD
Signal-to-
noise and
distortion
ratio
Single
ended
Fast channel (max speed) 62 65 -
dB
Slow channel (max speed) 62 65 -
Differential
Fast channel (max speed) 66 67.4 -
Slow channel (max speed) 66 67.4 -
SNR Signal-to-
noise ratio
Single
ended
Fast channel (max speed) 64 66 -
Slow channel (max speed) 64 66 -
Differential
Fast channel (max speed) 66.5 68 -
Slow channel (max speed) 66.5 68 -
Electrical characteristics STM32L471xx
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THD
To t a l
harmonic
distortion
ADC clock frequency
80 MHz,
Sampling rate 5.33 Msps,
2 V VDDA
Single
ended
Fast channel (max speed) - -74 -65
dB
Slow channel (max speed) - -74 -67
Differential
Fast channel (max speed) - -79 -70
Slow channel (max speed) - -79 -71
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4 V). It is disable when VDDA 2.4 V. No oversampling.
Table 69. ADC accuracy - limited test conditions 2(1)(2)(3) (continued)
Sym-
bol Parameter Conditions(4) Min Typ Max Unit
DS10741 Rev 2 157/229
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206
Table 70. ADC accuracy - limited test conditions 3(1)(2)(3)
Sym-
bol Parameter Conditions(4) Min Typ Max Unit
ET
To t a l
unadjusted
error
ADC clock frequency
80 MHz,
Sampling rate 5.33 Msps,
1.65 V VDDA = VREF+
3.6 V,
Voltage scaling Range 1
Single
ended
Fast channel (max speed) - 5.5 7.5
LSB
Slow channel (max speed) - 4.5 6.5
Differential
Fast channel (max speed) - 4.5 7.5
Slow channel (max speed) - 4.5 5.5
EO Offset
error
Single
ended
Fast channel (max speed) - 2 5
Slow channel (max speed) - 2.5 5
Differential
Fast channel (max speed) - 2 3.5
Slow channel (max speed) - 2.5 3
EG Gain error
Single
ended
Fast channel (max speed) - 4.5 7
Slow channel (max speed) - 3.5 6
Differential
Fast channel (max speed) - 3.5 4
Slow channel (max speed) - 3.5 5
ED
Differential
linearity
error
Single
ended
Fast channel (max speed) - 1.2 1.5
Slow channel (max speed) - 1.2 1.5
Differential
Fast channel (max speed) - 1 1.2
Slow channel (max speed) - 1 1.2
EL
Integral
linearity
error
Single
ended
Fast channel (max speed) - 3 3.5
Slow channel (max speed) - 2.5 3.5
Differential
Fast channel (max speed) - 2 2.5
Slow channel (max speed) - 2 2.5
ENOB
Effective
number of
bits
Single
ended
Fast channel (max speed) 10 10.4 -
bits
Slow channel (max speed) 10 10.4 -
Differential
Fast channel (max speed) 10.6 10.7 -
Slow channel (max speed) 10.6 10.7 -
SINAD
Signal-to-
noise and
distortion
ratio
Single
ended
Fast channel (max speed) 62 64 -
dB
Slow channel (max speed) 62 64 -
Differential
Fast channel (max speed) 65 66 -
Slow channel (max speed) 65 66 -
SNR Signal-to-
noise ratio
Single
ended
Fast channel (max speed) 63 65 -
Slow channel (max speed) 63 65 -
Differential
Fast channel (max speed) 66 67 -
Slow channel (max speed) 66 67 -
Electrical characteristics STM32L471xx
158/229 DS10741 Rev 2
THD
To t a l
harmonic
distortion
ADC clock frequency
80 MHz,
Sampling rate 5.33 Msps,
1.65 V VDDA = VREF+
3.6 V,
Voltage scaling Range 1
Single
ended
Fast channel (max speed) - -69 -67
dB
Slow channel (max speed) - -71 -67
Differential
Fast channel (max speed) - -72 -71
Slow channel (max speed) - -72 -71
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4 V). It is disable when VDDA 2.4 V. No oversampling.
Table 70. ADC accuracy - limited test conditions 3(1)(2)(3) (continued)
Sym-
bol Parameter Conditions(4) Min Typ Max Unit
DS10741 Rev 2 159/229
STM32L471xx Electrical characteristics
206
Table 71. ADC accuracy - limited test conditions 4(1)(2)(3)
Sym-
bol Parameter Conditions(4) Min Typ Max Unit
ET
To t a l
unadjusted
error
ADC clock frequency
26 MHz,
1.65 V VDDA = VREF+
3.6 V,
Voltage scaling Range 2
Single
ended
Fast channel (max speed) - 5 5.4
LSB
Slow channel (max speed) - 4 5
Differential
Fast channel (max speed) - 4 5
Slow channel (max speed) - 3.5 4.5
EO Offset
error
Single
ended
Fast channel (max speed) - 2 4
Slow channel (max speed) - 2 4
Differential
Fast channel (max speed) - 2 3.5
Slow channel (max speed) - 2 3.5
EG Gain error
Single
ended
Fast channel (max speed) - 4 4.5
Slow channel (max speed) - 4 4.5
Differential
Fast channel (max speed) - 3 4
Slow channel (max speed) - 3 4
ED
Differential
linearity
error
Single
ended
Fast channel (max speed) - 1 1.5
Slow channel (max speed) - 1 1.5
Differential
Fast channel (max speed) - 1 1.2
Slow channel (max speed) - 1 1.2
EL
Integral
linearity
error
Single
ended
Fast channel (max speed) - 2.5 3
Slow channel (max speed) - 2.5 3
Differential
Fast channel (max speed) - 2 2.5
Slow channel (max speed) - 2 2.5
ENOB
Effective
number of
bits
Single
ended
Fast channel (max speed) 10.2 10.5 -
bits
Slow channel (max speed) 10.2 10.5 -
Differential
Fast channel (max speed) 10.6 10.7 -
Slow channel (max speed) 10.6 10.7 -
SINAD
Signal-to-
noise and
distortion
ratio
Single
ended
Fast channel (max speed) 63 65 -
dB
Slow channel (max speed) 63 65 -
Differential
Fast channel (max speed) 65 66 -
Slow channel (max speed) 65 66 -
SNR Signal-to-
noise ratio
Single
ended
Fast channel (max speed) 64 65 -
Slow channel (max speed) 64 65 -
Differential
Fast channel (max speed) 66 67 -
Slow channel (max speed) 66 67 -
Electrical characteristics STM32L471xx
160/229 DS10741 Rev 2
THD
To t a l
harmonic
distortion
ADC clock frequency
26 MHz,
1.65 V VDDA = VREF+
3.6 V,
Voltage scaling Range 2
Single
ended
Fast channel (max speed) - -71 -69
dB
Slow channel (max speed) - -71 -69
Differential
Fast channel (max speed) - -73 -72
Slow channel (max speed) - -73 -72
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4 V). It is disable when VDDA 2.4 V. No oversampling.
Table 71. ADC accuracy - limited test conditions 4(1)(2)(3) (continued)
Sym-
bol Parameter Conditions(4) Min Typ Max Unit
HP
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STM32L471xx Electrical characteristics
206
Figure 26. ADC accuracy characteristics
Figure 27. Typical connection diagram using the ADC
1. Refer to Table 66: ADC characteristics for the values of RAIN and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 60: I/O static characteristics for the value of the pad capacitance). A high
Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 60: I/O static characteristics for the values of Ilkg.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 14: Power supply
scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.
ET = total unajusted error: maximum deviation
between the actual and ideal transfer curves.
EO = offset error: maximum deviation
between the first actual transition and
the first ideal one.
EG = gain error: deviation between the last
ideal transition and the last actual one.
ED = differential linearity error: maximum
deviation between actual steps and the ideal ones.
EL = integral linearity error: maximum deviation
between any actual transition and the end point
correlation line.
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
4095
4094
4093
7
6
5
4
3
2
1
023456
17 4093 4094 4095 4096 VDDA
VSSA
EO
ET
EL
EG
ED
1 LSB IDEAL
(1)
(3)
(2)
MS19880V2
MS33900V5
Sample and hold ADC converter
12-bit
converter
Cparasitic(2) Ilkg (3)
VTCADC
VDDA
RAIN(1)
VAIN
VT
AINx RADC
Electrical characteristics STM32L471xx
162/229 DS10741 Rev 2
6.3.19 Digital-to-Analog converter characteristics
Table 72. DAC characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
VDDA
Analog supply voltage for
DAC ON
DAC output buffer OFF (no resistive
load on DAC1_OUTx pin or internal
connection)
1.71 -
3.6
V
Other modes 1.80 -
VREF+ Positive reference voltage
DAC output buffer OFF (no resistive
load on DAC1_OUTx pin or internal
connection)
1.71 -
VDDA
Other modes 1.80 -
VREF- Negative reference voltage - VSSA
RLResistive load DAC output
buffer ON
connected to VSSA 5- -
k
connected to VDDA 25 - -
ROOutput Impedance DAC output buffer OFF 9.6 11.7 13.8 k
RBON
Output impedance sample
and hold mode, output
buffer ON
VDD = 2.7 V - - 2
k
VDD = 2.0 V - - 3.5
RBOFF
Output impedance sample
and hold mode, output
buffer OFF
VDD = 2.7 V - - 16.5
k
VDD = 2.0 V - - 18.0
CLCapacitive load
DAC output buffer ON - - 50 pF
CSH Sample and hold mode - 0.1 1 µF
VDAC_OUT
Voltage on DAC1_OUTx
output
DAC output buffer ON 0.2 - VREF+
– 0.2 V
DAC output buffer OFF 0 - VREF+
tSETTLING
Settling time (full scale: for
a 12-bit code transition
between the lowest and the
highest input codes when
DAC1_OUTx reaches final
value ±0.5LSB, ±1 LSB,
±2 LSB, ±4 LSB, ±8 LSB)
Normal mode
DAC output
buffer ON
CL 50 pF,
RL 5 k
±0.5 LSB - 1.7 3
µs
±1 LSB - 1.6 2.9
±2 LSB - 1.55 2.85
±4 LSB - 1.48 2.8
±8 LSB - 1.4 2.75
Normal mode DAC output buffer
OFF, ±1LSB, CL = 10 pF -2 2.5
tWAKEUP(2)
Wakeup time from off state
(setting the ENx bit in the
DAC Control register) until
final value ±1 LSB
Normal mode DAC output buffer ON
CL 50 pF, RL 5 k-4.2 7.5
µs
Normal mode DAC output buffer
OFF, CL 10 pF -2 5
PSRR VDDA supply rejection ratio Normal mode DAC output buffer ON
CL 50 pF, RL = 5 k, DC --80 -28dB
DS10741 Rev 2 163/229
STM32L471xx Electrical characteristics
206
TW_to_W
Minimal time between two
consecutive writes into the
DAC_DORx register to
guarantee a correct
DAC1_OUTx for a small
variation of the input code
(1 LSB)
DAC_MCR:MODEx[2:0] =
000 or 001
DAC_MCR:MODEx[2:0] =
010 or 011
CL 50 pF, RL 5 k
CL 10 pF
1
1.4
--µs
tSAMP
Sampling time in sample
and hold mode (code
transition between the
lowest input code and the
highest input code when
DAC1_OUTx reaches final
value ±1LSB)
DAC1_OUTx
pin connected
DAC output buffer
ON, CSH = 100 nF -0.7 3.5
ms
DAC output buffer
OFF, CSH = 100 nF -10.5 18
DAC1_OUTx
pin not
connected
(internal
connection
only)
DAC output buffer
OFF -2 3.5µs
Ileak Output leakage current Sample and hold mode,
DAC1_OUTx pin connected -- -
(3) nA
CIint
Internal sample and hold
capacitor - 5.2 7 8.8 pF
tTRIM Middle code offset trim time DAC output buffer ON 50 - - µs
Voffset
Middle code offset for 1 trim
code step
VREF+ = 3.6 V - 1500 -
µV
VREF+ = 1.8 V - 750 -
IDDA(DAC) DAC consumption from
VDDA
DAC output
buffer ON
No load, middle
code (0x800) - 315 500
µA
No load, worst code
(0xF1C) - 450 670
DAC output
buffer OFF
No load, middle
code (0x800) -- 0.2
Sample and hold mode, CSH =
100 nF -
315
Ton / (Ton
+Toff)
(4)
670
To n / ( To n
+Toff)
(4)
Table 72. DAC characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
1,
Electrical characteristics STM32L471xx
164/229 DS10741 Rev 2
Figure 28. 12-bit buffered / non-buffered DAC
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
IDDV(DAC) DAC consumption from
VREF+
DAC output
buffer ON
No load, middle
code (0x800) - 185 240
µA
No load, worst code
(0xF1C) - 340 400
DAC output
buffer OFF
No load, middle
code (0x800) - 155 205
Sample and hold mode, buffer ON,
CSH = 100 nF, worst case -
185
Ton / (Ton
+Toff)
(4)
400
To n / ( To n
+Toff)
(4)
Sample and hold mode, buffer OFF,
CSH = 100 nF, worst case -
155
Ton / (Ton
+Toff)
(4)
205
To n / ( To n
+Toff)
(4)
1. Guaranteed by design.
2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
3. Refer to Table 60: I/O static characteristics.
4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0392 reference manual for more details.
Table 72. DAC characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
(1)
Buffer
12-bit
digital to
analog
converter
Buffered/non-buffered DAC
DACx_OUT
R
LOAD
C
LOAD
ai17157d
DS10741 Rev 2 165/229
STM32L471xx Electrical characteristics
206
. Table 73. DAC accuracy(1)
Symbol Parameter Conditions Min Typ Max Unit
DNL Differential non
linearity (2)
DAC output buffer ON - - ±2
LSB
DAC output buffer OFF - - ±2
- monotonicity 10 bits guaranteed
INL Integral non
linearity(3)
DAC output buffer ON
CL 50 pF, RL 5 k--±4
DAC output buffer OFF
CL 50 pF, no RL --±4
Offset Offset error at
code 0x800(3)
DAC output buffer ON
CL 50 pF, RL 5 k
VREF+ = 3.6 V - - ±12
VREF+ = 1.8 V - - ±25
DAC output buffer OFF
CL 50 pF, no RL --±8
Offset1 Offset error at
code 0x001(4)
DAC output buffer OFF
CL 50 pF, no RL --±5
OffsetCal
Offset Error at
code 0x800
after calibration
DAC output buffer ON
CL 50 pF, RL 5 k
VREF+ = 3.6 V - - ±5
VREF+ = 1.8 V - - ±7
Gain Gain error(5)
DAC output buffer ON
CL 50 pF, RL 5 k--±0.5
%
DAC output buffer OFF
CL 50 pF, no RL --±0.5
TUE
Tot a l
unadjusted
error
DAC output buffer ON
CL 50 pF, RL 5 k--±30
LSB
DAC output buffer OFF
CL 50 pF, no RL --±12
TUECal
Tot a l
unadjusted
error after
calibration
DAC output buffer ON
CL 50 pF, RL 5 k--±23LSB
SNR Signal-to-noise
ratio
DAC output buffer ON
CL 50 pF, RL 5 k
1 kHz, BW 500 kHz
-71.2-
dB
DAC output buffer OFF
CL 50 pF, no RL, 1 kHz
BW 500 kHz
-71.6-
THD Total harmonic
distortion
DAC output buffer ON
CL 50 pF, RL 5 k, 1 kHz --78-
dB
DAC output buffer OFF
CL 50 pF, no RL, 1 kHz --79-
Electrical characteristics STM32L471xx
166/229 DS10741 Rev 2
SINAD
Signal-to-noise
and distortion
ratio
DAC output buffer ON
CL 50 pF, RL 5 k, 1 kHz -70.4-
dB
DAC output buffer OFF
CL 50 pF, no RL, 1 kHz -71-
ENOB Effective
number of bits
DAC output buffer ON
CL 50 pF, RL 5 k, 1 kHz -11.4-
bits
DAC output buffer OFF
CL 50 pF, no RL, 1 kHz -11.5-
1. Guaranteed by design.
2. Difference between two consecutive codes - 1 LSB.
3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (VREF+ – 0.2) V when buffer is ON.
Table 73. DAC accuracy(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
DS10741 Rev 2 167/229
STM32L471xx Electrical characteristics
206
6.3.20 Voltage reference buffer characteristics
Table 74. VREFBUF characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
VDDA
Analog supply
voltage
Normal mode
VRS = 0 2.4 - 3.6
V
VRS = 1 2.8 - 3.6
Degraded mode(2) VRS = 0 1.65 - 2.4
VRS = 1 1.65 - 2.8
VREFBUF_
OUT
Voltage
reference
output
Normal mode
VRS = 0 2.046(3) 2.048 2.049(3)
VRS = 1 2.498(3) 2.5 2.502(3)
Degraded mode(2) VRS = 0 VDDA-150 mV - VDDA
VRS = 1 VDDA-150 mV - VDDA
TRIM Trim step
resolution ---±0.05±0.1%
CL Load capacitor - - 0.5 1 1.5 µF
esr
Equivalent
Serial Resistor
of Cload
----2
Iload
Static load
current ----4mA
Iline_reg Line regulation 2.8 V VDDA 3.6 V
Iload = 500 µA - 200 1000
ppm/V
Iload = 4 mA - 100 500
Iload_reg
Load
regulation 500 A Iload 4 mA Normal mode - 50 500 ppm/mA
TCoeff
Temperature
coefficient
-40 °C < TJ < +125 °C - -
Tcoeff_
vrefint +
50 ppm/ °C
0 °C < TJ < +50 °C - -
Tcoeff_
vrefint +
50
PSRR Power supply
rejection
DC 40 60 -
dB
100 kHz 25 40 -
tSTART Start-up time
CL = 0.5 µF(4) - 300 350
µsCL = 1.1 µF(4) - 500 650
CL = 1.5 µF(4) - 650 800
IINRUSH
Control of
maximum DC
current drive
on VREFBUF_
OUT during
start-up phase
(5)
---8-mA
Electrical characteristics STM32L471xx
168/229 DS10741 Rev 2
IDDA(VREF
BUF)
VREFBUF
consumption
from VDDA
Iload = 0 µA - 16 25
µAIload = 500 µA - 18 30
Iload = 4 mA - 35 50
1. Guaranteed by design, unless otherwise specified.
2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (VDDA -
drop voltage).
3. Guaranteed by test in production.
4. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise.
5. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the VDDA voltage should be in
the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for VRS = 0 and VRS = 1.
Table 74. VREFBUF characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
DS10741 Rev 2 169/229
STM32L471xx Electrical characteristics
206
6.3.21 Comparator characteristics
Table 75. COMP characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
VDDA Analog supply voltage - 1.62 - 3.6
VVIN
Comparator input voltage
range -0-V
DDA
VBG(2) Scaler input voltage - VREFINT
VSC Scaler offset voltage - - ±5 ±10 mV
IDDA(SCALER) Scaler static consumption
from VDDA
BRG_EN=0 (bridge disable) - 200 300 nA
BRG_EN=1 (bridge enable) - 0.8 1 µA
tSTART_SCALER Scaler startup time - - 100 200 µs
tSTART
Comparator startup time to
reach propagation delay
specification
High-speed
mode
VDDA 2.7 V - - 5
µs
VDDA < 2.7 V - - 7
Medium mode
VDDA 2.7 V - - 15
VDDA < 2.7 V - - 25
Ultra-low-power mode - - 80
tD(3)
Propagation delay for
200 mV step
with 100 mV overdrive
High-speed
mode
VDDA 2.7 V - 55 80
ns
VDDA < 2.7 V - 65 100
Medium mode
VDDA 2.7 V - 0.55 0.9
µsVDDA < 2.7 V - 0.65 1
Ultra-low-power mode - 5 12
Voffset Comparator offset error Full common
mode range --±5±20mV
Vhys Comparator hysteresis
No hysteresis - 0 -
mV
Low hysteresis - 8 -
Medium hysteresis - 15 -
High hysteresis - 27 -
Electrical characteristics STM32L471xx
170/229 DS10741 Rev 2
6.3.22 Operational amplifiers characteristics
IDDA(COMP) Comparator consumption
from VDDA
Ultra-low-
power mode
Static - 400 600
nA
With 50 kHz
±100 mV overdrive
square signal
-1200-
Medium mode
Static - 5 7
µA
With 50 kHz
±100 mV overdrive
square signal
-6-
High-speed
mode
Static - 70 100
With 50 kHz
±100 mV overdrive
square signal
-75-
Ibias
Comparator input bias
current ----
(4) nA
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 26: Embedded internal voltage reference.
3. Guaranteed by characterization results.
4. Mostly I/O leakage when used in analog mode. Refer to Ilkg parameter in Table 60: I/O static characteristics.
Table 75. COMP characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 76. OPAMP characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
VDDA
Analog supply
voltage(2) -1.8-3.6V
CMIR Common mode
input range -0-V
DDA V
VIOFFSET
Input offset
voltage
25 °C, No Load on output. - - ±1.5
mV
All voltage/Temp. - - ±3
VIOFFSET
Input offset
voltage drift
Normal mode - ±5 - V/°C
Low-power mode - ±10 -
TRIMOFFSETP
TRIMLPOFFSETP
Offset trim step
at low common
input voltage
(0.1 VDDA)
--0.81.1
mV
TRIMOFFSETN
TRIMLPOFFSETN
Offset trim step
at high common
input voltage
(0.9 VDDA)
--11.35
DS10741 Rev 2 171/229
STM32L471xx Electrical characteristics
206
ILOAD Drive current
Normal mode
VDDA 2 V
- - 500
µA
Low-power mode - - 100
ILOAD_PGA
Drive current in
PGA mode
Normal mode
VDDA 2 V
- - 450
Low-power mode - - 50
RLOAD
Resistive load
(connected to
VSSA or to
VDDA)
Normal mode
VDDA < 2 V
4--
k
Low-power mode 20 - -
RLOAD_PGA
Resistive load
in PGA mode
(connected to
VSSA or to
VDDA)
Normal mode
VDDA < 2 V
4.5 - -
Low-power mode 40 - -
CLOAD Capacitive load - - - 50 pF
CMRR Common mode
rejection ratio
Normal mode - -85 -
dB
Low-power mode - -90 -
PSRR Power supply
rejection ratio
Normal mode CLOAD 50 pf,
RLOAD 4 k DC 70 85 -
dB
Low-power mode CLOAD 50 pf,
RLOAD 20 k DC 72 90 -
GBW Gain Bandwidth
Product
Normal mode VDDA 2.4 V
(OPA_RANGE = 1)
550 1600 2200
kHz
Low-power mode 100 420 600
Normal mode VDDA < 2.4 V
(OPA_RANGE = 0)
250 700 950
Low-power mode 40 180 280
SR(3)
Slew rate
(from 10 and
90% of output
voltage)
Normal mode
VDDA 2.4 V
-700-
V/ms
Low-power mode - 180 -
Normal mode
VDDA < 2.4 V
-300-
Low-power mode - 80 -
AO Open loop gain
Normal mode 55 110 -
dB
Low-power mode 45 110 -
VOHSAT(3) High saturation
voltage
Normal mode
Iload = max or Rload =
min Input at VDDA.
VDDA -
100 --
mV
Low-power mode VDDA -
50 --
VOLSAT(3) Low saturation
voltage
Normal mode Iload = max or Rload =
min Input at 0.
- - 100
Low-power mode - - 50
mPhase margin
Normal mode - 74 -
°
Low-power mode - 66 -
Table 76. OPAMP characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
Electrical characteristics STM32L471xx
172/229 DS10741 Rev 2
GM Gain margin
Normal mode - 13 -
dB
Low-power mode - 20 -
tWAKEUP
Wake up time
from OFF state.
Normal mode
CLOAD 50 pf,
RLOAD 4 k
follower
configuration
-510
µs
Low-power mode
CLOAD 50 pf,
RLOAD 20 k
follower
configuration
-1030
Ibias
OPAMP input
bias current
Dedicated input
(UFBGA132 only)
TJ 75 °C - - 1
nA
TJ 85 °C - - 3
TJ 105 °C - - 8
TJ 125 °C - - 15
General purpose input (all packages
except UFBGA132) ---
(4)
PGA gain(3) Non inverting
gain value -
-2-
-
-4-
-8-
-16-
Rnetwork
R2/R1 internal
resistance
values in PGA
mode(5)
PGA Gain = 2 - 80/80 -
k/k
PGA Gain = 4 - 120/
40 -
PGA Gain = 8 - 140/
20 -
PGA Gain = 16 - 150/
10 -
Delta R
Resistance
variation (R1 or
R2)
--15-15%
PGA gain error PGA gain error - -1 - 1 %
PGA BW
PGA bandwidth
for different non
inverting gain
Gain = 2 - - GBW/
2-
MHz
Gain = 4 - - GBW/
4-
Gain = 8 - - GBW/
8-
Gain = 16 - - GBW/
16 -
Table 76. OPAMP characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
DS10741 Rev 2 173/229
STM32L471xx Electrical characteristics
206
en Voltage noise
density
Normal mode at 1 kHz, Output
loaded with 4 k-500-
nV/Hz
Low-power mode at 1 kHz, Output
loaded with 20 k-600-
Normal mode at 10 kHz, Output
loaded with 4 k-180-
Low-power mode at 10 kHz, Output
loaded with 20 k-290-
IDDA(OPAMP)(3)
OPAMP
consumption
from VDDA
Normal mode no Load, quiescent
mode
- 120 260
µA
Low-power mode - 45 100
1. Guaranteed by design, unless otherwise specified.
2. The temperature range is limited to 0 °C-125 °C when VDDA is below 2 V
3. Guaranteed by characterization results.
4. Mostly I/O leakage, when used in analog mode. Refer to Ilkg parameter in Table 60: I/O static characteristics.
5. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between
OPAMP inverting input and ground. The PGA gain =1+R2/R1
Table 76. OPAMP characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
BAT
BAT
Electrical characteristics STM32L471xx
174/229 DS10741 Rev 2
6.3.23 Temperature sensor characteristics
6.3.24 VBAT monitoring characteristics
Table 77. TS characteristics
Symbol Parameter Min Typ Max Unit
TL(1) VTS linearity with temperature - ±1 ±2 °C
Avg_Slope(2) Average slope 2.3 2.5 2.7 mV/°C
V30 Voltage at 30°C (±5 °C)(3) 0.742 0.76 0.785 V
tSTART
(TS_BUF)(1) Sensor Buffer Start-up time in continuous mode(4) -815µs
tSTART(1) Start-up time when entering in continuous mode(4) -70120µs
tS_temp(1) ADC sampling time when reading the temperature 5 - - µs
IDD(TS)(1) Temperature sensor consumption from VDD, when
selected by ADC -4.77 µA
1. Guaranteed by design.
2. Guaranteed by characterization results.
3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 8:
Temperature sensor calibration values.
4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.
Table 78. VBAT monitoring characteristics
Symbol Parameter Min Typ Max Unit
R Resistor bridge for VBAT -39-k
QRatio on V
BAT measurement - 3 - -
Er(1)
1. Guaranteed by design.
Error on Q -10 - 10 %
tS_vbat(1) ADC sampling time when reading the VBAT 12 - - µs
Table 79. VBAT charging characteristics
Symbol Parameter Conditions Min Typ Max Unit
RBC
Battery
charging
resistor
VBRS = 0 - 5 -
k
VBRS = 1 - 1.5 -
DS10741 Rev 2 175/229
STM32L471xx Electrical characteristics
206
6.3.25 DFSDM characteristics
Unless otherwise specified, the parameters given in Table 80 for DFSDM are derived from
tests performed under the ambient temperature, fAPB2 frequency and VDD supply voltage
conditions summarized in Table 23: General operating conditions.
•Output speed is set to OSPEEDRy[1:0] = 10
•Capacitive load C = 30 pF
•Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDM1_CKINy, DFSDM1_DATINy, DFSDM1_CKOUT for
DFSDM).
Table 80. DFSDM characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fDFSDMCLK DFSDM clock - - - fSYSCLK
MHz
fCKIN
(1/TCKIN)
Input clock
frequency SPI mode (SITP[1:0] = 01) - - 20
(fDFSDMCLK/4)
fCKOUT
Output clock
frequency ---20MHz
DuCyCKOUT
Output clock
frequency
duty cycle
-455055%
twh(CKIN)
twl(CKIN)
Input clock
high and low
time
SPI mode (SITP[1:0] = 01),
External clock mode
(SPICKSEL[1:0] = 0)
TCKIN/2-0.5 TCKIN/2 -
ns
tsu
Data input
setup time
SPI mode (SITP[1:0]=01),
External clock mode
(SPICKSEL[1:0] = 0)
0- -
th
Data input
hold time
SPI mode (SITP[1:0]=01),
External clock mode
(SPICKSEL[1:0] = 0)
2- -
TManchester
Manchester
data period
(recovered
clock period)
Manchester mode (SITP[1:0]
= 10 or 11),
Internal clock mode
(SPICKSEL[1:0] 0)
(CKOUT
DIV+1)
TDFSDMCLK
-(2 CKOUTDIV)
TDFSDMCLK
1. Guaranteed by characterization results.
Figure 16: DFSDM timing diagram
9: sp
Electrical characteristics STM32L471xx
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Figure 16: DFSDM timing diagram
6.3.26 Timer characteristics
The parameters given in the following tables are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
06Y9
63,&.6(/
63,&.6(/
63,&.6(/
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WVX
WZO WZK WUWI
WK
WVX WK
6,73
6,73
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&.,1,1\
63,&.6(/
WVX WK
WVX WK
6,73
6,73
')6'0B'$7$,1\
6,73
6,73
5HFRYHUHGFORFN
5HFRYHUHGGDWD
')6'0B'$7$,1\
0DQFKHVWHUWLPLQJ 63,WLPLQJ63,&.6(/ 63,WLPLQJ63,&.6(/
WZO WZK WUWI
DS10741 Rev 2 177/229
STM32L471xx Electrical characteristics
206
Table 81. TIMx(1) characteristics
1. TIMx, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.
Symbol Parameter Conditions Min Max Unit
tres(TIM) Timer resolution time
-1-t
TIMxCLK
fTIMxCLK = 80 MHz 12.5 - ns
fEXT
Timer external clock
frequency on CH1 to CH4
-0f
TIMxCLK/2 MHz
fTIMxCLK = 80 MHz 0 40 MHz
ResTIM Timer resolution
TIMx (except TIM2
and TIM5) -16
bit
TIM2 and TIM5 - 32
tCOUNTER
16-bit counter clock
period
- 1 65536 tTIMxCLK
fTIMxCLK = 80 MHz 0.0125 819.2 µs
tMAX_COUNT
Maximum possible count
with 32-bit counter
- - 65536 × 65536 tTIMxCLK
fTIMxCLK = 80 MHz - 53.68 s
Table 82. IWDG min/max timeout period at 32 kHz (LSI)(1)
1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there
is always a full RC period of uncertainty.
Prescaler divider PR[2:0] bits Min timeout RL[11:0]=
0x000
Max timeout RL[11:0]=
0xFFF Unit
/4 0 0.125 512
ms
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768
Table 83. WWDG min/max timeout value at 80 MHz (PCLK)
Prescaler WDGTB Min timeout value Max timeout value Unit
1 0 0.0512 3.2768
ms
2 1 0.1024 6.5536
4 2 0.2048 13.1072
8 3 0.4096 26.2144
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6.3.27 Communication interfaces characteristics
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
•Standard-mode (Sm): with a bit rate up to 100 kbit/s
•Fast-mode (Fm): with a bit rate up to 400 kbit/s
•Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0392 reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIOx is disabled, but is still present. Only FT_f I/O pins
support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
Table 84. I2C analog filter characteristics(1)
1. Guaranteed by design.
Symbol ParameterMinMaxUnit
tAF
Maximum pulse width of spikes
that are suppressed by the analog
filter
50(2)
2. Spikes with widths below tAF(min) are filtered.
260(3)
3. Spikes with widths above tAF(max) are not filtered
ns
DS10741 Rev 2 179/229
STM32L471xx Electrical characteristics
206
SPI characteristics
Unless otherwise specified, the parameters given in Table 85 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 23: General operating conditions.
•Output speed is set to OSPEEDRy[1:0] = 11
•Capacitive load C = 30 pF
•Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 85. SPI characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode receiver/full duplex
2.7 < VDD < 3.6 V
Voltage Range 1
--
24
MHz
Master mode receiver/full duplex
1.71 < VDD < 3.6 V
Voltage Range 1
13
Master mode transmitter
1.71 < VDD < 3.6 V
Voltage Range 1
40
Slave mode receiver
1.71 < VDD < 3.6 V
Voltage Range 1
40
Slave mode transmitter/full duplex
2.7 < VDD < 3.6 V
Voltage Range 1
26(2)
Slave mode transmitter/full duplex
1.71 < VDD < 3.6 V
Voltage Range 1
16(2)
Voltage Range 2 13
1.08 < VDDIO2 < 1.32 V(3) 8
tsu(NSS) NSS setup time Slave mode, SPI prescaler = 2 4TPCLK --ns
th(NSS) NSS hold time Slave mode, SPI prescaler = 2 2TPCLK --ns
tw(SCKH)
tw(SCKL)
SCK high and low time Master mode TPCLK-2 TPCLK TPCLK+2 ns
tsu(MI) Data input setup time
Master mode 3.5 - -
ns
tsu(SI) Slave mode 3 - -
th(MI) Data input hold time
Master mode 6.5 - -
ns
th(SI) Slave mode 3 - -
ta(SO) Data output access time Slave mode 9 - 36 ns
tdis(SO) Data output disable time Slave mode 9 - 16 ns
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Figure 29. SPI timing diagram - slave mode and CPHA = 0
tv(SO)
Data output valid time
Slave mode 2.7 < VDD < 3.6 V
Voltage Range 1 -12.519
ns
Slave mode 1.71 < VDD < 3.6 V
Voltage Range 1 -12.530
Slave mode 1.71 < VDD < 3.6 V
Voltage Range 2 -12.533
-Slave mode 1.08 < VDDIO2 < 1.32 V(3) -2562.5
tv(MO) Master mode - 2.5 12.5
th(SO)
Data output hold time
Slave mode 9 - -
ns- Slave mode 1.08 < VDDIO2 < 1.32 V(3) 24 - -
th(MO) Master mode 0 - -
1. Guaranteed by characterization results.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50 %.
3. SPI mapped on Port G.
Table 85. SPI characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
MSv41658V1
NSS input
CPHA=0
CPOL=0
SCK input
CPHA=0
CPOL=1
MISO output
MOSI input
tsu(SI)
th(SI)
tw(SCKL)
tw(SCKH)
tc(SCK)
tr(SCK)
th(NSS)
tdis(SO)
tsu(NSS)
ta(SO) tv(SO)
Next bits IN
Last bit OUT
First bit IN
First bit OUT Next bits OUT
th(SO) tf(SCK)
Last bit IN
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Figure 30. SPI timing diagram - slave mode and CPHA = 1
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
Figure 31. SPI timing diagram - master mode
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
MSv41659V1
NSS input
CPHA=1
CPOL=0
SCK input
CPHA=1
CPOL=1
MISO output
MOSI input
tsu(SI) th(SI)
tw(SCKL)
tw(SCKH)
tsu(NSS)
tc(SCK)
ta(SO) tv(SO)
First bit OUT Next bits OUT
Next bits IN
Last bit OUT
th(SO) tr(SCK)
tf(SCK) th(NSS)
tdis(SO)
First bit IN Last bit IN
ai14136c
SCK Output
CPHA= 0
MOSI
OUTPUT
MISO
INP UT
CPHA= 0
LSB OUT
LSB IN
CPOL=0
CPOL=1
B I T1 OUT
NSS input
tc(SCK)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
th(MI)
High
SCK Output
CPHA=1
CPHA=1
CPOL=0
CPOL=1
tsu(MI)
tv(MO) th(MO)
MSB IN BIT6 IN
MSB OUT
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Quad SPI characteristics
Unless otherwise specified, the parameters given in Table 86 and Table 87 for Quad SPI
are derived from tests performed under the ambient temperature, fAHB frequency and VDD
supply voltage conditions summarized in Table 23: General operating conditions, with the
following configuration:
•Output speed is set to OSPEEDRy[1:0] = 11
•Capacitive load C = 15 or 20 pF
•Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics.
Table 86. Quad SPI characteristics in SDR mode(1)
Symbol Parameter Conditions Min Typ Max Unit
FCK
1/t(CK)
Quad SPI clock frequency
1.71 < VDD< 3.6 V, CLOAD = 20 pF
Voltage Range 1 --40
MHz
1.71 < VDD< 3.6 V, CLOAD = 15 pF
Voltage Range 1 --48
2.7 < VDD< 3.6 V, CLOAD = 15 pF
Voltage Range 1 --60
1.71 < VDD < 3.6 V CLOAD = 20 pF
Voltage Range 2 --26
tw(CKH) Quad SPI clock high and
low time fAHBCLK= 48 MHz, presc=0
t(CK)/2-2 - t(CK)/2
ns
tw(CKL) t(CK)/2 - t(CK)/2+2
ts(IN) Data input setup time
Voltage Range 1 4 - -
Voltage Range 2 3.5 - -
th(IN) Data input hold time
Voltage Range 1 5.5 - -
Voltage Range 2 6.5 - -
tv(OUT) Data output valid time
Voltage Range 1 - 2.5 5
Voltage Range 2 - 3 5
th(OUT) Data output hold time
Voltage Range 1 1.5 - -
Voltage Range 2 2 - -
1. Guaranteed by characterization results.
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Figure 32. Quad SPI timing diagram - SDR mode
Figure 33. Quad SPI timing diagram - DDR mode
Table 87. QUADSPI characteristics in DDR mode(1)
Symbol Parameter Conditions Min Typ Max Unit
FCK
1/t(CK)
Quad SPI clock
frequency
1.71 < VDD < 3.6 V, CLOAD = 20 pF
Voltage Range 1 --40
MHz
2 < VDD < 3.6 V, CLOAD = 20 pF
Voltage Range 1 --48
1.71 < VDD < 3.6 V, CLOAD = 15 pF
Voltage Range 1 --48
1.71 < VDD < 3.6 V CLOAD = 20 pF
Voltage Range 2 --26
tw(CKH) Quad SPI clock high
and low time fAHBCLK = 48 MHz, presc=0
t(CK)/2-2 - t(CK)/2
ns
tw(CKL) t(CK)/2 - t(CK)/2+2
tsf(IN);tsr(IN) Data input setup time
Voltage Range 1 and 2
3.5 - -
thf(IN); thr(IN) Data input hold time 6.5 - -
tvf(OUT);tvr(OUT) Data output valid time
Voltage Range 1
-
11 12
Voltage Range 2 15 19
thf(OUT); thr(OUT) Data output hold time
Voltage Range 1 6 -
-
Voltage Range 2 8 -
1. Guaranteed by characterization results.
MSv36878V1
Data output D0 D1 D2
Clock
Data input D0 D1 D2
t(CK) tw(CKH) tw(CKL)
tr(CK) tf(CK)
ts(IN) th(IN)
tv(OUT) th(OUT)
MSv36879V1
Data output D0 D2 D4
Clock
Data input D0 D2 D4
t(CK) tw(CKH) tw(CKL)
tr(CK) tf(CK)
tsf(IN) thf(IN)
tvf(OUT) thr(OUT)
D1 D3 D5
D1 D3 D5
tvr(OUT) thf(OUT)
tsr(IN) thr(IN)
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SAI characteristics
Unless otherwise specified, the parameters given in Table 88 for SAI are derived
from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized inTable 23: General operating conditions, with
the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 10
•Capacitive load C = 30 pF
•Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output
alternate function characteristics (CK,SD,FS).
Table 88. SAI characteristics(1)
Symbol Parameter Conditions Min Max Unit
fMCLK SAI Main clock output - - 50 MHz
fCK SAI clock frequency(2)
Master transmitter
2.7 VDD 3.6
Voltage Range 1
-18.5
MHz
Master transmitter
1.71 VDD 3.6
Voltage Range 1
-12.5
Master receiver
Voltage Range 1 -25
Slave transmitter
2.7 VDD 3.6
Voltage Range 1
-22.5
Slave transmitter
1.71 VDD 3.6
Voltage Range 1
-14.5
Slave receiver
Voltage Range 1 -25
Voltage Range 2 - 12.5
tv(FS) FS valid time
Master mode
2.7 VDD 3.6 -22
ns
Master mode
1.71 VDD 3.6 -40
th(FS) FS hold time Master mode 10 - ns
tsu(FS) FS setup time Slave mode 1 - ns
th(FS) FS hold time Slave mode 2 - ns
tsu(SD_A_MR) Data input setup time
Master receiver 2.5 -
ns
tsu(SD_B_SR) Slave receiver 3 -
th(SD_A_MR) Data input hold time
Master receiver 8 -
ns
th(SD_B_SR) Slave receiver 4 -
DS10741 Rev 2 185/229
STM32L471xx Electrical characteristics
206
Figure 34. SAI master timing waveforms
tv(SD_B_ST) Data output valid time
Slave transmitter (after enable edge)
2.7 VDD 3.6 -22
ns
Slave transmitter (after enable edge)
1.71 VDD 3.6 -34
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 10 - ns
tv(SD_A_MT) Data output valid time
Master transmitter (after enable edge)
2.7 VDD 3.6 -27
ns
Master transmitter (after enable edge)
1.71 VDD 3.6 -40
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 10 - ns
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
Table 88. SAI characteristics(1) (continued)
Symbol Parameter Conditions Min Max Unit
MS32771V1
SAI_SCK_X
SAI_FS_X
(output)
1/fSCK
SAI_SD_X
(transmit)
tv(FS)
Slot n
SAI_SD_X
(receive)
th(FS)
Slot n+2
tv(SD_MT) th(SD_MT)
Slot n
tsu(SD_MR) th(SD_MR)
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Figure 35. SAI slave timing waveforms
SDMMC characteristics
Unless otherwise specified, the parameters given in Table 89 for SDIO are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 23: General operating conditions, with the following
configuration:
•Output speed is set to OSPEEDRy[1:0] = 11
•Capacitive load C = 30 pF
•Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output
characteristics.
Table 89. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V(1)
Symbol Parameter Conditions Min Typ Max Unit
fPP Clock frequency in data transfer mode - 0 - 50 MHz
- SDIO_CK/fPCLK2 frequency ratio - - - 4/3 -
tW(CKL) Clock low time fPP = 50 MHz 8 10 - ns
tW(CKH) Clock high time fPP = 50 MHz 8 10 - ns
CMD, D inputs (referenced to CK) in MMC and SD HS mode
tISU Input setup time HS fPP = 50 MHz 2 - - ns
tIH Input hold time HS fPP = 50 MHz 4.5 - - ns
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV Output valid time HS fPP = 50 MHz - 12 14 ns
tOH Output hold time HS fPP = 50 MHz 9 - - ns
CMD, D inputs (referenced to CK) in SD default mode
tISUD Input setup time SD fPP = 50 MHz 2 - - ns
tIHD Input hold time SD fPP = 50 MHz 4.5 - - ns
MS32772V1
SAI_SCK_X
SAI_FS_X
(input)
SAI_SD_X
(transmit)
tsu(FS)
Slot n
SAI_SD_X
(receive)
tw(CKH_X) th(FS)
Slot n+2
tv(SD_ST) th(SD_ST)
Slot n
tsu(SD_SR)
tw(CKL_X)
th(SD_SR)
1/fSCK
CK
D, CMD
(mnpm)
D, CMD
(\nput)
‘mew
L Won)
‘OH
IX
Msu”
aMAES7
DS10741 Rev 2 187/229
STM32L471xx Electrical characteristics
206
Figure 36. SDIO high-speed mode
CMD, D outputs (referenced to CK) in SD default mode
tOVD Output valid default time SD fPP = 50 MHz - 4.5 5 ns
tOHD Output hold default time SD fPP = 50 MHz 0 - - ns
1. Guaranteed by characterization results.
Table 90. eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V(1)(2)
1. Guaranteed by characterization results.
2. CLOAD = 20pF.
Symbol Parameter Conditions Min Typ Max Unit
fPP Clock frequency in data transfer mode - 0 - 50 MHz
- SDIO_CK/fPCLK2 frequency ratio - - - 4/3 -
tW(CKL) Clock low time fPP = 50 MHz 8 10 - ns
tW(CKH) Clock high time fPP = 50 MHz 8 10 - ns
CMD, D inputs (referenced to CK) in eMMC mode
tISU Input setup time HS fPP = 50 MHz 0 - - ns
tIH Input hold time HS fPP = 50 MHz 5 - - ns
CMD, D outputs (referenced to CK) in eMMC mode
tOV Output valid time HS fPP = 50 MHz - 13.5 15.5 ns
tOH Output hold time HS fPP = 50 MHz 9 - - ns
Table 89. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
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STM32L471xx Electrical characteristics
206
6.3.28 FSMC characteristics
Unless otherwise specified, the parameters given in Table 91 to Table 104 for the FMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 23, with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 11
•Capacitive load C = 30 pF
•Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings
Figure 38 through Figure 41 represent asynchronous waveforms and Table 91 through
Table 98 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
•AddressSetupTime = 0x1
•AddressHoldTime = 0x1
•DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
•BusTurnAroundDuration = 0x0
In all timing tables, the THCLK is the HCLK clock period.
{
RR
T
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Figure 38. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
Data
FMC_NE
FMC_NBL[1:0]
FMC_D[15:0]
t
v(BL_NE)
th(Data_NE)
FMC_NOE
Address
FMC_A[25:0]
t
v(A_NE)
FMC_NWE
tsu(Data_NE)
tw(NE)
MS32753V1
w(NOE)
ttv(NOE_NE) th(NE_NOE)
th(Data_NOE)
th(A_NOE)
th(BL_NOE)
tsu(Data_NOE)
FMC_NADV (1)
tv(NADV_NE)
tw(NADV)
FMC_NWAIT
tsu(NWAIT_NE)
th(NE_NWAIT)
DS10741 Rev 2 191/229
STM32L471xx Electrical characteristics
206
Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2)
1. CL = 30 pF.
2. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 2THCLK-0.5 2THCLK+0.5
ns
tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 1
tw(NOE) FMC_NOE low time 2THCLK-0.5 2THCLK+1
th(NE_NOE) FMC_NOE high to FMC_NE high hold time 0 -
tv(A_NE) FMC_NEx low to FMC_A valid - 3.5
th(A_NOE) Address hold time after FMC_NOE high 0 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 2
th(BL_NOE) FMC_BL hold time after FMC_NOE high 0 -
tsu(Data_NE) Data to FMC_NEx high setup time THCLK-1 -
tsu(Data_NOE) Data to FMC_NOEx high setup time THCLK-0.5 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 1
tw(NADV) FMC_NADV low time - THCLK+0.5
Table 92. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT
timings(1)(2)
1. CL = 30 pF.
2. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 7THCLK-0.5 7THCLK+0.5
ns
tw(NOE) FMC_NWE low time 5THCLK-0.5 5THCLK+0.5
tw(NWAIT) FMC_NWAIT low time THCLK-0.5 -
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK+2 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK -
Electrical characteristics STM32L471xx
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Figure 39. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
Table 93. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2)
1. CL = 30 pF.
2. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 3THCLK-1 3THCLK+2
ns
tv(NWE_NE) FMC_NEx low to FMC_NWE low THCLK-0.5 THCLK+1.5
tw(NWE) FMC_NWE low time THCLK-1 THCLK+1
th(NE_NWE) FMC_NWE high to FMC_NE high hold time THCLK-0.5 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0
th(A_NWE) Address hold time after FMC_NWE high THCLK-1 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 1.5
th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK-0.5 -
tv(Data_NE) Data to FMC_NEx low to Data valid - THCLK+4
th(Data_NWE) Data hold time after FMC_NWE high THCLK+1 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 1
tw(NADV) FMC_NADV low time - THCLK+0.5
NBL
Data
FMC_NEx
FMC_NBL[1:0]
FMC_D[15:0]
t
v(BL_NE)
th(Data_NWE)
FMC_NOE
Address
FMC_A[25:0]
t
v(A_NE)
tw(NWE)
FMC_NWE
tv(NWE_NE) th(NE_NWE)
th(A_NWE)
th(BL_NWE)
tv(Data_NE)
tw(NE)
MS32754V1
FMC_NADV (1)
tv(NADV_NE)
tw(NADV)
FMC_NWAIT
tsu(NWAIT_NE)
th(NE_NWAIT)
DS10741 Rev 2 193/229
STM32L471xx Electrical characteristics
206
Figure 40. Asynchronous multiplexed PSRAM/NOR read waveforms
Table 94. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT
timings(1)(2)
1. CL = 30 pF.
2. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 8THCLK+0.5 8THCLK+0.5
ns
tw(NWE) FMC_NWE low time 6THCLK-0.5 6THCLK+0.5
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK+2 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+2 -
NBL
Data
FMC_ NBL[1:0]
FMC_ AD[15:0]
t
v(BL_NE)
th(Data_NE)
Address
FMC_ A[25:16]
t
v(A_NE)
FMC_NWE
tv(A_NE)
MS32755V1
Address
FMC_NADV
tv(NADV_NE)
tw(NADV)
tsu(Data_NE)
t
h(AD_NADV)
FMC_ NE
FMC_NOE
tw(NE)
tw(NOE)
tv(NOE_NE) th(NE_NOE)
th(A_NOE)
th(BL_NOE)
tsu(Data_NOE) th(Data_NOE)
FMC_NWAIT
tsu(NWAIT_NE)
th(NE_NWAIT)
Electrical characteristics STM32L471xx
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Table 95. Asynchronous multiplexed PSRAM/NOR read timings(1)(2)
1. CL = 30 pF.
2. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 3THCLK-0.5 3THCLK+2
ns
tv(NOE_NE) FMC_NEx low to FMC_NOE low 2THCLK-0.5 2THCLK+0.5
tw(NOE) FMC_NOE low time THCLK+0.5 THCLK+1
th(NE_NOE) FMC_NOE high to FMC_NE high hold time 0 -
tv(A_NE) FMC_NEx low to FMC_A valid - 3
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 1
tw(NADV) FMC_NADV low time THCLK-0.5 THCLK+1
th(AD_NADV)
FMC_AD(address) valid hold time after
FMC_NADV high 0 -
th(A_NOE) Address hold time after FMC_NOE high THCLK-0.5 -
th(BL_NOE) FMC_BL time after FMC_NOE high 0 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 2
tsu(Data_NE) Data to FMC_NEx high setup time THCLK-2 -
tsu(Data_NOE) Data to FMC_NOE high setup time THCLK-1 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
Table 96. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)(2)
1. CL = 30 pF.
2. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 8THCLK+2 8THCLK+4
ns
tw(NOE) FMC_NWE low time 5THCLK-1 5THCLK+1.5
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK+1.5 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+1 -
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STM32L471xx Electrical characteristics
206
Figure 41. Asynchronous multiplexed PSRAM/NOR write waveforms
NBL
Data
FMC_ NEx
FMC_ NBL[1:0]
FMC_ AD[15:0]
t
v(BL_NE)
th(Data_NWE)
FMC_NOE
Address
FMC_ A[25:16]
t
v(A_NE)
tw(NWE)
FMC_NWE
tv(NWE_NE) th(NE_NWE)
th(A_NWE)
th(BL_NWE)
tv(A_NE)
tw(NE)
MS32756V1
Address
FMC_NADV
tv(NADV_NE)
tw(NADV)
tv(Data_NADV)
t
h(AD_NADV)
FMC_NWAIT
tsu(NWAIT_NE)
th(NE_NWAIT)
Electrical characteristics STM32L471xx
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Synchronous waveforms and timings
Figure 42 through Figure 45 represent synchronous waveforms and Table 99
through Table 102 provide the corresponding timings. The results shown in these
tables are obtained with the following FMC configuration:
•BurstAccessMode = FMC_BurstAccessMode_Enable
•MemoryType = FMC_MemoryType_CRAM
•WriteBurst = FMC_WriteBurst_Enable
•CLKDivision = 1
•DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
Table 97. Asynchronous multiplexed PSRAM/NOR write timings(1)(2)
1. CL = 30 pF.
2. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 4THCLK-0.5 4THCLK+2
ns
tv(NWE_NE) FMC_NEx low to FMC_NWE low THCLK-0.5 THCLK+1
tw(NWE) FMC_NWE low time 2xTHCLK-1.5 2xTHCLK+1.
5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time THCLK-0.5 -
tv(A_NE) FMC_NEx low to FMC_A valid - 3
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 1
tw(NADV) FMC_NADV low time THCLK-0.5 THCLK+1
th(AD_NADV)
FMC_AD(adress) valid hold time after
FMC_NADV high THCLK-2 -
th(A_NWE) Address hold time after FMC_NWE high THCLK-1 -
th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK+0.5 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 1.5
tv(Data_NADV) FMC_NADV high to Data valid - THCLK +4
th(Data_NWE) Data hold time after FMC_NWE high THCLK +0.5 -
Table 98. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)
1. CL = 30 pF.
2. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 9THCLK-0.5 9THCLK+2
ns
tw(NWE) FMC_NWE low time 7THCLK-1.5 7THCLK+1.5
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK+2 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK-3 -
M3327 5555
DS10741 Rev 2 197/229
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206
In all timing tables, the THCLK is the HCLK clock period.
Figure 42. Synchronous multiplexed NOR/PSRAM read timings
FMC_CLK
FMC_NEx
FMC_NADV
FMC_A[25:16]
FMC_NOE
FMC_AD[15:0] AD[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tw(CLK) tw(CLK)
Data latency = 0
BUSTURN = 0
td(CLKL-NExL) td(CLKH-NExH)
td(CLKL-NADVL)
td(CLKL-AV)
td(CLKL-NADVH)
td(CLKH-AIV)
td(CLKL-NOEL) td(CLKH-NOEH)
td(CLKL-ADV)
td(CLKL-ADIV)
tsu(ADV-CLKH)
th(CLKH-ADV)
tsu(ADV-CLKH) th(CLKH-ADV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32757V1
Electrical characteristics STM32L471xx
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Table 99. Synchronous multiplexed NOR/PSRAM read timings(1)(2)
1. CL = 30 pF.
2. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(CLK) FMC_CLK period 2THCLK-1 -
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK+0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 3.5
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 1.5
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high THCLK+1 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 4
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 0 -
th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 2.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 0 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 4 -
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STM32L471xx Electrical characteristics
206
Figure 43. Synchronous multiplexed PSRAM write timings
MSv38001V1
FMC_CLK
FMC_NEx
FMC_NADV
FMC_A[25:16]
FMC_NWE
FMC_AD[15:0] AD[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tw(CLK) tw(CLK)
Data latency = 0
BUSTURN = 0
td(CLKL-NExL) td(CLKH-NExH)
td(CLKL-NADVL)
td(CLKL-AV)
td(CLKL-NADVH)
td(CLKH-AIV)
td(CLKH-NWEH)
td(CLKL-NWEL)
td(CLKH-NBLH)
td(CLKL-ADV)
td(CLKL-ADIV) td(CLKL-Data)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
td(CLKL-Data)
FMC_NBL
Electrical characteristics STM32L471xx
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Table 100. Synchronous multiplexed PSRAM write timings(1)(2)
1. CL = 30 pF.
2. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(CLK) FMC_CLK period 2THCLK-1 -
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK+0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 3.5
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 2
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high THCLK+1 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 4
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 5.5
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2.5
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK+1 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 0 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 4 -
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206
Figure 44. Synchronous non-multiplexed NOR/PSRAM read timings
Table 101. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2)
Symbol Parameter Min Max Unit
tw(CLK) FMC_CLK period 2THCLK -
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2.5
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK-0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0.5 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 3.5
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 2
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high THCLK-0.5 -
tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 0 -
th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 0 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 4 -
FMC_CLK
FMC_NEx
FMC_A[25:0]
FMC_NOE
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tw(CLK) tw(CLK)
Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)
td(CLKL-AV) td(CLKH-AIV)
td(CLKL-NOEL) td(CLKH-NOEH)
tsu(DV-CLKH) th(CLKH-DV)
tsu(DV-CLKH) th(CLKH-DV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32759V1
FMC_NADV
td(CLKL-NADVL) td(CLKL-NADVH)
Electrical characteristics STM32L471xx
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Figure 45. Synchronous non-multiplexed PSRAM write timings
1. CL = 30 pF.
2. Guaranteed by characterization results.
MSv38002V1
FMC_CLK
FMC_NEx
FMC_A[25:0]
FMC_NWE
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
tw(CLK) tw(CLK)
Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)
td(CLKL-AV) td(CLKH-AIV)
td(CLKH-NWEH)
td(CLKL-NWEL)
td(CLKL-Data)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
FMC_NADV
td(CLKL-NADVL) td(CLKL-NADVH)
td(CLKL-Data)
FMC_NBL
td(CLKH-NBLH)
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STM32L471xx Electrical characteristics
206
NAND controller waveforms and timings
Figure 46 through Figure 49 represent synchronous waveforms, and Table 103 and
Table 104 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
•COM.FMC_SetupTime = 0x02
•COM.FMC_WaitSetupTime = 0x03
•COM.FMC_HoldSetupTime = 0x02
•COM.FMC_HiZSetupTime = 0x03
•ATT.FMC_SetupTime = 0x01
•ATT.FMC_WaitSetupTime = 0x03
•ATT.FMC_HoldSetupTime = 0x02
•ATT.FMC_HiZSetupTime = 0x03
•Bank = FMC_Bank_NAND
•MemoryDataWidth = FMC_MemoryDataWidth_16b
•ECC = FMC_ECC_Enable
•ECCPageSize = FMC_ECCPageSize_512Bytes
•TCLRSetupTime = 0
•TARSetupTime = 0
In all timing tables, the THCLK is the HCLK clock period.
Table 102. Synchronous non-multiplexed PSRAM write timings(1)(2)
Symbol Parameter Min Max Unit
tw(CLK) FMC_CLK period 2THCLK-0.5 -
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK+0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 2.5 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 5
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK-1 -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 2
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high THCLK-1 -
td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 4.5
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 1.5 -
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK+1 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 0 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 4 -
1. CL = 30 pF.
2. Guaranteed by characterization results.
fl
Electrical characteristics STM32L471xx
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Figure 46. NAND controller waveforms for read access
Figure 47. NAND controller waveforms for write access
Figure 48. NAND controller waveforms for common memory read access
MSv38003V1
FMC_NWE
FMC_NOE (NRE)
FMC_D[15:0]
tsu(D-NOE) th(NOE-D)
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NCEx
td(NCE-NOE) th(NOE-ALE)
MSv38004V1
th(NWE-D)
tv(NWE-D)
FMC_NWE
FMC_NOE (NRE)
FMC_D[15:0]
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NCEx
td(NCE-NWE) th(NWE-ALE)
MSv38005V1
FMC_NWE
FMC_NOE
FMC_D[15:0]
tw(NOE)
tsu(D-NOE) th(NOE-D)
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NCEx
td(NCE-NOE) th(NOE-ALE)
DS10741 Rev 2 205/229
STM32L471xx Electrical characteristics
206
Figure 49. NAND controller waveforms for common memory write access
Table 103. Switching characteristics for NAND Flash read cycles(1)(2)
1. CL = 30 pF.
2. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
Tw(N0E) FMC_NOE low width 4THCLK-1 4THCLK+1
ns
Tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 16 -
Th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 6 -
Td(NCE-NOE) FMC_NCE valid before FMC_NOE low - 3THCLK+1
Th(NOE-ALE) FMC_NOE high to FMC_ALE invalid 2THCLK-2 -
Table 104. Switching characteristics for NAND Flash write cycles(1)(2)
1. CL = 30 pF.
2. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
Tw(NWE) FMC_NWE low width 4THCLK-1 4THCLK+1
ns
Tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid - 2.5
Th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 3THCLK-4 -
Td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5THCLK-3 -
Td(NCE_NWE) FMC_NCE valid before FMC_NWE low - 3THCLK+1
Th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 2THCLK-2 -
MSv38006V1
tw(NWE)
th(NWE-D)
tv(NWE-D)
FMC_NWE
FMC_NOE
FMC_D[15:0]
td(D-NWE)
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NCEx
td(NCE-NWE) th(NOE-ALE)
Electrical characteristics STM32L471xx
206/229 DS10741 Rev 2
6.3.29 SWPMI characteristics
The Single Wire Protocol Master Interface (SWPMI) and the associated SWPMI_IO
transceiver are compliant with the ETSI TS 102 613 technical specification.
Table 105. SWPMI electrical characteristics(1)
1. Guaranteed by design.
Symbol Parameter Conditions Min Typ Max Unit
tSWPSTART SWPMI regulator startup time SWP Class B
2.7 V VDD 3,3V - - 300 s
tSWPBIT SWP bit duration
VCORE voltage range 1 500 - -
ns
VCORE voltage range 2 620 - -
DS10741 Rev 2 207/229
STM32L471xx Package information
225
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1 LQFP144 package information
Figure 50. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline
1. Drawing is not to scale.
e
IDENTIFICATION
PIN 1
GAUGE PLANE
0.25 mm
SEATING
PLANE
D
D1
D3
E3
E1
E
K
ccc C
C
136
37
144
109
108 73
72
1A_ME_V4
A2
A
A1
L1
L
c
b
A1
Package information STM32L471xx
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Table 106. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 21.800 22.000 22.200 0.8583 0.8661 0.8740
D1 19.800 20.000 20.200 0.7795 0.7874 0.7953
D3 - 17.500 - - 0.6890 -
E 21.800 22.000 22.200 0.8583 0.8661 0.8740
E1 19.800 20.000 20.200 0.7795 0.7874 0.7953
E3 - 17.500 - - 0.6890 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0°3.5°7° 0°3.5°7°
ccc - - 0.080 - - 0.0031
l—H—l
Package information STM32L471xx
210/229 DS10741 Rev 2
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 52. LQFP144 marking (package top view)
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
MSv36850V2
Date code
Pin 1 identifier
STM32L471ZGT6
Product identification(1)
Revision code
YWW
Optional gate mark
3
A
<7 4»="" ._‘:|="" $$ooooooooo$="" oooooooooooo="" fix="" 000000000000="" 000000000000="" 000000000000="" oooooqpooooo="" 000000000000="" 000000000000="" 000000000000="" 000000000000="" oododoooooo$="" oodoooooo\00$="" w="" $="" ®="" \\="" ®="">DS10741 Rev 2 211/229
STM32L471xx Package information
225
7.2 UFBGA144 package information
Figure 53. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package outline
1. Drawing is not to scale.
Table 107. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package mechanical data
Symbol
millimeters inches(1)
Min. Typ. Max. Min. Typ. Max.
A 0.460 0.530 0.600 0.0181 0.0209 0.0236
A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 - 0.130 - - 0.0051 -
A4 - 0.320 - - 0.0126 -
b 0.360 0.400 0.440 0.0091 0.0110 0.0130
D 9.950 10.000 10.050 0.2736 0.2756 0.2776
D1 8.750 8.800 8.850 0.2343 0.2362 0.2382
E 9.950 10.000 10.050 0.2736 0.2756 0.2776
E1 8.750 8.800 8.850 0.2343 0.2362 0.2382
e 0.750 0.800 0.850 - 0.0197 -
F 0.550 0.600 0.650 0.0177 0.0197 0.0217
A02Y_ME_V2
Seating plane
A1
eF
F
D
M
Øb (144 balls)
A
E
TOP VIEWBOTTOM VIEW
112
e
A
A2
B
A
C
ddd Z
D1
E1
eee C A B
fff
Ø
Ø
M
MC
A3
A4
A1 ball
identifier
A1 ball
index area
0000000000
0000000000
000000000
000000000
000000000
000000000
000000000
000000000
000000000
000000000
000000000
000000000
0000000000
000000000000
0000000fl0000
Package information STM32L471xx
212/229 DS10741 Rev 2
Figure 54. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package recommended footprint
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
ddd - - 0.080 - - 0.0039
eee - - 0.150 - - 0.0059
fff - - 0.080 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 108. UFBGA144 recommended PCB design rules (0.80 mm pitch BGA)
Dimension Recommended values
Pitch 0.80 mm
Dpad 0.400 mm
Dsm 0.550 mm typ. (depends on the soldermask
registration tolerance)
Stencil opening 0.400 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.120 mm
Table 107. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package mechanical data (continued)
Symbol
millimeters inches(1)
Min. Typ. Max. Min. Typ. Max.
A02Y_FP_V1
Dpad
Dsm
Z
DS10741 Rev 2 213/229
STM32L471xx Package information
225
Figure 55. UFBGA144 marking (package top view)
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
MSv50914V1
Y WW
Product
identification(1)
Additional
information
Ball A1
indentifier
ZGJ6
Y
STM32L471
Date code
*, F ,1
490000000006 ff;
+ 000000000000 ///
000000000000
000000000000
0000 0000
0000 0+0 0000
0000 00 0000
0000 0000
000000000000
000000000000
wooooooooooo
wooooooooooo
f »
$Deee®CAIB\
®m®
A
+T+ ++ \
—><—>Package information STM32L471xx
214/229 DS10741 Rev 2
7.3 UFBGA132 package information
Figure 56. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array
package outline
1. Drawing is not to scale.
Table 109. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array
package mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A - - 0.600 - - 0.0236
A1 - - 0.110 - - 0.0043
A2 - 0.450 - - 0.0177 -
A3 - 0.130 - - 0.0051 -
A4 - 0.320 - - 0.0126 -
b 0.240 0.290 0.340 0.0094 0.0114 0.0134
D 6.850 7.000 7.150 0.2697 0.2756 0.2815
D1 - 5.500 - - 0.2165 -
E 6.850 7.000 7.150 0.2697 0.2756 0.2815
E1 - 5.500 - - 0.2165 -
UFBGA132_A0G8_ME_V2
SEATING
PLANE
A4
A1
eZ
Z
D
A
eee C A B
fff
Øb (132 balls)
Ø
Ø
M
M
M
E
TOP VIEWBOTTOM VIEW
12 1
e
A
A2
C
A
B
A1 ball identifier
b
D1
E1
ddd C
A3
©©©© ©© ©©©©
©©©© ©© ©©©©
©©©© ©©©©
©©©©©©©©©©©©
©©©©©©©©©©©©
©©©©©©©©©©©©
©©©©©©©©©©©©
DS10741 Rev 2 215/229
STM32L471xx Package information
225
Figure 57. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array
package recommended footprint
e - 0.500 - - 0.0197 -
Z - 0.750 - - 0.0295 -
ddd - 0.080 - - 0.0031 -
eee - 0.150 - - 0.0059 -
fff - 0.050 - - 0.0020 -
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 110. UFBGA132 recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values
Pitch 0.5 mm
Dpad 0.280 mm
Dsm 0.370 mm typ. (depends on the soldermask
registration tolerance)
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm
Ball diameter 0.280 mm
Table 109. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array
package mechanical data (continued)
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
UFBGA132_A0G8_FP_V1
Dpad
Dsm
£70 K
Package information STM32L471xx
216/229 DS10741 Rev 2
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 58. UFBGA132 marking (package top view)
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
MSv36853V3
STM32L
471QGI6
Revision code
Product identification(1)
Date code
Ball A1 indentifier
3
YWW
DS10741 Rev 2 217/229
STM32L471xx Package information
225
7.4 LQFP100 package information
Figure 59. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline
1. Drawing is not to scale.
Table 111. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 - 12.000 - - 0.4724 -
E 15.800 16.000 16.200 0.6220 0.6299 0.6378
e
IDENTIFICATION
PIN 1
GAUGE PLANE
0.25 mm
SEATING PLANE
D
D1
D3
E3
E1
E
K
ccc C
C
125
26
100
76
75 51
50
1L_ME_V5
A2
A
A1
L1
L
c
b
A1
,7l]|]|]|]|]|]|]|]|]|]|]|] |]|]|]|]|] |]|]|]|]|]
|]|]|]|]|]|]|]|]|]|]|]|] |]|]|]|]|]|]|]|]|]|]|]|]
|]|]|]|]|]|]|]|][||]|] |]|]|]|]|]|]|]|][||]|]
z:
z:
z:
z:
:=.
E
III
E
III
E
III
z:
z:
z:
z:
z:
z:
E
E
E
E
E
E
E
f
Package information STM32L471xx
218/229 DS10741 Rev 2
Figure 60. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
E1 13.800 14.000 14.200 0.5433 0.5512 0.5591
E3 - 12.000 - - 0.4724 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 111. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data (continued)
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
75 51
5076 0.5
0.3
16.7 14.3
100 26
12.3
25
1.2
16.7
1
ai14906c
N\
DS10741 Rev 2 219/229
STM32L471xx Package information
225
Figure 61. LQFP100 marking (package top view)
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
MSv36847V2
Revision code
Product identification(1)
Date code
Pin 1
indentifier
STM32L471
VGT6 3
YWW
Optional gate mark
HHMMMMMWM
E i g
E 1 :
Package information STM32L471xx
220/229 DS10741 Rev 2
7.5 LQFP64 package information
Figure 62. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline
1. Drawing is not to scale.
Table 112. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D - 12.000 - - 0.4724 -
D1 - 10.000 - - 0.3937 -
D3 - 7.500 - - 0.2953 -
E - 12.000 - - 0.4724 -
E1 - 10.000 - - 0.3937 -
5W_ME_V3
A1
A2
A
SEATING PLANE
ccc C
b
C
c
A1
L
L1
K
IDENTIFICATION
PIN 1
D
D1
D3
e
116
17
32
33
48
49
64
E3
E1
E
GAUGE PLANE
0.25 mm
UH Hflflfl flflflflflflflfl
flflflflflflflflflflfl HUD
flflflfl HHHHHHHH
4,:
fl
UUUUHUUUHUHUUHU ‘in"
Pi
DS10741 Rev 2 221/229
STM32L471xx Package information
225
Figure 63. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
E3 - 7.500 - - 0.2953 -
e - 0.500 - - 0.0197 -
K 0°3.5°7° 0°3.5°7°
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 112. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data (continued)
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
48
32
49
64 17
116
1.2
0.3
33
10.3
12.7
10.3
0.5
7.8
12.7
ai14909c
"(1)
Package information STM32L471xx
222/229 DS10741 Rev 2
Figure 64. LQFP64 marking (package top view)
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
MSv36856V3
Date code
Pin 1 identifier
STM32L471
RGT6
Product identification(1)
Revision code
3
Y WW
DS10741 Rev 2 223/229
STM32L471xx Package information
225
7.6 Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 22: General operating conditions.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x JA)
Where:
•TA max is the maximum ambient temperature in °C,
•JA is the package junction-to-ambient thermal resistance, in °C/W,
•PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
•PINT max is the product of all IDDXXX and VDDXXX, expressed in Watts. This is the
maximum chip internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = (VOL × IOL) + ((VDDIOx – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
7.6.1 Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
7.6.2 Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Ordering information.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32L471xx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range will be best suited to the application.
Table 113. Package thermal characteristics
Symbol Parameter Value Unit
JA
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch 45
°C/W
Thermal resistance junction-ambient
LQFP100 - 14 × 14mm 42
Thermal resistance junction-ambient
LQFP144 - 20 × 20 mm 32
Thermal resistance junction-ambient
UFBGA144 - 10 × 10 mm 53
Thermal resistance junction-ambient
UFBGA132 - 7 × 7 mm 55
Package information STM32L471xx
224/229 DS10741 Rev 2
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW:
PDmax = 175 + 272 = 447 mW
Using the values obtained in Table 113 TJmax is calculated as follows:
– For LQFP64, 45 °C/W
TJmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.115 °C = 102.115 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C) see Section 8:
Ordering information.
In this case, parts must be ordered at least with the temperature range suffix 6 (see Part
numbering).
Note: With this given PDmax we can find the TAmax allowed for a given device temperature range
(order code suffix 6 or 7).
Suffix 6: TAmax = TJmax - (45°C/W × 447 mW) = 105-20.115 = 84.885 °C
Suffix 7: TAmax = TJmax - (45°C/W × 447 mW) = 125-20.115 = 104.885 °C
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
Assuming the following application conditions:
Maximum ambient temperature TAmax = 100 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 3.5 V= 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW
Using the values obtained in Table 113 TJmax is calculated as follows:
– For LQFP64, 45 °C/W
TJmax = 100 °C + (45 °C/W × 134 mW) = 100 °C + 6.03 °C = 106.03 °C
This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C).
DS10741 Rev 2 225/229
STM32L471xx Package information
225
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8: Ordering information) unless we reduce the power dissipation in order to be able
to use suffix 6 parts.
Refer to Figure 65 to select the required temperature range (suffix 6 or 7) according to your
ambient temperature or power requirements.
Figure 65. LQFP64 PD max vs. TA
MSv32143V1
600
0
100
200
300
400
500
700
65 75 85 95 105 115 125 135
Suffix 6
Suffix 7
PD (mW)
TA (°C)
%
Ordering information STM32L471xx
226/229 DS10741 Rev 2
8 Ordering information
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Table 114. STM32L471xx ordering information scheme
Example: STM32 L 471 R G T 6 TR
Device family
STM32 = Arm® based 32-bit microcontroller
Product type
L = ultra-low-power
Device subfamily
471: STM32L471xx
Pin count
R = 64 pins
V = 100 pins
Q = 132 pins
Z = 144 pins
Flash memory size
E = 512 KB of Flash memory
G = 1 MB of Flash memory
Package
T = LQFP ECOPACK®2
I = UFBGA (7 × 7 mm) ECOPACK®2
J = UFBGA (10 × 10 mm) ECOPACK®2
Temperature range
6 = Industrial temperature range, -40 to 85 °C (105 °C junction)
7 = Industrial temperature range, -40 to 105 °C (125 °C junction)
3 = Industrial temperature range, -40 to 125 °C (130 °C junction)
Packing
TR = tape and reel
xxx = programmed parts
DS10741 Rev 2 227/229
STM32L471xx Revision history
228
9 Revision history
Table 115. Document revision history
Date Revision Changes
04-Fev-2016 1 Initial release.
31-May-2018 2
Updates in the whole document:
– Added UFBGA144 package
– Updated all DFSDM references to DFSDM1
– All the mentions in the document saying “Guaranteed
based on test during characterization...” were updated
to “Guaranteed by characterization results...”
Added:
–Section 3.23.5: Infrared interface (IRTIM)
–Section 6.3.16: Extended interrupt and event
controller input (EXTI) characteristics
–Section 6.3.29: SWPMI characteristics
–Table 44: Wakeup time using USART/LPUART
–Figure 3: Power-up/down sequence
–Figure 5: Voltage reference buffer
Sections updated:
–Section : Features
–Section 3.9.1: Power supply schemes
–Section 3.23.6: Independent watchdog (IWDG)
–Section 3.27: Low-power universal asynchronous
receiver transmitter (LPUART)
–Section 6.2: Absolute maximum ratings.
–Section 6.3.2: Operating conditions at power-up /
power-down.
Tables updated:
–Table 6: STM32L471xx peripherals interconnect
matrix to add TIM16/TIM17
–Table 16: STM32L471xx pin definitions for: on pin PA3
updated I/O structure from TT to TT_a, on pin
VSSA/VREF- updated type to supply pin, on pin PG7
updated alternate function FMC_INT3 to FMC_INT, on
pin PG9 updated alternate function FMC_NCE3 to
FMC_NCE
–Table 17: Alternate function AF0 to AF7
–Table 18: Alternate function AF8 to AF15
–Table 23: General operating conditions
–Table 26: Embedded internal voltage reference
–Table 65: Analog switches booster characteristics:
deleted VBOOST
–Table 75: COMP characteristics to add Ibias
parameter.
Figure updated:
–Figure 1: STM32L471xx block diagram.
Revision history STM32L471xx
228/229 DS10741 Rev 2
31-May-2018 2
(continued)
Footnotes updated for:
–Table 16: STM32L471xx pin definitions
–Table 20: Voltage characteristics
–Table 36: Current consumption in Stop 1 mode
–Table 60: I/O static characteristics
–Table 75: COMP characteristics
–Table 25: Recommended NRST pin protection.
Table 115. Document revision history (continued)
Date Revision Changes
DS10741 Rev 2 229/229
STM32L471xx
229
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