CYUSB306X

@cYPREss

CYUSB306X

EZ-USB® CX3: MIPI CSI-2 to

SuperSpeed USB Bridge Controller

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 001-87516 Rev. *N Revised December 12, 2018

EZ-USB® CX3: MIPI CSI- 2 to SuperSpeed USB Bridge Co ntroller

Features

■Universal Serial Bus (USB) integration

❐USB 3.0 and USB 2.0 peripherals, compliant with USB 3.0

specification 1.0

❐5-Gbps USB 3.0 PHY compliant with PIPE 3.0

❐Thirty-two physical endpoints

■MIPI CSI-2 RX interface

❐MIPI CSI-2 compliant (Version 1.01, Revision 0.04 – 2nd A pril

2009)

❐Supports up to four data lanes (CYUSB3065 supports up to

four lanes; CYUSB3064 supports up to two lanes)

❐Each lane supports up to 1 Gbps (CYUSB3065 supports up

to four lanes; CYUSB3064 supports up to two lanes)

❐CCI interface for image sensor configuration

■Supports the following video data formats:

❐User-defined 8-bit

❐RAW8/10/12/14

❐YUV422 (CCIR/ITU 8/10bit), YUV444

❐RGB888/666/565

■Fully accessible 32-bit CPU

❐ARM926EJ-S core with 200-MHz operation

❐512-KB or 256-KB embedded SRAM

■Additional connectivity to the following peripherals:

❐I2C master controller at 1 MHz

❐I2S master (transmitter only) at sampling frequencies of

8 kHz, 16 kHz, 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, and

192 kHz

❐UART support of up to 4 Mbps

❐SPI master at 33 MHz

■Twelve GPIOs

■Ultra-low-power in core power-down mode

■Independent power domains for core and I/O

❐Core operation at 1.2 V

❐I2S, UART, and SPI operation at 1.8 to 3.3 V

❐I2C, I/O operation at 1.8 to 3.3 V

■10 × 10 mm, 0.8-mm pitch Pb-free ball grid array (BGA)

package

■EZ-USB® software development kit (SDK) for easy code

development

Applications

■Digital video cameras

■Digital still cameras

■Webcams

■Scanners

■Video conference systems

■Gesture-based control

■Surveillance cameras

■Medical imaging devices

■Video IP phones

■USB microscopes

■Industrial cameras

CYUSB306X

Document Number: 001-87516 Rev. *N Page 2 of 41

Logic Block Diagram

CPU

ARM926EJ-S

Program

RAM

EPs

JTAG

USB

Port

I2C

I2C_SCL

I2C_SDA

I2S

CLKIN_32

CLKIN

RESET#

SSRX-

SSRX+

SSTX-

SSTX+

D+

D-

TDI

TD0

TCK

TRST

TMS

HS/FS

Peripheral

UART

SPI

I2S_CLK

I2S_SD

I2S_WS

I2S_MCLK

MISO

MOSI

SSN

SCK

CTS

RTS

MIPI CSI-2 RX

interface

REFCLK

MCLK

XRST

XSHUTDOWN

CP / CM

D0P / D0M

D1P / D1M

D2P / D2M

D3P / D3M

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CYUSB306X

Document Number: 001-87516 Rev. *N Page 3 of 41

More Information

Cypress provides a wealth of data at www.cypress.com to help

you to select the right device for your design, and to help you to

quickly and effectively integrate the device into your design. For

a comprehensive list of resources refer to the cypress web page

for CX3 at www.cypress.com/CX3.

■Overview: USB Portfolio, USB Roadmap

■USB 3.0 Product Selectors: FX3, FX3S, CX3, GX3, HX3

■Application notes: Cypress offers a large number of USB appli-

cation notes covering a broad range of topics, from basic to

advanced level. Recommended application notes for getting

started with CX3 are:

❐AN75705 - Getting Started with EZ-USB FX3

❐AN90369 - How to Interface a MIPI CSI-2 Image Sensor With

EZ-USB® CX3

❐AN75779 - How to Implement an Image Sensor Interface with

EZ-USB® FX3™ in a USB Video Class (UVC) Framework

❐AN76405 - EZ-USB FX3 Boot Options

❐AN70707 - EZ-USB FX3/FX3S Hardware Design Guidelines

and Schematic Checklist

❐AN86947 - Optimizing USB 3.0 Throughput with EZ-USB

FX3

■Code Examples:

❐USB SuperSpeed

■Technical Reference Manual (TRM):

❐EZ-USB® CX3 Technical Reference Manual

■Knowledge Base Articles:

❐CX3 Firmware: Frequently Asked Questions - KBA91297

❐CX3 Hardware: Frequently Asked Questions - KBA91295

❐CX3 Application Software / USB Driver: Frequently Asked

Questions - KBA91298

❐Knowledge Base - Cypress Semiconductor Cage Code -

KBA89258

■Development Kits:

❐Ascella - Cypress® CX3™ THine® ISP 13MP reference

design kit (RDK)

❐Denebola - USB 3.0 UVC Reference Design Kit (RDK)

❐Tania - Cypress CX3™ Socionext® ISP reference design kit

(RDK) with Dual Sony Sensors

■Models:

❐CX3 Device OrCad Schematic Symbol

❐CYUSB306x - IBIS

EZ-USB Software Development Kit

Cypress delivers the complete firmware stack for CX3, in order

to easily integrate SuperSpeed USB into any embedded MIPI

image sensor application. The Software Development Kit (FX3

SDK) comes with tools, drivers and application examples, which

help accelerate application development. The FX3 SDK Setup

includes CX3 APIs and example firmware for OmniVision

OV5640 and Aptina AS0260 image sensor interface. The eclipse

plugin for the FX3 SDK accelerates CX3 firmware development

for any other image sensor.

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CYUSB306X

Document Number: 001-87516 Rev. *N Page 4 of 41

Contents

Functional Overview ........................................................ 5

Application Examples ...................................................... 5

USB Interface .................................................................... 6

ReNumeration ............................................................. 6

VBUS Overvoltage Protection ..................................... 6

MIPI CSI-2 RX Interface .................................................... 7

Additional Outputs ....................................................... 7

CPU .................................................................................... 7

JTAG Interface .................................................................. 7

Other Interfaces ................................................................ 7

UART Interface ............................................................7

I2C Interface ................................................................ 7

I2S Interface ................................................................ 8

SPI Interface ................................................................ 8

Boot Options ..................................................................... 8

Reset .................................................................................. 8

Hard Reset .................................................................. 8

Soft Reset .................................................................... 8

Clocking ............................................................................ 9

32-kHz Watchdog Timer Clock Input ...........................9

Power ............................................................................... 10

Power Modes ............................................................ 10

Configuration Options ................................................... 13

Digital I/Os ....................................................................... 13

GPIOs ............................................................................... 13

EMI ................................................................................... 13

System-level ESD ........................................................... 13

Pin Configuration ........................................................... 14

Pin Description ............................................................... 15

Electrical Specifications ................................................ 17

Absolute Maximum Ratings .......................................17

Operating Conditions ................................................. 17

DC Specifications ...................................................... 17

MIPI D-PHY Electrical Characteristics ...................... 19

Thermal Characteristics ................................................. 19

AC Timing Parameters ................................................... 20

MIPI Data to Clock Timing Reference ....................... 20

Reference Clock Specifications .................................20

MIPI CSI Signal

Low Power AC Characteristics ......................................... 21

AC Specifications ...................................................... 21

Serial Peripherals Timing .......................................... 22

Reset Sequence .............................................................. 27

Ordering Information ...................................................... 28

Ordering Code Definitions ......................................... 28

Package Diagram ............................................................ 29

Acronyms ........................................................................ 30

Document Conventions ................................................. 30

Units of Measure ....................................................... 30

Errata ............................................................................... 31

Part Numbers Affected .............................................. 31

Qualification Status ................................................... 31

Errata Summary ........................................................ 31

Document History Page ................................................. 37

Sales, Solutions, and Legal Information ...................... 41

Worldwide Sales and Design Support ....................... 41

Products .................................................................... 41

PSoC® Solutions ...................................................... 41

Cypress Developer Community ................................. 41

Technical Support ..................................................... 41

H \ H \\\ MW

CYUSB306X

Document Number: 001-87516 Rev. *N Page 5 of 41

Functional Overview

Cypress’s EZ-USB CX3 is the next-generation bridge controller

that can connect devices with the Mobile Industry Processor

Interface – Camera Serial Interface 2 (MIPI CSI-2) interface to

any USB 3.0 Host.

CX3 has a 4-lane CSI-2 receiver with up to 1 Gbps on each lane.

It supports video data formats such as RAW8/10/12/14, YUV422

(CCIR/ITU 8/10-bit), RGB888/666/565, and user-defined 8-bit.

CX3 has integrated the USB 3.0 and USB 2.0 physical layers

(PHYs) along with a 32-bit ARM926EJ-S microprocessor for

powerful data processing and for building custom applications.

CX3 contains 512 KB of on-chip SRAM (see Ordering

Information on page 28) for code and data. EZ-USB CX3 also

provides interfaces to connect to serial peripherals such as

UART, SPI, I2C, and I2S.

CX3 comes with application development tools. The software

development kit comes with application examples for acceler-

ating time-to-market.

CX3 complies with the USB 3.0 v1.0 specification and is also

backward compatible with USB 2.0. It also complies with the

MIPI CSI-2 v1.01, revision 0.04 specification dated 2nd April

2009.

Application Examples

In a typical application (see Figure 1), CX3 acts as the main

processor and connects to an image sensor, an audio device, or

camera control devices amongst others.

Figure 1. EZ-USB CX3 Example Application

Image

sensor

EZ-USB CX3

Autofocus, Pan, Tilt, Zoom,

Shutter control, Lighting, etc.

Audio

input

Audio

output

USB

Host

Clock

6-40 MHz

Clock

19.2 MHz

Power

subsystem

MIPI CSI-2

I2C I2SSPI

REFCLK CLKIN VDD

CYPRESS' ' EMaEnnEn w mmmw-

CYUSB306X

Document Number: 001-87516 Rev. *N Page 6 of 41

USB Interface

CX3 complies with the following specifications and supports the

following features:

■Supports USB peripheral functionality compliant with USB 3.0

Specification, Revision 1.0, and is also backward compatible

with the USB 2.0 Specification.

■As a peripheral, CX3 is capable of SuperSpeed, High-Speed,

and Full-Speed.

■Supports up to 16 IN and 16 OUT endpoints

■Supports the USB 3.0 Streams feature

■As a USB peripheral, CX3 supports USB-attached storage

(UAS), USB Video Class (UVC), and Media Transfer Protocol

(MTP) USB peripheral classes. As a USB peripheral, all other

device classes are supported only in pass-through mode when

handled entirely by a host processor external to the device.

Figure 2. USB Interface Signals

ReNumeration

Because of CX3’s soft configuration, one chip can take on the

identities of multiple distinct USB devices.

When first plugged into USB, CX3 enumerates automatically

with the Cypress Vendor ID (0x04B4) and downloads the

firmware and USB descriptors over the USB interface. The

downloaded firmware executes an electrical disconnect and

connect. CX3 enumerates again, this time as a device defined

by the downloaded information. This patented two-step process,

called ReNumeration, happens instantly when the device is

plugged in.

VBUS Overvoltage Protection

The maximum input voltage on CX3's VUSB pin is 6 V. A charger

can supply up to 9 V on VUSB. In this case, an external

overvoltage protection (OVP) device is required to protect CX3

from damage on VUSB. Figure 3 shows the system application

diagram with an OVP device connected on VUSB. Refer to DC

Specifications on page 17 for the operating range of VUSB.

Note: The VBUS pin of the USB connector should be connected

to the VUSB pin of CX3.

Figure 3. System Diagram with OVP Device For VUSB

EZ-USB CX3

VUSB

USB Interface

SSRX-

SSRX+

SSTX-

SSTX+

D-

D+

POWER SUBSYSTEM

USB Connector

EZ-USB CX3

USB-Port

VUSB

GND

SSRX-

SSRX+

SSTX-

SSTX+

D-

D+

VDD

VDDIO1

CVDDQ

VDDIO2

VDDIO3

AVDD

OVP device

U3TXVDDQ

U3RXVDDQ

CYUSB306X

Document Number: 001-87516 Rev. *N Page 7 of 41

MIPI CSI-2 RX Interface

The Mobile Industry Processor Interface (MIPI) association

defined the Camera Serial Interface 2 (CSI-2) standard to enable

image data to be sent on high-bandwidth serial lines.

CX3 implements a MIPI CSI-2 Receiver with the following

features:

1. It can receive clock and data in 1, 2, 3, or 4 lanes.

(CYUSB3065 part supports up to four lanes; CYUSB3064 part

supports up to two lanes)

2. Up to 1 Gbps of data on each CSI lane is supported (total

maximum bandwidth should not exceed 2.4 Gbps).

3. Video formats such as RAW8/10/12/14, YUV422 (CCIR/ITU

8/10-bit), RGB888/666/565, and User-Defined 8-bit are

supported

4. A CCI interface (compatible with 100-kHz or 400-kHz I2C

interface with 7-bit addressing) is provided to configure the

sensor.

5. GPIOs are available for synchronization of external flash or

lighting system with image sensors to illuminate the scene

that improves the image quality by improving Signal to noise

ratio.

6. GPIOs can also be used to synchronize the image sensor with

external events, so that image can be captured based on

external event.

7. Serial interfaces (such as I2C, I2S, SPI, UART) are available

to implement camera functions such as Auto focus and Pan,

Tilt, Zoom (PTZ)

Additional Outputs

In addition to the standard MIPI CSI-2 signals, the following three

additional outputs are provided:

1. XRST: this can be used to reset the image sensor

2. XSHUTDOWN: this pin can be used to put the sensor to a

standby/shutdown mode

3. MCLK: this pin can provide the clock output. It can be used

only for testing the image sensor. For production, use an

external clock generator as clock input for image sensors.

CPU

CX3 has an on-chip 32-bit, 200-MHz ARM926EJ-S core CPU.

The core has direct access to 16 kB of Instruction Tightly

Coupled Memory (TCM) and 8 kB of data TCM. The

ARM926EJ-S core provides a JTAG interface for firmware

debugging.

CX3 offers the following advantages:

■Integrates 512 KB of embedded SRAM for code and data and

8 kB of instruction cache and data cache.

■Implements efficient and flexible DMA connectivity between the

various peripherals (such as, USB, CSI-2 Rx, I2S, SPI, and

UART), requiring firmware only to configure data accesses

between peripherals, which are then managed by the DMA

fabric.

■Allows easy application development on industry-standard

development tools for ARM926EJ-S.

Examples of the CX3 firmware are available with the Cypress

EZ-USB CX3 Development Kit. Software APIs that can be ported

to an external processor are available with the Cypress EZ-USB

CX3 Software Development Kit.

JTAG Interface

CX3’s JTAG interface has a standard five-pin interface to

connect to a JTAG debugger in order to debug firmware through

the CPU-core's on-chip-debug circuitry.

Industry-standard debugging tools for the ARM926EJ-S core

can be used for the CX3 application development.

Other Interfaces

CX3 supports the following serial peripherals:

■UART

■I2C

■I2S

■SPI

The CYUSB306X Pin List on page 15 shows the details of how

these interfaces are mapped.

UART Interface

The UART interface of CX3 supports full-duplex communication.

It includes the signals noted in Table 1.

The UART is capable of generating a range of baud rates, from

300 bps to 4608 Kbps, selectable by the firmware. If flow control

is enabled, then CX3's UART only transmits data when the CTS

input is asserted. In addition to this, CX3's UART asserts the RTS

output signal, when it is ready to receive data.

I2C Interface

CX3’s I2C interface is compatible with the I2C Bus Specification

Revision 3. This I2C interface is capable of operating only as I2C

master; therefore, it may be used to communicate with other I2C

slave devices. For example, CX3 may boot from an EEPROM

connected to the I2C interface, as a selectable boot option.

CX3’s I2C Master Controller also supports multi-master mode

functionality.

The power supply for the I2C interface is VDDIO1, which is a

separate power domain from the other serial peripherals. This

gives the I2C interface the flexibility to operate at a different

voltage than the other serial interfaces.

The I2C controller supports bus frequencies of 400 kHz, and

1 MHz. When VDDIO1 is 1.8 V, 2.5 V, or 3.3 V, the operating

frequencies supported are 400 kHz and 1 MHz. The I2C

Table 1. UART Interface Signals

Signal Description

TX Output signal

RX Input signal

CTS Flow control

RTS Flow control

PMODE[2:0

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Document Number: 001-87516 Rev. *N Page 8 of 41

controller supports the clock-stretching feature to enable slower

devices to exercise flow control.

The I2C interface’s SCL and SDA signals require external pull-up

resistors. The pull-up resistors must be connected to VDDIO1.

Note: I2C addresses with the pattern 0x0000111x are used inter-

nally and no slave devices with those addresses should be

connected to the bus.

I2S Interface

CX3 has an I2S port to support external audio codec devices.

CX3 functions as I2S Master as transmitter only. The I2S

interface consists of four signals: clock line (I2S_CLK), serial

data line (I2S_SD), word select line (I2S_WS), and master

system clock (I2S_MCLK). CX3 can generate the system clock

as an output on I2S_MCLK or accept an external system clock

input on I2S_MCLK.

The sampling frequencies supported by the I2S interface are

8 kHz, 16 kHz, 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, and 192 kHz.

SPI Interface

CX3 supports an SPI Master interface on the Serial Peripherals

port. The maximum operation frequency is 33 MHz.

The SPI controller supports four modes of SPI communication

(see SPI Timing Specification on page 25 for details on the

modes) with the Start-Stop clock. This controller is a

single-master controller with a single automated SSN control. It

supports transaction sizes ranging from 4 bits to 32 bits.

Boot Options

CX3 can load boot images from various sources, selected by the

configuration of the PMODE pins. Following are the CX3 boot

options:

■Boot from USB

■Boot from I2C

■Boot from SPI

❐Cypress SPI flash parts supported are S25FS064S (64-Mbit),

S25FS128S (128-Mbit) and S25LFL064L (64-Mbit).

❐W25Q32FW (32-Mbit) is also supported.

Reset

Hard Reset

A hard reset is initiated by asserting the RESET# pin on CX3.

The specific reset sequence and timing requirements are

detailed in Figure 11 on page 27 and Table 18 on page 27. All

I/Os are tristated during a hard reset.

An additional reset pin called MIPI_RESET is provided that

resets the MIPI CSI-2 core. It should be pulled down with a

resistor for normal operation.

Soft Reset

There are two types of Soft Reset:

■CPU Reset – The CPU Program Counter is reset. Firmware

does not need to be reloaded following a CPU Reset.

■Whole Device Reset – This reset is identical to Hard Reset.

The firmware must be reloaded following a Whole Device

Reset.

Table 2. CX3 Booting Options

PMODE[2:0][1] Boot From

F11 USB boot

F1F I2C, On failure, USB boot is enabled

1FF I2C only

0F1 SPI, On failure, USB boot is enabled

Note

1. F indicates Floating.

CYUSB306X

Document Number: 001-87516 Rev. *N Page 9 of 41

Clocking

CX3 requires two clocks for normal operation:

1. A 19.2-MHz clock to be connected at the CLKIN pin

2. A 6-MHz to 40-MHz clock to be connected at the REFCLK pin

Clock inputs to CX3 must meet the phase noise and jitter require-

ments specified in Table 3.

The input clock frequency is independent of the clock and data

rate of the CX3 core or any of the device interfaces (including the

CSI-2 Rx Port). The internal PLL applies the appropriate

clock-multiply option depending on the input frequency.

Note: REFCLK and CLKIN must have either separate clock

inputs or if the same source is used, the clock must be passed

through a buffer with two outputs and then connected to the clock

pins.

32-kHz Watchdog Timer Clock Input

CX3 includes a watchdog timer. The watchdog timer can be used

to interrupt the ARM926EJ-S core, automatically wake up the

CX3 in Standby mode, and reset the ARM926EJ-S core. The

watchdog timer runs a 32-kHz clock, which may be optionally

supplied from an external source on a dedicated CX3 pin.

The firmware can disable the watchdog timer.

Tab le 4 provides the requirements for the optional 32-kHz clock

input

Table 3. CX3 Input Clock Specifications

Parameter Description Specification Units

Min Max

Phase noise

100-Hz offset – –75 dB

1-kHz offset – –104 dB

10-kHz offset – –120 dB

100-kHz offset – –128 dB

1-MHz offset – –130 dB

Maximum frequency deviation – – 150 ppm

Duty cycle – 30 70 %

Overshoot – – 3 %

Undershoot – – –3 %

Rise time/fall time – – 3 ns

Table 4. 32-kHz Clock Input Requirements

Parameter Min Max Units

Duty cycle 40 60 %

Frequency deviation – ±200 ppm

Rise time/fall time – 200 ns

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Document Number: 001-87516 Rev. *N Page 10 of 41

Power

CX3 has the following power supply domains:

■IO_VDDQ: This is a group of independent supply domains for

digital I/Os.

❐VDDIO1: GPIO, I2C, JTAG, XRST, XSHUTDOWN and REF-

CLK

❐VDDIO2: UART and I2S (except MCLK)

❐VDDIO3: I2S_MCLK and SPI

❐CVDDQ: CLKIN

❐VDD_MIPI: MIPI CSI-2 clock and data lanes

■VDD: This is the supply voltage for the logic core. The nominal

supply-voltage level is 1.2 V. This supplies the core logic

circuits. The same supply must also be used for the following:

❐AVDD: This is the 1.2 V supply for the PLL, crystal oscillator,

and other core analog circuits.

❐U3TXVDDQ/U3RXVDDQ: These are the 1.2 V supply volt-

ages for the USB 3.0 interface.

■VUSB: This is the 4 V to 6 V power supply for the USB I/O and

analog circuits. This supply powers the USB transceiver

through CX3’s internal voltage regulator. VUSB is internally

regulated to 3.3 V.

Note: The different power supplies have to be powered on or off

in a specific sequence as illustrated in Figure 4.

Power Modes

CX3 supports the following power modes:

■Normal mode: This is the full-functional operating mode. The

internal CPU clock and the internal PLLs are enabled in this

mode.

❐Normal operating power consumption does not exceed the

sum of ICC Core max and ICC USB max (see DC

Specifications on page 17 for current consumption

specifications).

❐The I/O power supplies VDDIO2 and VDDIO3 can be turned off

when the corresponding interface is not in use. VDDIO1 should

never be turned off for normal operation.

■Low-power modes (see Table 5 on page 11):

❐Suspend mode with USB 3.0 PHY enabled

❐Standby mode

❐Core power-down mode

Figure 4. Power-up Sequence

VUSB

(VBUS)

VDD

(VDD, AVDD,

VDD_MIPI)

VDDIO1

CVDDQ, VDDIO2,

VDDIO3

CLK_IN, REFCLK

RESET#

MIPI_RESET

>= 1 ms

XRST

(Image Sensor RESET)

User programmable

in firmware

<= 10 ms

CYUSB306X

Document Number: 001-87516 Rev. *N Page 11 of 41

Table 5. Entry and Exit Methods for Low-Power Modes

Low-Power Mode Characteristics Methods of Entry Methods of Exit

Suspend Mode with

USB 3.0 PHY

Enabled

■Power consumption in this mode does not

exceed ISB1

■USB 3.0 PHY is enabled and is in U3 mode

(one of the suspend modes defined by the

USB 3.0 specification). This one block

alone is operational with its internal clock,

while all other clocks are shut down

■All I/Os maintain their previous state

■Power supply for the wakeup source and

core power must be retained. All other

power domains can be turned on or off

individually

■The states of the configuration registers,

buffer memory, and all internal RAM are

maintained

■All transactions must be completed before

CX3 enters suspend mode (state of

outstanding transactions are not

preserved)

■The firmware resumes operation from

where it was suspended (except when

woken up by RESET# assertion) because

the program counter does not reset

■Firmware executing on

ARM926EJ-S core can put CX3 into

the suspend mode. For example, on

USB suspend condition, the firmware

may decide to put CX3 into suspend

mode

■D+ transitioning to low

or high

■D- transitioning to low

or high

■Resume condition on

SSRX±

■Detection of VBUS

■Level detect on

UART_CTS

(programmable

polarity)

■Assertion of RESET#

Standby Mode

■The power consumption in this mode does

not exceed ISB3

■All configuration register settings and

program/data RAM contents are

preserved. However, data in the buffers or

other parts of the data path, if any, is not

guaranteed. Therefore, the external

processor should take care that the data

needed is read before putting CX3 into the

standby mode

■The program counter is reset after waking

up from the standby mode

■GPIO pins maintain their configuration

■Internal PLL is turned off

■USB transceiver is turned off

■ARM926EJ-S core is powered down.

Upon wakeup, the core re-starts and runs

the program stored in the program/data

RAM

■Power supply for the wakeup source and

core power must be retained. All other

power domains can be turned on or off

individually

■The firmware executing on

ARM926EJ-S core or external

processor configures the appropriate

■Detection of VBUS

■Level detect on

UART_CTS

(programmable

polarity)

■Assertion of RESET#

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Document Number: 001-87516 Rev. *N Page 12 of 41

Core Power-down

Mode

■The power consumption in this mode does

not exceed ISB4

■Core power is turned off

■All buffer memory, configuration registers,

and the program RAM do not maintain

state. After exiting this mode, reload the

firmware

■In this mode, all other power domains can

be turned on or off individually

■Turn off VDD

■Reapply VDD

■Assertion of RESET#

Table 5. Entry and Exit Methods for Low-Power Modes (continued)

Low-Power Mode Characteristics Methods of Entry Methods of Exit

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Document Number: 001-87516 Rev. *N Page 13 of 41

Configuration Options

Configuration options are available for specific usage models.

Contact Cypress Marketing (usb3@cypress.com) for details.

Digital I/Os

CX3 has internal firmware-controlled pull-up or pull-down

resistors on all digital I/O pins. An internal 50-k resistor pulls

the pins high, while an internal 10-k resistor pulls the pins low

to prevent them from floating. The I/O pins may have the

following states:

■Tristated (High-Z)

■Weak pull-up (via internal 50 k)

■Pull-down (via internal 10 k)

■Hold (I/O hold its value) when in low-power modes

■The JTAG TDI, TMC, and TRST# signals have fixed 50-k

internal pull-ups, and the TCK signal has a fixed 10-k

pull-down resistor.

All unused I/Os should be pulled high by using the internal

pull-up resistors. All unused outputs should be left floating. All

I/Os can be driven at full-strength, three-quarter strength,

half-strength, or quarter-strength. These drive strengths are

configured separately for each interface.

GPIOs

CX3 provides 12 pins for general purpose I/O (for example, can

be used for lighting, sync-in, sync-out and so on). See Pin

Configuration on page 14 for pinout details.

All GPIO pins support an external load of up to 16 pF for every

pin.

EMI

CX3 can meet EMI requirements outlined by FCC 15B (USA)

and EN55022 (Europe) for consumer electronics at system level.

CX3 can tolerate reasonable EMI, conducted by the aggressor,

outlined by these specifications and continue to function as

expected.

System-level ESD

CX3 has built-in ESD protection on the D+, D–, and GND pins

on the USB interface. The ESD protection levels provided on

these ports are:

■±2.2-kV human body model (HBM) based on JESD22-A114

specification

■±6-kV contact discharge and ±8-kV air gap discharge based

on IEC61000-4-2 level 3A using external system-level

protection devices

■± 8-kV contact discharge and ±15-kV air gap discharge based

on IEC61000-4-2 level 4C using external system-level

protection devices

This protection ensures that the device continues to function

after ESD events up to the levels stated in this section.

The SSRX+, SSRX–, SSTX+, and SSTX– pins only have up to

±2.2-kV HBM internal ESD protection.

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CYUSB306X

Document Number: 001-87516 Rev. *N Page 14 of 41

Pin Configuration

Legend

Figure 5. CX3 Ball Map (Top View)

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

U3VSSQ U3RXVDDQ SSRXM SSRXP SSTXP SSTXM AVDD VSS DP DM GPIO[24]

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11

VDDIO3 VSS GPIO[23] GPIO[21] U3TXVDDQ CVDDQ AVSS VSS VSS VDD TRST#

C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11

SPI_SSN /

GPIO[54]

SPI_MISO /

GPIO[55] VDD GPIO[26] RESET# GPIO[18] GPIO[19] GPIO[22] GPIO[45] TDO I2S_MCLK

/ GPIO[57]

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11

I2S_CLK /

GPIO[50]

I2S_SD /

GPIO[51]

I2S_WS /

GPIO[52]

SPI_SCK /

GPIO[53]

SPI_MOSI /

GPIO[56] CLKIN_32 CLKIN VSS I2C_SCL I2C_SDA GPIO[17]

E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11

UART_CTS /

GPIO[47] VSS VDDIO2 UART_RX /

GPIO[49]

UART_TX /

GPIO[48] GPIO[20] TDI TMS VDD VUSB VSS

F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11

DNU REFCLK GPIO[44] XRST UART_RTS /

GPIO[46] TCK DNU DNU DNU DNU VDD

G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11

VSS XSHUTDOW

NMCLK PMODE[0] /

GPIO[30] GPIO[25] HSYNC_test DNU DNU DNU DNU VSS

H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11

VDD DNU DNU PMODE[1] /

GPIO[31] VSYNC_test MIPI RESET DNU PCLK_test DNU DNU VDDIO1

J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11

DNU DNU DNU DNU MIPI_D0P MIPI_D1P1

1. Unused MIPI input data lanes to be connected to GND.

MIPI_CP MIPI_D2P1, 2 MIPI_D2N1, 2

2. The signals MIPI_D2N, MIPI_D2P, MIPI_D3N, and MIPI_D3P are not available in the CYUSB3064 part. These pins should be left "open" in the customer board.

DNU VDD

K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11

DNU DNU VSS VSS MIPI_D0N MIPI_D1N1MIPI_CN MIPI_D3N1, 2 DNU DNU DNU

L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11

VSS VSS VSS PMODE[2] /

GPIO[32] VDD_MIPI VSS VDD MIPI_D3P1, 2 VDDIO1 DNU VSS

Ground

USB PHY power supply; Clock power supply

Power supply

CYUSB306X

Document Number: 001-87516 Rev. *N Page 15 of 41

Pin Description

Table 6. CYUSB306X Pin List

CX3

Pin# Pin name I/O

F10 DNU I/O

F9 DNU I/O

F7 DNU I/O

G10 DNU I/O

G9 DNU I/O

F8 DNU I/O

H10 DNU I/O

H9 DNU I/O

J10 DNU I/O

H7 DNU I/O

K11 DNU I/O

L10 DNU I/O

K10 DNU I/O

K9 DNU I/O

G7 DNU I/O

G8 DNU I/O

K2 DNU I/O

J4 DNU I/O

K1 DNU I/O

J2 DNU I/O

J3 DNU I/O

J1 DNU I/O

H2 DNU I/O

H3 DNU I/O

G6 HSYNC_test I/O

H5 VSYNC_test I/O

H8 PCLK_test I/O

VDDIO1 Power Domain

D11 GPIO[17] I/O

C6 GPIO[18] I/O

C7 GPIO[19] I/O

E6 GPIO[20] I/O

B4 GPIO[21] I/O

C8 GPIO[22] I/O

B3 GPIO[23] I/O

A11 GPIO[24] I/O

G5 GPIO[25] I/O

C4 GPIO[26] I/O

F3 GPIO[44] I/O

C9 GPIO[45] I/O

G4 PMODE[0] / GPIO[30] I/O

H4 PMODE[1] / GPIO[31] I/O

L4 PMODE[2] / GPIO[32] I/O

F1 DNU I/O

H6 MIPI RESET I/O

C5 RESET# I

F4 XRST O

G2 XSHUTDOWN O

G3 MCLK O

VDDIO2 Power Domain

F5 UART_RTS / GPIO[46] I/O

E1 UART_CTS / GPIO[47] I/O

E5 UART_TX / GPIO[48] I/O

E4 UART_RX / GPIO[49] I/O

D1 I2S_CLK / GPIO[50] I/O

D2 I2S_SD / GPIO[51] I/O

D3 I2S_WS / GPIO[52] I/O

VDDIO3 Power Domain

D4 SPI_SCK / GPIO[53] I/O

C1 SPI_SSN / GPIO[54] I/O

C2 SPI_MISO / GPIO[55] I/O

D5 SPI_MOSI / GPIO[56] I/O

C11 I2S_MCLK / GPIO[57] I/O

USB Port (U3TXVDDQ/U3RXVDDQ

Power Domain)

A3 SSRXM I

A4 SSRXP I

A6 SSTXM O

A5 SSTXP O

USB Port (VUSB Power Domain)

A9 DP I/O

A10 DM I/O

VDDIO1 Power Domain

F2 REFCLK I

VDD_MIPI Power Domain

J7 MIPI_CP I

Table 6. CYUSB306X Pin List (continued)

CX3

Pin# Pin name I/O

CYUSB306X

Document Number: 001-87516 Rev. *N Page 16 of 41

K7 MIPI_CN I

J5 MIPI_D0P I

K5 MIPI_D0N I

J6 MIPI_D1P1I

K6 MIPI_D1N1I

J9 MIPI_D2N1, 2 I

J8 MIPI_D2P1, 2 I

L8 MIPI_D3P1, 2 I

K8 MIPI_D3N1, 2 I

CVDDQ Power Domain

D7 CLKIN I

D6 CLKIN_32 I

VDDIO1 Power Domain

D9 I2C_SCL I/O

D10 I2C_SDA I/O

E7 TDI I

C10 TDO O

B11 TRST# I

E8 TMS I

F6 TCK I

Power Domains

E10 VUSB PWR

A1 U3VSSQ PWR

H11 VDDIO1 PWR

L9 VDDIO1 PWR

E3 VDDIO2 PWR

B1 VDDIO3 PWR

B6 CVDDQ PWR

B5 U3TXVDDQ PWR

A2 U3RXVDDQ PWR

A7 AVDD PWR

B7 AVSS PWR

L5 VDD_MIPI PWR

B10 VDD PWR

J11 VDD PWR

C3 VDD PWR

E9 VDD PWR

F11 VDD PWR

H1 VDD PWR

Table 6. CYUSB306X Pin List (continued)

CX3

Pin# Pin name I/O

L7 VDD PWR

D8 VSS PWR

E2 VSS PWR

E11 VSS PWR

G1 VSS PWR

A8 VSS PWR

G11 VSS PWR

L1 VSS PWR

B8 VSS PWR

L6 VSS PWR

B2 VSS PWR

L11 VSS PWR

B9 VSS PWR

K4 VSS PWR

L3 VSS PWR

K3 VSS PWR

L2 VSS PWR

1. Unused MIPI input data lanes to be connected to GND.

2. The signals MIPI_D2N, MIPI_D2P, MIPI_D3N, and MIPI_D3P are not available

in the CYUSB3064 part. These pins should be left "open" in the customer

board.

Table 6. CYUSB306X Pin List (continued)

CX3

Pin# Pin name I/O

m m m m

CYUSB306X

Document Number: 001-87516 Rev. *N Page 17 of 41

Electrical Specifications

Absolute Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device.

Storage temperature ......................... ...... –65 °C to +150 °C

Supply voltage to ground potential

VDD, AVDDQ ................................................................. 1.25 V

VDDIO1, VDDIO2, VDDIO3 ............................................. ...3.6 V

U3TXVDDQ, U3RXVDDQ ......................................... .....1.25 V

DC input voltage to any input pin ...........................VCC + 0.3

DC voltage applied to

outputs in high Z state

(VCC is the corresponding I/O voltage) ..................VCC + 0.3

Maximum latch-up current ........................................ 140 mA

Maximum output short-circuit current

for all I/O configurations. (VOUT = 0 V) .................. –100 mA

Operating Conditions

TA (ambient temperature under bias)

Commercial .................................................. 0 °C to +70 °C

Industrial ................................................... –40 °C to +85 °C

VDD, AVDDQ, U3TXVDDQ, U3RXVDDQ

Supply voltage .............................................1.15 V to 1.25 V

VUSB supply voltage ..............................................4 V to 6 V

VDDIO1, VDDIO2, VDDIO3, CVDDQ

Supply voltage .................................................1.7 V to 3.6 V

DC Specifications

Table 7. DC Specifications

Parameter Description Min Max Units Notes

VDD Core voltage supply 1.15 1.25 V 1.2-V typical

AVDD Analog voltage supply 1.15 1.25 V 1.2-V typical

VDD_MIPI MIPI bridge D-PHY supply

voltage

1.15 1.25 V 1.2-V typical

VDDIO1 I2C, JTAG and GPIO power

domain

1.7 3.6 V 1.8-, 2.5-, and 3.3-V typical

VDDIO2 UART/I2S power supply domain 1.7 3.6 V 1.8-, 2.5-, and 3.3-V typical

VDDIO3 SPI/I2S power supply domain 1.7 3.6 V 1.8-, 2.5-, and 3.3-V typical

VUSB USB voltage supply 4 6 V 5-V typical

U3TXVDDQ USB 3.0 1.2-V supply 1.15 1.25 V 1.2-V typical. A 22-µF bypass capacitor is

required on this power supply.

U3RXVDDQ USB 3.0 1.2-V supply 1.15 1.25 V 1.2-V typical. A 22-µF bypass capacitor is

required on this power supply.

CVDDQ Clock voltage supply 1.7 3.6 V 1.8-, 3.3-V typical

VIH1 Input HIGH voltage 1 0.625 × VCC VCC + 0.3 V For 2.0 V  VCC  3.6 V (except USB and

MIPI CSI-2 pins).VCC is the corresponding

I/O voltage supply.

VIH2 Input HIGH voltage 2 VCC – 0.4 VCC + 0.3 V For 1.7 V  VCC 2.0 V

(except USB USB and MIPI CSI-2 pins).VCC

is the corresponding I/O voltage supply.

VIL Input LOW voltage –0.3 0.25 × VCC VV

CC is the corresponding I/O voltage supply.

VOH Output HIGH voltage 0.9 × VCC –VI

OH (max) = –100 µA tested at quarter drive

strength. VCC is the corresponding I/O

voltage supply.

Refer toTable 8 on page 18 for values of IOH

at various drive strength and VCC.

VOL Output LOW voltage – 0.1 × VCC VI

OL (min) = +100 µA tested at quarter drive

strength. VCC is the corresponding I/O

voltage supply.

Refer toTable 8 on page 18 for values of IOL

at various drive strength and VCC.

CYUSB306X

Document Number: 001-87516 Rev. *N Page 18 of 41

IIX Input leakage current for all pins

except

SSTXP/SSXM/SSRXP/SSRXM

–1 1 µA All I/O signals held at VDDQ

(For I/Os with a pull-up or pull-down resistor

connected, the leakage current increases by

VDDQ/RPU or VDDQ/RPD)

IOZ Output High-Z leakage current for

all pins except SSTXP/ SSXM/

SSRXP/SSRXM and MIPI CSI-2

signals

–1 1 µA All I/O signals held at VDDQ

ICC Core Core and analog voltage

operating current

– 192 mA Total current through AVDD, VDD

ICC USB USB voltage supply operating

current

–60mA –

ISB1 Total suspend current during

suspend mode with USB 3.0 PHY

enabled

Core: 558.35 µA – µA Core Current is measured through VDD, AVDD

and VDD_MIPI.

I/O Current is measured through VDDIO1 to

VDDIO3.

USB Current is measured through VUSB,

U3TXVDDQ and U3RXVDDQ.

I/O: 4.58 µA – µA

USB: 4672 µA – µA

ISB3 Total standby current during core

power-down mode

Core: 148.31 µA – µA

I/O: 3.16 µA – µA

USB: 15.8 µA – µA

VRAMP Voltage ramp rate on core and I/O

supplies

0.2 12 V/ms Voltage ramp must be monotonic

VNNoise level permitted on VDD and

I/O supplies

– 100 mV Max p-p noise level permitted on all supplies

except AVDD

VN_AVDD Noise level permitted on AVDD

supply

– 20 mV Max p-p noise level permitted on AVDD

Table 7. DC Specifications (continued)

Parameter Description Min Max Units Notes

Table 8. IOH/IOL values for different drive strength and VDDIO values

VDDIO (V) VOH (V) VOL (V) Drive Strength IOH max (mA) IOL min (mA)

1.7 1.53 0.17 Quarter 1.02 2.21

Half 1.51 3.28

Three-Quarters 1.83 3.85

Full 2.28 4.73

2.5 2.25 0.25 Quarter 5.03 3.96

Half 7.38 5.84

Three-Quarters 8.89 6.89

Full 11.07 8.61

3.6 3.24 0.36 Quarter 7.80 5.74

Half 11.36 8.64

Three-Quarters 13.64 10.15

Full 16.92 12.67

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CYUSB306X

Document Number: 001-87516 Rev. *N Page 19 of 41

MIPI D-PHY Electrical Characteristics

Thermal Characteristics

Table 9. MIPI D-PHY Electrical Characteristics

Parameter Description Spec Unit

Min Nom Max

MIPI D-PHY RX DC Characteristics

VPIN Pin signal voltage range –50 – 1350 mV

VIH Logic 1 input voltage 880 – – mV

VIL Logic 0 input voltage – – 550 mV

VCMRX (DC) Common-mode voltage HS receiver mode 70 – 330 mV

VIDTH Differential input high threshold – 70 mV

VIDTL Differential input low threshold –70 – – mV

VIHHS Single-ended input high voltage – 460 mV

VILHS Single-ended input low voltage –40 – – mV

Table 10. Thermal Characteristics

Parameter Description Value Unit

TJ MAX Maximum Junction Temperature 125 C

JA Thermal resistance (junction to ambient) 24.4 C/W

JB Thermal resistance (junction to board) 17.27 C/W

JC Thermal resistance (junction to case) 5.5 C/W

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CYUSB306X

Document Number: 001-87516 Rev. *N Page 20 of 41

AC Timing Parameters

MIPI Data to Clock Timing Reference

Figure 6. MIPI CSI Signal Data to Clock Timing Reference

Reference Clock Specifications

TSETUP THOLD

0.5UIINST +

TSKEW

Reference Time

1 UIINST

TCLKp

CLKp

CLKn

Table 11. MIPI Data to Clock Timing Reference

Parameter Description Min Max Units

TSKEW Data to clock skew measured at the transmitter –0.15 0.15 UIINST

TSETUP Data to clock setup time at receiver 0.15 –UIINST

THOLD Clock to data hold time at receiver 0.15 –UIINST

UIINST One data bit time (instantaneous) 112.5 ns

TCLKp Period of dual data rate clock 225 ns

Table 12. Reference Clock Specifications

Parameter Description Min Max Units Notes

RefClk Reference clock frequency 640 MHz –

RefclkDutyCyl Duty cycle 40% 60% – –

RefClkPJ Reference clock input period jitter -100 100 ps –

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CYUSB306X

Document Number: 001-87516 Rev. *N Page 21 of 41

MIPI CSI Signal Low Power AC Characteristics

Figure 7. MIPI CSI bus Input Glitch Rejection

AC Specifications

2*TLPX 2*TLPX

eSPIKE

TMIN-RX TMIN-RX

VIH

VIL

Input

Output

Table 13. MIPI CSI Signal Low Power AC Characteristics

Parameter Description Min Max Units Notes

eSPIKE Input noise rejection –300 V.ps

Time-voltage integration of a spike above VIL

when being in LP-0 or below VIH when being in

LP-1 state.

An impulse less than this will not change the

receiver state.

TMIN-RX Minimum pulse width response 20 –ns An input pulse greater than this shall toggle the

output.

VINT peak interference amplitude –200 mV –

FINT Interference frequency 450 –MHz –

TLPX

Length of any low power state

period 50 –ns –

Table 14. AC Specifications

Parameter Description Min Max Units Details / Conditions

ΔVCMRX(HF)

Common-mode interference

beyond 450 MHz –100 mV ΔVCMRX(HF) is the peak amp. Of a sine wave

superimposed on the receiver inputs.

ΔVCMRX(LF)

Common-mode interference

beyond 50 - 450 MHz -50 50 mV

Excluding static ground shift of 50 mV.

Voltage difference compared to the DC average

common-mode potential

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CYUSB306X

Document Number: 001-87516 Rev. *N Page 22 of 41

Serial Peripherals Timing

I2C Timing

Figure 8. I2C Timing Definition

Table 15. I2C Timing Parameters[2]

Parameter Description Min Max Units

I2C Standard Mode Parameters

fSCL SCL clock frequency 0100 kHz

tHD:STA Hold time START condition 4 – µs

tLOW LOW period of the SCL 4.7 –µs

tHIGH HIGH period of the SCL 4 – µs

tSU:STA Setup time for a repeated START condition 4.7 –µs

tHD:DAT Data hold time 0 – µs

tSU:DAT Data setup time 250 –ns

trRise time of both SDA and SCL signals –1000 ns

tfFall time of both SDA and SCL signals –300 ns

tSU:STO Setup time for STOP condition 4 – µs

tBUF Bus free time between a STOP and START condition 4.7 –µs

tVD:DAT Data valid time –3.45 µs

tVD:ACK Data valid ACK –3.45 µs

tSP Pulse width of spikes that must be suppressed by input filter n/a n/a

Note

2. All parameters guaranteed by design and validated through characterization.

CYUSB306X

Document Number: 001-87516 Rev. *N Page 23 of 41

I2C Fast Mode Parameters

fSCL SCL clock frequency 0400 kHz

tHD:STA Hold time START condition 0.6 –µs

tLOW LOW period of the SCL 1.3 –µs

tHIGH HIGH period of the SCL 0.6 –µs

tSU:STA Setup time for a repeated START condition 0.6 –µs

tHD:DAT Data hold time 0 – µs

tSU:DAT Data setup time 100 –ns

trRise time of both SDA and SCL signals –300 ns

tfFall time of both SDA and SCL signals –300 ns

tSU:STO Setup time for STOP condition 0.6 –µs

tBUF Bus free time between a STOP and START condition 1.3 –µs

tVD:DAT Data valid time –0.9 µs

tVD:ACK Data valid ACK –0.9 µs

tSP Pulse width of spikes that must be suppressed by input filter 050 ns

I2C Fast Mode Plus Parameters

fSCL SCL clock frequency 01000 kHz

tHD:STA Hold time START condition 0.26 –µs

tLOW LOW period of the SCL 0.5 –µs

tHIGH HIGH period of the SCL 0.26 –µs

tSU:STA Setup time for a repeated START condition 0.26 –µs

tHD:DAT Data hold time 0 – µs

tSU:DAT Data setup time 50 –ns

trRise time of both SDA and SCL signals –120 ns

tfFall time of both SDA and SCL signals –120 ns

tSU:STO Setup time for STOP condition 0.26 –µs

tBUF Bus-free time between a STOP and START condition 0.5 –µs

tVD:DAT Data valid time –0.45 µs

tVD:ACK Data valid ACK –0.55 µs

tSP Pulse width of spikes that must be suppressed by input filter 050 ns

Table 15. I2C Timing Parameters[2] (continued)

Parameter Description Min Max Units

A 9‘

CYUSB306X

Document Number: 001-87516 Rev. *N Page 24 of 41

I2S Timing Diagram

Figure 9. I2S Transmit Cycle

tTR tTF tTL

tThd

tTd

tTH

SCK

SA,

WS (output)

Table 16. I2S Timing Parameters[3]

Parameter Description Min Max Units

tTI2S transmitter clock cycle tTR –ns

tTL I2S transmitter cycle LOW period 0.35 tTR –ns

tTH I2S transmitter cycle HIGH period 0.35 tTR –ns

tTR I2S transmitter rise time –0.15 tTR ns

tTF I2S transmitter fall time –0.15 tTR ns

tThd I2S transmitter data hold time 0 – ns

tTd I2S transmitter delay time –0.8 tTns

Note tT is selectable through clock gears. Max tTR is designed for 96-kHz codec at 32 bits to be 326 ns (3.072 MHz).

Note

3. All parameters guaranteed by design and validated through characterization.

CYUSB306X

Document Number: 001-87516 Rev. *N Page 25 of 41

SPI Timing Specification

Figure 10. SPI Timing

LSB

MSB

LSB

MSB

tlead

tsck

tsdd

thoi

twsck twsck

tlag

trf

tssnh

tdis

tsdi

tlead

tsck

twsck twsck

tlag

trf

tssnh

tsdi

tdis

tdv

thoi

SSN

(output)

SCK

(CPOL=0,

Output)

SCK

(CPOL=1,

Output)

MISO

(input)

MOSI

(output)

SSN

(output)

SCK

(CPOL=0,

Output)

SCK

(CPOL=1,

Output)

MISO

(input)

MOSI

(output)

SPI Master Timing for CPHA = 0

SPI Master Timing for CPHA = 1

tdi

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CYUSB306X

Document Number: 001-87516 Rev. *N Page 26 of 41

Table 17. SPI Timing Parameters[4]

Parameter Description Min Max Units

fop Operating frequency 033 MHz

tsck Cycle time 30 –ns

twsck Clock HIGH/LOW time 13.5 –ns

tlead SSN-SCK lead time 1/2 tsck[5] – 5 1.5 tsck[5] + 5 ns

tlag Enable lag time 0.5 1.5 tsck[5] + 5 ns

trf Rise/fall time – 8 ns

tsdd Output SSN to valid data delay time – 5 ns

tdv Output data valid time – 5 ns

tdi Output data invalid 0 – ns

tssnh Minimum SSN HIGH time 10 –ns

tsdi Data setup time input 8 – ns

thoi Data hold time input 0 – ns

tdis Disable data output on SSN HIGH 0 – ns

Notes

4. All parameters guaranteed by design and validated through characterization.

5. Depends on LAG and LEAD setting in the SPI_CONFIG register.

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CYUSB306X

Document Number: 001-87516 Rev. *N Page 27 of 41

Reset Sequence

CX3’s hard reset sequence requirements are specified in this section.

Figure 11. Reset Sequence

Table 18. Reset and Standby Timing Parameters

Parameter Definition Conditions Min (ms) Max (ms)

tRPW Minimum RESET# pulse width Clock Input 1 –

tRH Minimum HIGH on RESET# – 5 –

tRR

Reset recovery time (after which the boot loader begins

firmware download) Clock Input 1 –

tSBY

Time to enter standby/suspend mode (from the time

MAIN_CLOCK_EN/ MAIN_POWER_EN bit is set) – – 1

tWU Time to wakeup from standby Clock Input 1 –

tWH

Minimum time before standby/suspend source may be

reasserted – 5 –

VDD

(core)

xVDDQ

CLKIN

RESET#

Mandatory

Reset Pulse Hard Reset

tRPW

tRh

Standby/

Suspend

Source

Standby/Suspend source Is asserted

(MAIN_POWER_EN/ MAIN_CLK_EN bit is set)

Standby/Suspend

source Is deasserted

tSBY tWU

CLKIN must be stable before

exiting Standby/Suspend

tRR

tWH

CYUSB306X

Document Number: 001-87516 Rev. *N Page 28 of 41

Ordering Information

Ordering Code Definitions

Table 19. Ordering Information

Ordering Code MIPI CSI-2 Lanes Package Type Temperature Grade

CYUSB3065-BZXI 4 121-ball BGA Industrial

CYUSB3065-BZXC 4 121-ball BGA Commercial

CYUSB3064-BZXI 2 121-ball BGA Industrial

CYUSB3064-BZXC 2 121-ball BGA Commercial

Temperature Grade:

I = Industrial

C = Commercial

Pb-free

Package Type: BZ = 121-ball BGA

X = 4 for up to 2 MIPI CSI-2 lanes

X = 5 for up to 4 MIPI CSI-2 lanes

Density: Base part number for USB 3.0

Marketing Code: USB = USB Controller

Company ID: CY = Cypress

CY BZ

USB 3X

-I

06X

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CYUSB306X

Document Number: 001-87516 Rev. *N Page 29 of 41

Package Diagram

Figure 12. 121-ball BGA (10 × 10 × 1.7 mm) Package Outline, 001-87293

001-87293 **

CYUSB306X

Document Number: 001-87516 Rev. *N Page 30 of 41

Acronyms Document Conventions

Units of Measure

Table 20. Acronyms Used in this Document

Acronym Description

CSI - 2 Camera Serial Interface - 2

DMA Direct Memory Access

DNU Do Not Use

HNP Host Negotiation Protocol

MIPI Mobile Industry Processor Interface

MMC Multimedia Card

MTP Media Transfer Protocol

PLL Phase Locked Loop

PMIC Power Management IC

SD Secure Digital

SDIO Secure Digital Input / Output

SLC Single-Level Cell

SPI Serial Peripheral Interface

SRP Session Request Protocol

USB Universal Serial Bus

WLCSP Wafer Level Chip Scale Package

Table 21. Units of Measure

Symbol Unit of Measure

°C degree Celsius

Mbps Megabits per second

MBps Megabytes per second

MHz megahertz

µA microampere

µs microsecond

mA milliampere

ms millisecond

ns nanosecond

ohm

pF picofarad

Vvolt

CYUSB306X

Document Number: 001-87516 Rev. *N Page 31 of 41

Errata

This section describes the errata for CX3. Details include errata trigger conditions, scope of impact, available workaround, and silicon

revision applicability. Contact your local Cypress Sales Representative if you have questions.

Part Numbers Affected

Qualification Status

Product Status: Production

Errata Summary

The following table defines the errata applicability to available EZ-USB CX3 SuperSpeed USB Controller family devices.

Part Number Device Characteristics

CYUSB306x-xxxx All Variants

Items [Part Number] Silicon Revision Fix Status

1. Turning off VDDIO1 during Normal, Suspend, and Standby

modes causes the CX3 to stop working.

CYUSB306x-xxxx All Workaround provided

2. USB enumeration failure in USB boot mode when CX3 is

self-powered.

CYUSB306x-xxxx All Workaround provided

3. Extra ZLP is generated by the COMMIT action in the GPIF II

state.

CYUSB306x-xxxx All Workaround provided

4. Invalid PID Sequence in USB 2.0 ISOC data transfer. CYUSB306x-xxxx All Workaround provided

5. USB data transfer errors are seen when ZLP is followed by

data packet within same microframe.

CYUSB306x-xxxx All Workaround provided

6. Bus collision is seen when the I2C block is used as a master

in the I2C Multi-master configuration.

CYUSB306x-xxxx All Use CX3 in single-master

configuration

7. Low Power U1 Fast-Exit Issue with USB3.0 host controller. CYUSB306x-xxxx All Workaround provided

8. USB data corruption when operating on hosts with poor link

quality.

CYUSB306x-xxxx All Workaround provided

9. Device treats Rx Detect sequence from the USB 3.0 host as

a valid U1 exit LFPS burst.

CYUSB306x-xxxx All Workaround provided

10. I2C Data Valid (tVD:DAT) specification violation at 400 kHz

with a 40/60 duty cycle.

CYUSB306x-xxxx All No workaround needed

11. CX3 Device does not respond correctly to Port Capability

Request from Host after multiple power cycles.

CYUSB306x-xxxx All Workaround provided

nnnnnnnnnnnnnnnnnnn

CYUSB306X

Document Number: 001-87516 Rev. *N Page 32 of 41

1. Turning off VDDIO1 during Normal, Suspend, and Standby modes causes the CX3 to stop working.

■Problem Definition

Turning off the VDDIO1 during Normal, Suspend, and Standby modes will cause the CX3 to stop working.

■Parameters Affected

N/A

■Trigger Conditions

This condition is triggered when the VDDIO1 is turned off during Normal, Suspend, and Standby modes.

■Scope Of Impact

CX3 stops working.

■Workaround

VDDIO1 must stay on during Normal, Suspend, and Standby modes.

■Fix Status

No fix. Workaround is required.

2. USB enumeration failure in USB boot mode when CX3 is self-powered.

■Problem Definition

When CX3 is self-powered and not connected to the USB host, it enters low-power mode and does not wake up when connected

to USB host afterwards. This is because the bootloader does not check the VBUS pin on the connector to detect USB connection.

It expects that the USB bus is connected to the host when it is powered on.

■Parameters Affected

N/A

■Trigger Conditions

This condition is triggered when CX3 is self-powered in USB boot mode.

■Scope Of Impact

Device does not enumerate.

■Workaround

Reset the device after connecting to USB host.

■Fix Status

No fix. Workaround is required.

3. Extra ZLP is generated by the COMMIT action in the GPIF II state.

■Problem Definition

When COMMIT action is used in a GPIF-II state without IN_DATA action then an extra Zero Length Packet (ZLP) is committed

along with the data packets.

■Parameters Affected

N/A

■Trigger Conditions

This condition is triggered when COMMIT action is used in a state without IN_DATA action.

■Scope Of Impact

Extra ZLP is generated.

■Workaround

Use IN_DATA action along with COMMIT action in the same state.

■Fix Status

No fix. Workaround is required.

nnnnnnnnnnnnnnnnnnn

CYUSB306X

Document Number: 001-87516 Rev. *N Page 33 of 41

4. Invalid PID Sequence in USB 2.0 ISOC data transfer.

■Problem Definition

When the CX3 device is functioning as a high speed USB device with high bandwidth isochronous endpoints, the PID sequence

of the ISO data packets is governed solely by the isomult setting. The length of the data packet is not considered while generating

the PID sequence during each microframe. For example, even if a short packet is being sent on an endpoint with MULT set to 2;

the PID used will be DATA2.

■Parameters Affected

N/A

■Trigger Conditions

This condition is triggered when high bandwidth ISOC transfer endpoints are used.

■Scope Of Impact

ISOC data transfers failure.

■Workaround

This problem can be worked around by reconfiguring the endpoint with a lower isomult setting prior to sending short packets, and

then switching back to the original value.

■Fix Status

No fix. Workaround is required.

5. USB data transfer errors are seen when ZLP is followed by data packet within same microframe.

■Problem Definition

Some data transfer errors may be seen if a Zero Length Packet is followed very quickly (within one microframe or 125 µs) by

another data packet on a burst enabled USB IN endpoint operating at super speed.

■Parameters Affected

N/A

■Trigger Conditions

This condition is triggered in SuperSpeed transfer with ZLPs.

■Scope Of Impact

Data failure and lower data speed.

■Workaround

The solution is to ensure that some time is allowed to elapse between a ZLP and the next data packet on burst enabled USB IN

endpoints. If this cannot be ensured at the data source, the CyU3PDmaChannelSetSuspend() API can be used to suspend the

corresponding USB DMA socket on seeing the EOP condition. The channel operation can then be resumed as soon as the

suspend callback is received.

■Fix Status

No fix. Workaround is required.

6. Bus collision is seen when the I2C block is used as a master in the I2C Multi-master configuration.

■Problem Definition

When CX3 is used as a master in the I2C multi-master configuration, there can be occasional bus collisions.

■Parameters Affected

■Trigger Conditions

This condition is triggered only when the CX3 I2C block operates in Multi-master configuration.

■Scope Of Impact

The CX3 I2C block can transmit data when the I2C bus is not idle leading to bus collision.

■Workaround

Use CX3 as a single master.

■Fix Status

No fix.

nnnnnnnnnnnnnnnnnnn

CYUSB306X

Document Number: 001-87516 Rev. *N Page 34 of 41

7. Low Power U1 Fast-Exit Issue with USB3.0 host controller.

■Problem Definition

When CX3 device transitions from Low power U1 state to U0 state within 5 µs after entering U1 state, the device sometimes fails

to transition back to U0 state, resulting in USB Reset.

■Parameters Affected

■Trigger Conditions

This condition is triggered during low power transition mode.

■Scope Of Impact

Unexpected USB warm reset during data transfer.

■Workaround

This problem can be worked around in the FW by disabling LPM (Link Power Management) during data transfer.

■Fix Status

FW workaround is proven and reliable.

8. USB data corruption when operating on hosts with poor link quality.

■Problem Definition

If CX3 is operating on a USB 3.0 link with poor signal quality, the device could send corrupted data on any of the IN endpoints

(including the control endpoint).

■Parameters Affected

■Trigger Conditions

This condition is triggered when the USB3.0 link signal quality is very poor.

■Scope Of Impact

Data corruption in any of the IN endpoints (including the control endpoint).

■Workaround

The application firmware should perform an error recovery by stalling the endpoint on receiving CYU3P_USBEPSS_RESET_EVT

event (available only with SDK 1.3.3 and above), and then stop and restart DMA path when the CLEAR_FEATURE request is

received.

Note: For more details in application firmware, please refer to GpiftoUsb example available with FX3 SDK.

■Fix Status

FW Work-around is proven and reliable.

nnnnnnnnnnnnnnnnnnn

CYUSB306X

Document Number: 001-87516 Rev. *N Page 35 of 41

9. Device treats Rx Detect sequence from the USB 3.0 host as a valid U1 exit LFPS burst.

■Problem Definition

The USB 3.0 PHY in the CX3 device uses an electrical idle detector to determine whether LFPS is being received. The duration

for which the receiver does not see an electrical idle condition is timed to detect various LFPS bursts. This implementation causes

the device to treat an Rx Detect sequence from the USB host as a valid U1 exit LFPS burst.

■Parameters Affected

■Trigger Conditions

This condition is triggered when the USB host is initiating an Rx Detect sequence while the USB 3.0 Link State Machine on the

CX3 is in the U1 state. Since the host will only perform Rx Detect sequence in the RX Detect and U2 states, the error condition

is seen only in cases where the USB link on the host has moved into the U2 state while the link on CX3 is in the U1 state.

■Scope Of Impact

CX3 moves into Recovery prematurely leading to a Recovery failure followed by Warm Reset and USB re-enumeration. This

sequence can repeat multiple times resulting in data transfer failures.

■Workaround

CX3 can be configured to transition from U1 to U2 a few microseconds before the host does so. This will ensure that the link will

be in U2 on the device side before the host attempts any Rx Detect sequence; thereby preventing a false detection of U1 exit.

■Fix Status

Workaround is implemented in SDK library 1.3.4 and above.

10. I2C Data Valid (tVD:DAT) specification violation at 400 kHz with a 40/60 duty cycle.

■Problem Definition

I2C Data Valid (tVD:DAT) parameter at 400 kHz with a 40/60 duty cycle is 1.0625 µs, which exceeds the I2C specification limit of

0.9 µs.

■Parameters Affected

N/A

■Trigger Conditions

This violation occurs only at 400 kHz with a 40/60 duty cycle of the I2C clock.

■Scope Of Impact

Setup time (tSUDAT) is met with a huge margin for the transmitted data for 400 kHz and so tvd:DAT violation will not cause any data

integrity issues.

■Workaround

No workaround needed.

■Fix Status

No fix needed.

nnnnnnnnnnnnnnnnnnn

CYUSB306X

Document Number: 001-87516 Rev. *N Page 36 of 41

11. CX3 Device does not respond correctly to Port Capability Request from Host after multiple power cycles.

■Problem Definition

During multiple power cycles, sometimes the CX3 device does not respond correctly to the Port Capability request (Link Packet)

from the USB Controller. In view of this, CX3 does not get the subsequent Port Configuration request from the USB controller,

resulting in SS.Disabled state. The device fails to recover from this state and finally results in enumeration failure.

■Parameters Affected

N/A

■Trigger Conditions

This condition is triggered when the CX3 provides an incorrect response to the Port Capability request from the host.

■Scope Of Impact

Device fails to enumerate after multiple retries.

■Workaround

Since the host does not send the Port Configuration request to the CX3 device, it causes a Port Configuration request timeout

interrupt to be triggered in the device. This interrupt is handled in the FX3 SDK 1.3.4 onwards to generate and signal

CY_U3P_USB_EVENT_LMP_EXCH_FAIL event to the application. This event should be handled in the user application such

that it does a USB Interface Block Restart. Refer the Knowledge Base Article (KBA225778) for more details and the firmware

workaround example project.

■Fix Status

Suggested firmware work-around is proven and reliable.

aCYPRESS' ' maznnznwmomw 06x, EZ-USB®

CYUSB306X

Document Number: 001-87516 Rev. *N Page 37 of 41

Document History Page

Document Title: CYUSB306X, EZ-USB® CX3: MIPI CSI-2 to SuperSpeed USB Bridge Controller

Document Number: 001-87516

Revision ECN Orig. of

Change

Submission

Date Description of Change

** 3994736 KUMR 05/09/2013 New data sheet.

*A 4065766 KUMR 07/17/2013 Replaced “VBUS” and “VBATT” by “VUSB” in all instances across the

document.

Updated Logic Block Diagram.

Updated Pin Description:

Updated Table 6.

Updated DC Specifications:

Removed VBATT

, VBUS, VOH_MIPI, VOL_MIPI parameters and their details.

Added VUSB parameter and its details.

Changed maximum value of VRAMP parameter from 50 V/ms to 12 V/ms.

Updated to new template.

*B 4080302 KUMR 07/29/2013 Changed status from Final to Preliminary.

*C 4088328 KUMR 08/06/2013 Updated Pin Configuration:

Updated Figure 5.

*D 4113754 KUMR 09/04/2013 Updated Clocking:

Updated description (Added a Note at the bottom of section).

Updated Pin Description:

Updated Table 6.

Updated DC Specifications:

Updated details in “Description” column corresponding to VDDIO2, VDDIO3

parameters.

Changed maximum value of ICC Core parameter from 200 mA to 380 mA.

*E 4188453 KUMR 11/14/2013 Changed status from Preliminary to Final.

Updated Features:

Updated description.

Updated Applications:

Updated description.

Updated Logic Block Diagram.

Updated MIPI CSI-2 RX Interface:

Updated Additional Outputs:

Updated description.

Updated Reset:

Updated Soft Reset:

Updated description.

Updated Power.

Updated Power Modes.

Updated Table 5:

Updated details in “Methods of Entry” column corresponding to “Suspend

Mode with USB 3.0 PHY Enabled”.

Updated details in “Characteristics” column corresponding to “Standby Mode”.

Updated EMI:

Updated description.

Updated System-level ESD:

Updated description.

Updated Pin Configuration:

Updated Figure 5 (Updated details of G4, H4, L4, F1, F5, E1, E5, E4, D1, D2,

D3, D4, C1, C2, D5, C11 pins).

Updated Pin Description:

Updated Table 6:

Updated details in “Pin name” column for G4, H4, L4, F1, F5, E1, E5, E4, D1,

D2, D3, D4, C1, C2, D5, C11 pins.

aCYPRESS' ' mmnmwmmw 06x, EZ-USB®

CYUSB306X

Document Number: 001-87516 Rev. *N Page 38 of 41

*E (cont.) 4188453 KUMR 11/14/2013 Updated Absolute Maximum Ratings:

Removed “Ambient temperature with power applied” and its corresponding

details.

Removed “Static discharge voltage ESD protection levels” and its

corresponding details.

Removed “Latch-up current” and its corresponding details.

Added “Maximum latch-up current” and its corresponding details.

Updated DC Specifications:

Updated details in “Notes” column corresponding to VIH1 and VIH2 parameters.

Updated details in “Description” column corresponding to IOZ parameter.

Updated details in “Min” column corresponding to ISB1 and ISB3 parameters.

Updated details in “Notes” column corresponding to ISB1 and ISB3 parameters.

Added MIPI D-PHY Electrical Characteristics.

Updated AC Timing Parameters:

Updated MIPI Data to Clock Timing Reference:

Updated Figure 6.

Updated Table 11:

Added 1 ns under “Min” column corresponding to UIINST parameter.

Changed maximum value of TCLKp parameter from 2 ns to 25 ns.

Updated MIPI CSI Signal Low Power AC Characteristics:

Updated Figure 7.

Updated Serial Peripherals Timing:

Updated I2C Timing:

Updated Table 15:

Removed “(Not supported at I2C_VDDQ = 1.2 V)” in “I2C Fast Mode Plus

Parameters” sub-heading.

Updated Reset Sequence.

Updated Table 18:

Removed “Crystal Input” condition for tRPW, tRR, tWU parameters.

Updated Figure 11.

Updated Ordering Information:

Updated part numbers.

*F 4214952 RAJA 03/12/2014 Updated Features:

Updated description.

Updated Application Examples:

Updated Figure 1.

Updated Configuration Options:

Updated description (Added e-mail).

Updated Pin Description.

Updated Table 6 (caption only).

Updated AC Timing Parameters:

Updated MIPI CSI Signal Low Power AC Characteristics:

Updated Table 13:

Updated details in “Notes” column corresponding to eSPIKE parameter.

Updated to new template.

*G 4417040 KUMR 06/23/2014 Updated Power:

Updated description (Updated details corresponding to “IO_VDDQ” power

supply domain).

Updated DC Specifications:

Changed maximum value of ICC Core parameter 380 mA to 192 mA.

Document History Page (continued)

Document Title: CYUSB306X, EZ-USB® CX3: MIPI CSI-2 to SuperSpeed USB Bridge Controller

Document Number: 001-87516

Revision ECN Orig. of

Change

Submission

Date Description of Change

aCYPRESS' ' maznnznwmomw 06x, EZ-USB®

CYUSB306X

Document Number: 001-87516 Rev. *N Page 39 of 41

*H 4467092 RAJA 08/06/2014 Added CYUSB3064 part related information in all instances across the

document.

Updated Pin Configuration:

Updated Figure 5.

Added footnote 2.

Updated Pin Description:

Updated Table 6.

Updated Ordering Information:

Updated part numbers.

*I 4862446 RAGO 08/13/2015 Updated Pin Configuration:

Updated Figure 5.

Added footnote 1.

Updated Pin Description:

Updated Table 6.

*J 4974015 RAGO 10/19/2015 Added More Information.

*K 5283275 RAGO 05/24/2016 Updated to new template.

Completing Sunset Review.

*L 5464498 RAJA 06/22/2017 Updated Power:

Updated description.

Updated Operating Conditions:

Replaced “3.2 V” with “4 V” in Operating Conditions corresponding to “VUSB

supply voltage”.

Updated DC Specifications:

Changed minimum value of VUSB parameter from 3.2 V to 4 V.

Added Errata.

Updated to new template.

*M 6237413 HPPC 09/28/2018 Updated Features:

Updated description.

Updated More Information:

Updated description.

Updated Other Interfaces:

Updated I2S Interface:

Updated description.

Updated Boot Options:

Updated description.

Updated Electrical Specifications:

Updated Operating Conditions:

Added Commercial Temperature Range related information.

Updated DC Specifications:

Updated Table 7.

Added Ta bl e 8.

Added Thermal Characteristics.

Updated Errata:

Updated Errata Summary:

Updated description.

Added items “Low Power U1 Fast-Exit Issue with USB3.0 host controller.”,

“USB data corruption when operating on hosts with poor link quality.”, “Device

treats Rx Detect sequence from the USB 3.0 host as a valid U1 exit LFPS

burst.”, “I2C Data Valid (tVD:DAT) specification violation at 400 kHz with a 40/60

duty cycle.” and their corresponding details in the table.

Updated to new template.

Document History Page (continued)

Document Title: CYUSB306X, EZ-USB® CX3: MIPI CSI-2 to SuperSpeed USB Bridge Controller

Document Number: 001-87516

Revision ECN Orig. of

Change

Submission

Date Description of Change

oex, EZ-USB®

CYUSB306X

Document Number: 001-87516 Rev. *N Page 40 of 41

*N 6409378 HPPC 12/12/2018 Updated Errata:

Updated Errata Summary:

Updated description.

Added item “CX3 Device does not respond correctly to Port Capability Request

from Host after multiple power cycles.” and its corresponding details in the

table.

Document History Page (continued)

Document Title: CYUSB306X, EZ-USB® CX3: MIPI CSI-2 to SuperSpeed USB Bridge Controller

Document Number: 001-87516

Revision ECN Orig. of

Change

Submission

Date Description of Change

nnnnnnnnnnnnnnnnnnn

Document Number: 001-87516 Rev. *N Revised December 12, 2018 Page 41 of 41

EZ-USB® is a registered trademark of Cypress Semiconductor Corporation.

CYUSB306X

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